\PWM_2:PWMUDB:runmode_enable\/q |
\PWM_2:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 |
3.562 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell5 |
U(1,4) |
1 |
\PWM_2:PWMUDB:runmode_enable\ |
\PWM_2:PWMUDB:runmode_enable\/clock_0 |
\PWM_2:PWMUDB:runmode_enable\/q |
1.250 |
Route |
|
1 |
\PWM_2:PWMUDB:runmode_enable\ |
\PWM_2:PWMUDB:runmode_enable\/q |
\PWM_2:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 |
2.312 |
datapathcell2 |
U(1,4) |
1 |
\PWM_2:PWMUDB:sP8:pwmdp:u0\ |
|
HOLD |
0.000 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\PWM_1:PWMUDB:runmode_enable\/q |
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 |
3.565 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell4 |
U(1,4) |
1 |
\PWM_1:PWMUDB:runmode_enable\ |
\PWM_1:PWMUDB:runmode_enable\/clock_0 |
\PWM_1:PWMUDB:runmode_enable\/q |
1.250 |
Route |
|
1 |
\PWM_1:PWMUDB:runmode_enable\ |
\PWM_1:PWMUDB:runmode_enable\/q |
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 |
2.315 |
datapathcell1 |
U(0,4) |
1 |
\PWM_1:PWMUDB:sP8:pwmdp:u0\ |
|
HOLD |
0.000 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 |
Net_151/main_0 |
4.364 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
controlcell2 |
U(1,4) |
1 |
\PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\ |
\PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/clock |
\PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 |
2.040 |
Route |
|
1 |
\PWM_2:PWMUDB:ctrl_enable\ |
\PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 |
Net_151/main_0 |
2.324 |
macrocell1 |
U(1,4) |
1 |
Net_151 |
|
HOLD |
0.000 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 |
\PWM_2:PWMUDB:runmode_enable\/main_0 |
4.364 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
controlcell2 |
U(1,4) |
1 |
\PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\ |
\PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/clock |
\PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 |
2.040 |
Route |
|
1 |
\PWM_2:PWMUDB:ctrl_enable\ |
\PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 |
\PWM_2:PWMUDB:runmode_enable\/main_0 |
2.324 |
macrocell5 |
U(1,4) |
1 |
\PWM_2:PWMUDB:runmode_enable\ |
|
HOLD |
0.000 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 |
\PWM_1:PWMUDB:runmode_enable\/main_0 |
4.683 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
controlcell1 |
U(0,4) |
1 |
\PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\ |
\PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/clock |
\PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 |
2.040 |
Route |
|
1 |
\PWM_1:PWMUDB:ctrl_enable\ |
\PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 |
\PWM_1:PWMUDB:runmode_enable\/main_0 |
2.643 |
macrocell4 |
U(1,4) |
1 |
\PWM_1:PWMUDB:runmode_enable\ |
|
HOLD |
0.000 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 |
Net_67/main_0 |
4.693 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
controlcell1 |
U(0,4) |
1 |
\PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\ |
\PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/clock |
\PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 |
2.040 |
Route |
|
1 |
\PWM_1:PWMUDB:ctrl_enable\ |
\PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 |
Net_67/main_0 |
2.653 |
macrocell2 |
U(1,4) |
1 |
Net_67 |
|
HOLD |
0.000 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\PWM_2:PWMUDB:sP8:pwmdp:u0\/cl0_comb |
Net_151/main_1 |
5.433 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
datapathcell2 |
U(1,4) |
1 |
\PWM_2:PWMUDB:sP8:pwmdp:u0\ |
\PWM_2:PWMUDB:sP8:pwmdp:u0\/clock |
\PWM_2:PWMUDB:sP8:pwmdp:u0\/cl0_comb |
3.130 |
Route |
|
1 |
\PWM_2:PWMUDB:compare1\ |
\PWM_2:PWMUDB:sP8:pwmdp:u0\/cl0_comb |
Net_151/main_1 |
2.303 |
macrocell1 |
U(1,4) |
1 |
Net_151 |
|
HOLD |
0.000 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb |
Net_67/main_1 |
5.445 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
datapathcell1 |
U(0,4) |
1 |
\PWM_1:PWMUDB:sP8:pwmdp:u0\ |
\PWM_1:PWMUDB:sP8:pwmdp:u0\/clock |
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb |
3.130 |
Route |
|
1 |
\PWM_1:PWMUDB:compare1\ |
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb |
Net_67/main_1 |
2.315 |
macrocell2 |
U(1,4) |
1 |
Net_67 |
|
HOLD |
0.000 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\PWM_2:PWMUDB:sP8:pwmdp:u0\/z0_comb |
\PWM_2:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 |
5.552 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
datapathcell2 |
U(1,4) |
1 |
\PWM_2:PWMUDB:sP8:pwmdp:u0\ |
\PWM_2:PWMUDB:sP8:pwmdp:u0\/clock |
\PWM_2:PWMUDB:sP8:pwmdp:u0\/z0_comb |
3.270 |
datapathcell2 |
U(1,4) |
1 |
\PWM_2:PWMUDB:sP8:pwmdp:u0\ |
\PWM_2:PWMUDB:sP8:pwmdp:u0\/z0_comb |
\PWM_2:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 |
2.282 |
datapathcell2 |
U(1,4) |
1 |
\PWM_2:PWMUDB:sP8:pwmdp:u0\ |
|
HOLD |
0.000 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb |
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 |
5.555 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
datapathcell1 |
U(0,4) |
1 |
\PWM_1:PWMUDB:sP8:pwmdp:u0\ |
\PWM_1:PWMUDB:sP8:pwmdp:u0\/clock |
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb |
3.270 |
datapathcell1 |
U(0,4) |
1 |
\PWM_1:PWMUDB:sP8:pwmdp:u0\ |
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb |
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 |
2.285 |
datapathcell1 |
U(0,4) |
1 |
\PWM_1:PWMUDB:sP8:pwmdp:u0\ |
|
HOLD |
0.000 |
Clock |
|
|
|
|
Skew |
0.000 |
|