Static Timing Analysis

Project : Lab2
Build Time : 01/23/13 16:52:26
Device : CY8C5868AXI-LP035
Temperature : -40C - 85/125C
Vdda : 5.00
Vddd : 5.00
Vio0 : 5.00
Vio1 : 5.00
Vio2 : 5.00
Vio3 : 5.00
Voltage : 5.0
Vusb : 5.00
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_DelSig_1_Ext_CP_Clk(routed) ADC_DelSig_1_Ext_CP_Clk(routed) 1.000 MHz 1.000 MHz N/A
ADC_DelSig_1_theACLK(fixed-function) ADC_DelSig_1_theACLK(fixed-function) 131.148 kHz 131.148 kHz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
ADC_DelSig_1_Ext_CP_Clk CyMASTER_CLK 1.000 MHz 1.000 MHz N/A
ADC_DelSig_1_theACLK CyMASTER_CLK 131.148 kHz 131.148 kHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A