Static Timing Analysis

Project : Lab1
Build Time : 01/23/13 13:51:47
Device : CY8C5868AXI-LP035
Temperature : -40C - 85/125C
Vdda : 5.00
Vddd : 5.00
Vio0 : 5.00
Vio1 : 5.00
Vio2 : 5.00
Vio3 : 5.00
Voltage : 5.0
Vusb : 5.00
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
Clock_1 CyMASTER_CLK 40.000 kHz 40.000 kHz 56.641 MHz
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 25000ns(40 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 56.641 MHz 17.655 24982.345
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,4) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb 3.850
datapathcell1 U(0,4) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 2.285
datapathcell1 U(0,4) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ SETUP 11.520
Clock Skew 0.000
\PWM_2:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_2:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 56.651 MHz 17.652 24982.348
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,4) 1 \PWM_2:PWMUDB:sP8:pwmdp:u0\ \PWM_2:PWMUDB:sP8:pwmdp:u0\/clock \PWM_2:PWMUDB:sP8:pwmdp:u0\/z0_comb 3.850
datapathcell2 U(1,4) 1 \PWM_2:PWMUDB:sP8:pwmdp:u0\ \PWM_2:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_2:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 2.282
datapathcell2 U(1,4) 1 \PWM_2:PWMUDB:sP8:pwmdp:u0\ SETUP 11.520
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 66.291 MHz 15.085 24984.915
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(1,4) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.315
datapathcell1 U(0,4) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ SETUP 11.520
Clock Skew 0.000
\PWM_2:PWMUDB:runmode_enable\/q \PWM_2:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 66.304 MHz 15.082 24984.918
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(1,4) 1 \PWM_2:PWMUDB:runmode_enable\ \PWM_2:PWMUDB:runmode_enable\/clock_0 \PWM_2:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_2:PWMUDB:runmode_enable\ \PWM_2:PWMUDB:runmode_enable\/q \PWM_2:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.312
datapathcell2 U(1,4) 1 \PWM_2:PWMUDB:sP8:pwmdp:u0\ SETUP 11.520
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_67/main_1 86.919 MHz 11.505 24988.495
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,4) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 5.680
Route 1 \PWM_1:PWMUDB:compare1\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_67/main_1 2.315
macrocell2 U(1,4) 1 Net_67 SETUP 3.510
Clock Skew 0.000
\PWM_2:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_151/main_1 87.009 MHz 11.493 24988.507
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,4) 1 \PWM_2:PWMUDB:sP8:pwmdp:u0\ \PWM_2:PWMUDB:sP8:pwmdp:u0\/clock \PWM_2:PWMUDB:sP8:pwmdp:u0\/cl0_comb 5.680
Route 1 \PWM_2:PWMUDB:compare1\ \PWM_2:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_151/main_1 2.303
macrocell1 U(1,4) 1 Net_151 SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 Net_67/main_0 114.377 MHz 8.743 24991.257
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,4) 1 \PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\ \PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \PWM_1:PWMUDB:ctrl_enable\ \PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 Net_67/main_0 2.653
macrocell2 U(1,4) 1 Net_67 SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \PWM_1:PWMUDB:runmode_enable\/main_0 114.508 MHz 8.733 24991.267
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,4) 1 \PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\ \PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \PWM_1:PWMUDB:ctrl_enable\ \PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \PWM_1:PWMUDB:runmode_enable\/main_0 2.643
macrocell4 U(1,4) 1 \PWM_1:PWMUDB:runmode_enable\ SETUP 3.510
Clock Skew 0.000
\PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 Net_151/main_0 118.850 MHz 8.414 24991.586
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,4) 1 \PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\ \PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \PWM_2:PWMUDB:ctrl_enable\ \PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 Net_151/main_0 2.324
macrocell1 U(1,4) 1 Net_151 SETUP 3.510
Clock Skew 0.000
\PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \PWM_2:PWMUDB:runmode_enable\/main_0 118.850 MHz 8.414 24991.586
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,4) 1 \PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\ \PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \PWM_2:PWMUDB:ctrl_enable\ \PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \PWM_2:PWMUDB:runmode_enable\/main_0 2.324
macrocell5 U(1,4) 1 \PWM_2:PWMUDB:runmode_enable\ SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\PWM_2:PWMUDB:runmode_enable\/q \PWM_2:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 3.562
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(1,4) 1 \PWM_2:PWMUDB:runmode_enable\ \PWM_2:PWMUDB:runmode_enable\/clock_0 \PWM_2:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_2:PWMUDB:runmode_enable\ \PWM_2:PWMUDB:runmode_enable\/q \PWM_2:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.312
datapathcell2 U(1,4) 1 \PWM_2:PWMUDB:sP8:pwmdp:u0\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 3.565
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(1,4) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.315
datapathcell1 U(0,4) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ HOLD 0.000
Clock Skew 0.000
\PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 Net_151/main_0 4.364
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,4) 1 \PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\ \PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.040
Route 1 \PWM_2:PWMUDB:ctrl_enable\ \PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 Net_151/main_0 2.324
macrocell1 U(1,4) 1 Net_151 HOLD 0.000
Clock Skew 0.000
\PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \PWM_2:PWMUDB:runmode_enable\/main_0 4.364
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,4) 1 \PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\ \PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.040
Route 1 \PWM_2:PWMUDB:ctrl_enable\ \PWM_2:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \PWM_2:PWMUDB:runmode_enable\/main_0 2.324
macrocell5 U(1,4) 1 \PWM_2:PWMUDB:runmode_enable\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \PWM_1:PWMUDB:runmode_enable\/main_0 4.683
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,4) 1 \PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\ \PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.040
Route 1 \PWM_1:PWMUDB:ctrl_enable\ \PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \PWM_1:PWMUDB:runmode_enable\/main_0 2.643
macrocell4 U(1,4) 1 \PWM_1:PWMUDB:runmode_enable\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 Net_67/main_0 4.693
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,4) 1 \PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\ \PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.040
Route 1 \PWM_1:PWMUDB:ctrl_enable\ \PWM_1:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 Net_67/main_0 2.653
macrocell2 U(1,4) 1 Net_67 HOLD 0.000
Clock Skew 0.000
\PWM_2:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_151/main_1 5.433
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,4) 1 \PWM_2:PWMUDB:sP8:pwmdp:u0\ \PWM_2:PWMUDB:sP8:pwmdp:u0\/clock \PWM_2:PWMUDB:sP8:pwmdp:u0\/cl0_comb 3.130
Route 1 \PWM_2:PWMUDB:compare1\ \PWM_2:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_151/main_1 2.303
macrocell1 U(1,4) 1 Net_151 HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_67/main_1 5.445
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,4) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 3.130
Route 1 \PWM_1:PWMUDB:compare1\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_67/main_1 2.315
macrocell2 U(1,4) 1 Net_67 HOLD 0.000
Clock Skew 0.000
\PWM_2:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_2:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 5.552
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,4) 1 \PWM_2:PWMUDB:sP8:pwmdp:u0\ \PWM_2:PWMUDB:sP8:pwmdp:u0\/clock \PWM_2:PWMUDB:sP8:pwmdp:u0\/z0_comb 3.270
datapathcell2 U(1,4) 1 \PWM_2:PWMUDB:sP8:pwmdp:u0\ \PWM_2:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_2:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 2.282
datapathcell2 U(1,4) 1 \PWM_2:PWMUDB:sP8:pwmdp:u0\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 5.555
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,4) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb 3.270
datapathcell1 U(0,4) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 2.285
datapathcell1 U(0,4) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ Clock_1
Source Destination Delay (ns)
Net_151/q Pin_2(0)_PAD 29.297
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(1,4) 1 Net_151 Net_151/clock_0 Net_151/q 1.250
Route 1 Net_151 Net_151/q Net_70/main_0 2.314
macrocell3 U(1,4) 1 Net_70 Net_70/main_0 Net_70/q 3.350
Route 1 Net_70 Net_70/q Pin_2(0)/pin_input 6.637
iocell2 P6[2] 1 Pin_2(0) Pin_2(0)/pin_input Pin_2(0)/pad_out 15.746
Route 1 Pin_2(0)_PAD Pin_2(0)/pad_out Pin_2(0)_PAD 0.000
Clock Clock path delay 0.000