|
Loading plugins phase: Elapsed time ==> 0s.214ms
|
|
Initializing data phase: Elapsed time ==> 0s.000ms
|
|
<CYPRESSTAG name="CyDsfit arguments...">
|
|
cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -p C:\Users\pmad\Desktop\BLE Workshop\Labs\Completed Labs\BLE Lab 1_1\BLE Lab 1_1.cydsn\BLE Lab 1_1.cyprj -d CY8C4247LQI-BL483 -s C:\Users\pmad\Desktop\BLE Workshop\Labs\Completed Labs\BLE Lab 1_1\BLE Lab 1_1.cydsn\Generated_Source\PSoC4 -- -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE</CYPRESSTAG>
|
|
<CYPRESSTAG name="Design elaboration results...">
|
|
</CYPRESSTAG>
|
|
Elaboration phase: Elapsed time ==> 4s.962ms
|
|
<CYPRESSTAG name="HDL generation results...">
|
|
</CYPRESSTAG>
|
|
HDL generation phase: Elapsed time ==> 0s.050ms
|
|
<CYPRESSTAG name="Synthesis results...">
|
|
|
|
| | | | | | |
|
|
_________________
|
|
-| |-
|
|
-| |-
|
|
-| |-
|
|
-| CYPRESS |-
|
|
-| |-
|
|
-| |- Warp Verilog Synthesis Compiler: Version 6.3 IR 41
|
|
-| |- Copyright (C) 1991-2001 Cypress Semiconductor
|
|
|_______________|
|
|
| | | | | | |
|
|
|
|
======================================================================
|
|
Compiling: BLE Lab 1_1.v
|
|
Program : C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\warp\bin/warp.exe
|
|
Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\pmad\Desktop\BLE Workshop\Labs\Completed Labs\BLE Lab 1_1\BLE Lab 1_1.cydsn\BLE Lab 1_1.cyprj -dcpsoc3 BLE Lab 1_1.v -verilog
|
|
======================================================================
|
|
|
|
======================================================================
|
|
Compiling: BLE Lab 1_1.v
|
|
Program : C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\warp\bin/warp.exe
|
|
Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\pmad\Desktop\BLE Workshop\Labs\Completed Labs\BLE Lab 1_1\BLE Lab 1_1.cydsn\BLE Lab 1_1.cyprj -dcpsoc3 BLE Lab 1_1.v -verilog
|
|
======================================================================
|
|
|
|
======================================================================
|
|
Compiling: BLE Lab 1_1.v
|
|
Program : vlogfe
|
|
Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\pmad\Desktop\BLE Workshop\Labs\Completed Labs\BLE Lab 1_1\BLE Lab 1_1.cydsn\BLE Lab 1_1.cyprj -dcpsoc3 -verilog BLE Lab 1_1.v
|
|
======================================================================
|
|
|
|
vlogfe V6.3 IR 41: Verilog parser
|
|
Fri May 29 00:00:19 2015
|
|
|
|
|
|
======================================================================
|
|
Compiling: BLE Lab 1_1.v
|
|
Program : vpp
|
|
Options : -yv2 -q10 BLE Lab 1_1.v
|
|
======================================================================
|
|
|
|
vpp V6.3 IR 41: Verilog Pre-Processor
|
|
Fri May 29 00:00:19 2015
|
|
|
|
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\warp\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v'
|
|
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\warp\..\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0\or_v1_0.v'
|
|
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\warp\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0\cy_constant_v1_0.v'
|
|
|
|
vpp: No errors.
|
|
|
|
Library 'work' => directory 'lcpsoc3'
|
|
General_symbol_table
|
|
General_symbol_table
|
|
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\warp\lib\common\std.vhd'.
|
|
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\warp\lib\common\cypress.vhd'.
|
|
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\warp\lib\common\work\cypress.vif'.
|
|
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'.
|
|
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'.
|
|
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'.
|
|
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.
|
|
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.
|
|
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.
|
|
Using control file 'BLE Lab 1_1.ctl'.
|
|
|
|
vlogfe: No errors.
|
|
|
|
|
|
======================================================================
|
|
Compiling: BLE Lab 1_1.v
|
|
Program : tovif
|
|
Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\pmad\Desktop\BLE Workshop\Labs\Completed Labs\BLE Lab 1_1\BLE Lab 1_1.cydsn\BLE Lab 1_1.cyprj -dcpsoc3 -verilog BLE Lab 1_1.v
|
|
======================================================================
|
|
|
|
tovif V6.3 IR 41: High-level synthesis
|
|
Fri May 29 00:00:20 2015
|
|
|
|
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\warp\lib\common\std.vhd'.
|
|
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\warp\lib\common\cypress.vhd'.
|
|
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\warp\lib\common\work\cypress.vif'.
|
|
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'.
|
|
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'.
|
|
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'.
|
|
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.
|
|
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.
|
|
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.
|
|
Linking 'C:\Users\pmad\Desktop\BLE Workshop\Labs\Completed Labs\BLE Lab 1_1\BLE Lab 1_1.cydsn\codegentemp\BLE Lab 1_1.ctl'.
|
|
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v'.
|
|
Linking 'C:\Users\pmad\Desktop\BLE Workshop\Labs\Completed Labs\BLE Lab 1_1\BLE Lab 1_1.cydsn\codegentemp\BLE Lab 1_1.v'.
|
|
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0\or_v1_0.v'.
|
|
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0\cy_constant_v1_0.v'.
|
|
|
|
tovif: No errors.
|
|
|
|
|
|
======================================================================
|
|
Compiling: BLE Lab 1_1.v
|
|
Program : topld
|
|
Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\pmad\Desktop\BLE Workshop\Labs\Completed Labs\BLE Lab 1_1\BLE Lab 1_1.cydsn\BLE Lab 1_1.cyprj -dcpsoc3 -verilog BLE Lab 1_1.v
|
|
======================================================================
|
|
|
|
topld V6.3 IR 41: Synthesis and optimization
|
|
Fri May 29 00:00:20 2015
|
|
|
|
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\warp\lib\common\std.vhd'.
|
|
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\warp\lib\common\cypress.vhd'.
|
|
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\warp\lib\common\work\cypress.vif'.
|
|
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'.
|
|
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'.
|
|
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'.
|
|
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.
|
|
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.
|
|
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.
|
|
Linking 'C:\Users\pmad\Desktop\BLE Workshop\Labs\Completed Labs\BLE Lab 1_1\BLE Lab 1_1.cydsn\codegentemp\BLE Lab 1_1.ctl'.
|
|
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v'.
|
|
Linking 'C:\Users\pmad\Desktop\BLE Workshop\Labs\Completed Labs\BLE Lab 1_1\BLE Lab 1_1.cydsn\codegentemp\BLE Lab 1_1.v'.
|
|
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0\or_v1_0.v'.
|
|
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0\cy_constant_v1_0.v'.
|
|
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\warp\lib\lcpsoc3\stdlogic\cpsoc3.vif'.
|
|
|
|
----------------------------------------------------------
|
|
Detecting unused logic.
|
|
----------------------------------------------------------
|
|
User names
|
|
Net_97
|
|
\BLE:Net_55\
|
|
|
|
|
|
Deleted 2 User equations/components.
|
|
Deleted 0 Synthesized equations/components.
|
|
|
|
------------------------------------------------------
|
|
Alias Detection
|
|
------------------------------------------------------
|
|
Aliasing \PWM:Net_66\ to \PWM:Net_75\
|
|
Aliasing \PWM:Net_82\ to \PWM:Net_75\
|
|
Aliasing \PWM:Net_72\ to \PWM:Net_75\
|
|
Aliasing tmpOE__Red_LED_net_0 to \PWM:Net_69\
|
|
Aliasing zero to \PWM:Net_75\
|
|
Aliasing one to \PWM:Net_69\
|
|
Removing Lhs of wire \PWM:Net_81\[1] = Net_43[13]
|
|
Removing Lhs of wire \PWM:Net_66\[4] = \PWM:Net_75\[2]
|
|
Removing Lhs of wire \PWM:Net_82\[5] = \PWM:Net_75\[2]
|
|
Removing Lhs of wire \PWM:Net_72\[6] = \PWM:Net_75\[2]
|
|
Removing Rhs of wire tmpOE__Red_LED_net_0[15] = \PWM:Net_69\[3]
|
|
Removing Rhs of wire zero[19] = \PWM:Net_75\[2]
|
|
Removing Lhs of wire one[20] = tmpOE__Red_LED_net_0[15]
|
|
|
|
------------------------------------------------------
|
|
Aliased 0 equations, 7 wires.
|
|
------------------------------------------------------
|
|
|
|
----------------------------------------------------------
|
|
Circuit simplification
|
|
----------------------------------------------------------
|
|
|
|
Substituting virtuals - pass 1:
|
|
|
|
|
|
----------------------------------------------------------
|
|
Circuit simplification results:
|
|
|
|
Expanded 0 signals.
|
|
Turned 0 signals into soft nodes.
|
|
Maximum default expansion cost was set at 3.
|
|
----------------------------------------------------------
|
|
|
|
topld: No errors.
|
|
|
|
CYPRESS_DIR : C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\warp
|
|
Warp Program : C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\warp\bin/warp.exe
|
|
Warp Arguments : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya "-.fftprj=C:\Users\pmad\Desktop\BLE Workshop\Labs\Completed Labs\BLE Lab 1_1\BLE Lab 1_1.cydsn\BLE Lab 1_1.cyprj" -dcpsoc3 "BLE Lab 1_1.v" -verilog
|
|
</CYPRESSTAG>
|
|
Warp synthesis phase: Elapsed time ==> 0s.254ms
|
|
<CYPRESSTAG name="Fitter results...">
|
|
<CYPRESSTAG name="Fitter startup details...">
|
|
cyp3fit: V3.2.0.706, Family: PSoC3, Started at: Friday, 29 May 2015 00:00:20
|
|
Options: -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\pmad\Desktop\BLE Workshop\Labs\Completed Labs\BLE Lab 1_1\BLE Lab 1_1.cydsn\BLE Lab 1_1.cyprj -d CY8C4247LQI-BL483 BLE Lab 1_1.v -verilog
|
|
</CYPRESSTAG>
|
|
<CYPRESSTAG name="Design parsing">
|
|
Design parsing phase: Elapsed time ==> 0s.013ms
|
|
</CYPRESSTAG>
|
|
<CYPRESSTAG name="Tech mapping">
|
|
<CYPRESSTAG name="Initial Mapping" icon="FILE_RPT_TECHM">
|
|
Assigning clock BLE_LFCLK to clock LFCLK because it is a pass-through
|
|
<CYPRESSTAG name="Global Clock Selection" icon="FILE_RPT_TECHM">
|
|
Fixed Function Clock 7: Automatic-assigning clock 'Clock_1'. Signal=Net_43_ff7
|
|
<CYPRESSTAG name="UDB Clock/Enable Remapping Results">
|
|
</CYPRESSTAG>
|
|
</CYPRESSTAG>
|
|
<CYPRESSTAG name="Duplicate Macrocell detection">
|
|
</CYPRESSTAG>
|
|
</CYPRESSTAG>
|
|
<CYPRESSTAG name="Duplicate Macrocell detection">
|
|
</CYPRESSTAG>
|
|
<CYPRESSTAG name="Design Equations" icon="FILE_RPT_EQUATION">
|
|
|
|
------------------------------------------------------------
|
|
Design Equations
|
|
------------------------------------------------------------
|
|
<CYPRESSTAG name="Pin listing">
|
|
|
|
------------------------------------------------------------
|
|
Pin listing
|
|
------------------------------------------------------------
|
|
|
|
Pin : Name = Red_LED(0)
|
|
Attributes:
|
|
In Group/Port: True
|
|
In Sync Option: AUTO
|
|
Out Sync Option: NOSYNC
|
|
Interrupt generated: False
|
|
Interrupt mode: NONE
|
|
Drive mode: CMOS_OUT
|
|
VTrip: EITHER
|
|
Slew: FAST
|
|
Input Sync needed: False
|
|
Output Sync needed: False
|
|
SC shield enabled: False
|
|
POR State: ANY
|
|
LCD Mode: COMMON
|
|
Register Mode: RegComb
|
|
CaSense Mode: NEITHER
|
|
Treat as pin: True
|
|
Is OE Registered: False
|
|
Uses Analog: False
|
|
Can contain Digital: True
|
|
Is SIO: False
|
|
SIO Output Buf: NONREGULATED
|
|
SIO Input Buf: SINGLE_ENDED
|
|
SIO HiFreq: LOW
|
|
SIO Hyst: DISABLED
|
|
SIO Vtrip: MULTIPLIER_0_5
|
|
SIO RefSel: VCC_IO
|
|
Required Capabilitites: DIGITAL
|
|
Initial Value: 1
|
|
IO Voltage: 0
|
|
PORT MAP (
|
|
pa_out => Red_LED(0)__PA ,
|
|
input => Net_94 ,
|
|
pad => Red_LED(0)_PAD );
|
|
Properties:
|
|
{
|
|
}
|
|
</CYPRESSTAG>
|
|
<CYPRESSTAG name="Macrocell listing" icon="FILE_RPT_EQUATION">
|
|
</CYPRESSTAG>
|
|
<CYPRESSTAG name="Datapath listing">
|
|
</CYPRESSTAG>
|
|
<CYPRESSTAG name="Status register listing">
|
|
</CYPRESSTAG>
|
|
<CYPRESSTAG name="StatusI register listing">
|
|
</CYPRESSTAG>
|
|
<CYPRESSTAG name="Sync listing">
|
|
</CYPRESSTAG>
|
|
<CYPRESSTAG name="Control register listing">
|
|
</CYPRESSTAG>
|
|
<CYPRESSTAG name="Count7 listing">
|
|
</CYPRESSTAG>
|
|
<CYPRESSTAG name="DRQ listing">
|
|
</CYPRESSTAG>
|
|
<CYPRESSTAG name="Interrupt listing">
|
|
|
|
------------------------------------------------------------
|
|
Interrupt listing
|
|
------------------------------------------------------------
|
|
|
|
interrupt: Name =\BLE:bless_isr\
|
|
PORT MAP (
|
|
interrupt => \BLE:Net_15\ );
|
|
Properties:
|
|
{
|
|
int_type = "10"
|
|
}
|
|
</CYPRESSTAG>
|
|
</CYPRESSTAG>
|
|
<CYPRESSTAG name="Technology mapping summary" expanded>
|
|
|
|
------------------------------------------------------------
|
|
Technology mapping summary
|
|
------------------------------------------------------------
|
|
|
|
Resource Type : Used : Free : Max : % Used
|
|
============================================================
|
|
Digital clock dividers : 0 : 4 : 4 : 0.00%
|
|
Pins : 5 : 33 : 38 : 13.16%
|
|
UDB Macrocells : 0 : 32 : 32 : 0.00%
|
|
UDB Unique Pterms : 0 : 64 : 64 : 0.00%
|
|
UDB Datapath Cells : 0 : 4 : 4 : 0.00%
|
|
UDB Status Cells : 0 : 4 : 4 : 0.00%
|
|
UDB Control Cells : 0 : 4 : 4 : 0.00%
|
|
Interrupts : 1 : 31 : 32 : 3.13%
|
|
Comparator/Opamp Fixed Blocks : 0 : 4 : 4 : 0.00%
|
|
SAR Fixed Blocks : 0 : 1 : 1 : 0.00%
|
|
CSD Fixed Blocks : 0 : 1 : 1 : 0.00%
|
|
CapSense Blocks : 0 : 1 : 1 : 0.00%
|
|
8-bit CapSense IDACs : 0 : 1 : 1 : 0.00%
|
|
7-bit CapSense IDACs : 0 : 1 : 1 : 0.00%
|
|
Temperature Sensors : 0 : 1 : 1 : 0.00%
|
|
Low Power Comparators : 0 : 2 : 2 : 0.00%
|
|
TCPWM Blocks : 1 : 3 : 4 : 25.00%
|
|
Serial Communication Blocks : 0 : 2 : 2 : 0.00%
|
|
Segment LCD Blocks : 0 : 1 : 1 : 0.00%
|
|
Bluetooth Low Energy Blocks : 1 : 0 : 1 : 100.00%
|
|
</CYPRESSTAG>
|
|
Technology Mapping: Elapsed time ==> 0s.038ms
|
|
Tech mapping phase: Elapsed time ==> 0s.077ms
|
|
</CYPRESSTAG>
|
|
<CYPRESSTAG name="Analog Placement">
|
|
<CYPRESSTAG name="Analog Placement">
|
|
Elapsed time ==> 0.0126907s
|
|
</CYPRESSTAG>
|
|
Analog Placement phase: Elapsed time ==> 0s.048ms
|
|
</CYPRESSTAG>
|
|
<CYPRESSTAG name="Analog Routing">
|
|
<CYPRESSTAG name="Analog Routing">
|
|
Route success=True, Iterations=1 Elapsed=0.0022390 secs
|
|
</CYPRESSTAG>
|
|
Analog Routing phase: Elapsed time ==> 0s.004ms
|
|
</CYPRESSTAG>
|
|
<CYPRESSTAG name="Analog Code Generation">
|
|
============ Analog Final Answer Routes ============
|
|
Dump of CyAnalogRoutingResultsDB
|
|
Map of net to items {
|
|
}
|
|
Map of item to net {
|
|
}
|
|
Mux Info {
|
|
}
|
|
Analog Code Generation phase: Elapsed time ==> 0s.146ms
|
|
</CYPRESSTAG>
|
|
<CYPRESSTAG name="Digital Placement">
|
|
<CYPRESSTAG name="Detailed placement messages">
|
|
I2659: No Constrained paths were found. The placer will run in non-timing driven mode.
|
|
I2076: Total run-time: 0.3 sec.
|
|
|
|
</CYPRESSTAG>
|
|
<CYPRESSTAG name="PLD Packing">
|
|
<CYPRESSTAG name="PLD Packing Summary">
|
|
No PLDs were packed.
|
|
</CYPRESSTAG>
|
|
PLD Packing: Elapsed time ==> 0s.001ms
|
|
</CYPRESSTAG>
|
|
<CYPRESSTAG name="Partitioning">
|
|
<CYPRESSTAG name="Initial Partitioning Summary">
|
|
Initial Partitioning Summary not displayed at this verbose level.</CYPRESSTAG>
|
|
<CYPRESSTAG name="Final Partitioning Summary">
|
|
Final Partitioning Summary not displayed at this verbose level.</CYPRESSTAG>
|
|
Partitioning: Elapsed time ==> 0s.013ms
|
|
</CYPRESSTAG>
|
|
<CYPRESSTAG name="Simulated Annealing">
|
|
Annealing: Elapsed time ==> 0s.001ms
|
|
<CYPRESSTAG name="Simulated Annealing Results">
|
|
The seed used for moves was 114161200.
|
|
Inital cost was 9, final cost is 9 (0.00% improvement).</CYPRESSTAG>
|
|
</CYPRESSTAG>
|
|
<CYPRESSTAG name="Final Placement Summary">
|
|
|
|
------------------------------------------------------------
|
|
Final Placement Summary
|
|
------------------------------------------------------------
|
|
|
|
Resource Type : Count : Avg Inputs : Avg Outputs
|
|
========================================================
|
|
UDB : 0 : 0.00 : 0.00
|
|
<CYPRESSTAG name="Final Placement Details">
|
|
<CYPRESSTAG name="Component Details">
|
|
|
|
------------------------------------------------------------
|
|
Component Placement Details
|
|
------------------------------------------------------------
|
|
UDB [UDB=(0,0)] is empty.
|
|
UDB [UDB=(0,1)] is empty.
|
|
UDB [UDB=(1,0)] is empty.
|
|
UDB [UDB=(1,1)] is empty.
|
|
Intr hod @ [IntrHod=(0)]:
|
|
Intr@ [IntrHod=(0)][IntrId=(12)]
|
|
interrupt: Name =\BLE:bless_isr\
|
|
PORT MAP (
|
|
interrupt => \BLE:Net_15\ );
|
|
Properties:
|
|
{
|
|
int_type = "10"
|
|
}
|
|
Port 0 is empty
|
|
Port 1 is empty
|
|
Port 2 contains the following IO cells:
|
|
[IoId=6]:
|
|
Pin : Name = Red_LED(0)
|
|
Attributes:
|
|
In Group/Port: True
|
|
In Sync Option: AUTO
|
|
Out Sync Option: NOSYNC
|
|
Interrupt generated: False
|
|
Interrupt mode: NONE
|
|
Drive mode: CMOS_OUT
|
|
VTrip: EITHER
|
|
Slew: FAST
|
|
Input Sync needed: False
|
|
Output Sync needed: False
|
|
SC shield enabled: False
|
|
POR State: ANY
|
|
LCD Mode: COMMON
|
|
Register Mode: RegComb
|
|
CaSense Mode: NEITHER
|
|
Treat as pin: True
|
|
Is OE Registered: False
|
|
Uses Analog: False
|
|
Can contain Digital: True
|
|
Is SIO: False
|
|
SIO Output Buf: NONREGULATED
|
|
SIO Input Buf: SINGLE_ENDED
|
|
SIO HiFreq: LOW
|
|
SIO Hyst: DISABLED
|
|
SIO Vtrip: MULTIPLIER_0_5
|
|
SIO RefSel: VCC_IO
|
|
Required Capabilitites: DIGITAL
|
|
Initial Value: 1
|
|
IO Voltage: 0
|
|
PORT MAP (
|
|
pa_out => Red_LED(0)__PA ,
|
|
input => Net_94 ,
|
|
pad => Red_LED(0)_PAD );
|
|
Properties:
|
|
{
|
|
}
|
|
|
|
Port 3 is empty
|
|
Port 4 is empty
|
|
Port 5 is empty
|
|
Port 6 is empty
|
|
Clock group 0:
|
|
M0S8 Clock Block @ [FFB(Clock,0)]:
|
|
m0s8clockblockcell: Name =ClockBlock
|
|
PORT MAP (
|
|
hfclk => ClockBlock_HFCLK ,
|
|
imo => ClockBlock_IMO ,
|
|
ext => ClockBlock_EXTCLK ,
|
|
sysclk => ClockBlock_SYSCLK ,
|
|
eco => ClockBlock_ECO ,
|
|
ilo => ClockBlock_ILO ,
|
|
lfclk => ClockBlock_LFCLK ,
|
|
wco => ClockBlock_WCO ,
|
|
dsi_in_0 => ClockBlock_Routed1 ,
|
|
ff_div_7 => Net_43_ff7 );
|
|
Properties:
|
|
{
|
|
}
|
|
PM group 0: empty
|
|
SPC group 0: empty
|
|
WDT group 0: empty
|
|
FSS group 0: empty
|
|
Low Power Comparator group 0: empty
|
|
Serial Communication Block group 0: empty
|
|
CSD Fixed Block group 0: empty
|
|
8-bit CapSense IDAC group 0: empty
|
|
7-bit CapSense IDAC group 0: empty
|
|
TCPWM Block group 0:
|
|
Tcpwm Block @ [FFB(TCPWM,0)]:
|
|
m0s8tcpwmcell: Name =\PWM:cy_m0s8_tcpwm_1\
|
|
PORT MAP (
|
|
clock => Net_43_ff7 ,
|
|
capture => zero ,
|
|
count => tmpOE__Red_LED_net_0 ,
|
|
reload => zero ,
|
|
stop => zero ,
|
|
start => zero ,
|
|
tr_underflow => Net_88 ,
|
|
tr_overflow => Net_87 ,
|
|
tr_compare_match => Net_89 ,
|
|
line_out => Net_15 ,
|
|
line_out_compl => Net_94 ,
|
|
interrupt => Net_86 );
|
|
Properties:
|
|
{
|
|
cy_registers = ""
|
|
}
|
|
Comparator/Opamp Fixed Block group 0: empty
|
|
Temperature Sensor group 0: empty
|
|
SAR Fixed Block group 0: empty
|
|
Segment LCD Block group 0: empty
|
|
CLK_GEN group 0:
|
|
M0S8 Clock Gen Block @ [FFB(CLK_GEN,0)]:
|
|
m0s8clockgenblockcell: Name =ClockGenBlock
|
|
PORT MAP (
|
|
);
|
|
Properties:
|
|
{
|
|
}
|
|
LPCOMPBLOCK group 0: empty
|
|
CTBMBLOCK group 0: empty
|
|
ANAPUMP group 0: empty
|
|
Bluetooth Low Energy Block group 0:
|
|
BLE Block @ [FFB(BLE,0)]:
|
|
p4blecell: Name =\BLE:cy_m0s8_ble\
|
|
PORT MAP (
|
|
interrupt => \BLE:Net_15\ );
|
|
Properties:
|
|
{
|
|
}
|
|
GANGED_PICU group 0: empty
|
|
</CYPRESSTAG>
|
|
<CYPRESSTAG name="Port Configuration Details">
|
|
|
|
------------------------------------------------------------
|
|
Port Configuration report
|
|
------------------------------------------------------------
|
|
| | | Interrupt | | |
|
|
Port | Pin | Fixed | Type | Drive Mode | Name | Connections
|
|
-----+-----+-------+-----------+------------------+------------+------------
|
|
2 | 6 | * | NONE | CMOS_OUT | Red_LED(0) | In(Net_94)
|
|
----------------------------------------------------------------------------
|
|
</CYPRESSTAG>
|
|
</CYPRESSTAG>
|
|
</CYPRESSTAG>
|
|
Digital component placer commit/Report: Elapsed time ==> 0s.005ms
|
|
Digital Placement phase: Elapsed time ==> 0s.495ms
|
|
</CYPRESSTAG>
|
|
<CYPRESSTAG name="Digital Routing">
|
|
Routing successful.
|
|
Digital Routing phase: Elapsed time ==> 0s.465ms
|
|
</CYPRESSTAG>
|
|
<CYPRESSTAG name="Bitstream and API generation">
|
|
Bitstream and API generation phase: Elapsed time ==> 0s.305ms
|
|
</CYPRESSTAG>
|
|
<CYPRESSTAG name="Bitstream verification">
|
|
Bitstream verification phase: Elapsed time ==> 0s.030ms
|
|
</CYPRESSTAG>
|
|
<CYPRESSTAG name="Static timing analysis">
|
|
Timing report is in BLE Lab 1_1_timing.html.
|
|
Static timing analysis phase: Elapsed time ==> 0s.140ms
|
|
</CYPRESSTAG>
|
|
<CYPRESSTAG name="Data reporting">
|
|
Data reporting phase: Elapsed time ==> 0s.000ms
|
|
</CYPRESSTAG>
|
|
<CYPRESSTAG name="Database update...">
|
|
Design database save phase: Elapsed time ==> 0s.258ms
|
|
</CYPRESSTAG>
|
|
cydsfit: Elapsed time ==> 2s.010ms
|
|
</CYPRESSTAG>
|
|
Fitter phase: Elapsed time ==> 2s.067ms
|
|
API generation phase: Elapsed time ==> 1s.123ms
|
|
Dependency generation phase: Elapsed time ==> 0s.024ms
|
|
Cleanup phase: Elapsed time ==> 0s.001ms
|