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net ClockBlock_HFCLK
|
|
term ":m0s8clockblockcell.hfclk"
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switch ":m0s8clockblockcell.hfclk==>:interrupt_12.clock"
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|
term ":interrupt_12.clock"
|
|
end ClockBlock_HFCLK
|
|
net Net_94
|
|
term ":m0s8tcpwmcell_0.line_out_compl"
|
|
switch ":m0s8tcpwmcell_0.line_out_compl==>Stub-:dsiswitch_top@[DSI=(0,1)][side=top]:dsihc_top:v24+:dsiswitch_top@[DSI=(0,1)][side=top]:dsihc_top:v26"
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switch "OStub-:dsiswitch_top@[DSI=(0,1)][side=top]:dsihc_top:v24+:dsiswitch_top@[DSI=(0,1)][side=top]:dsihc_top:v26"
|
|
switch ":dsiswitch_top@[DSI=(0,1)][side=top]:dsihc_top:24,28"
|
|
switch ":dsiswitch_top@[DSI=(0,1)][side=top]:dsihc_top:95,28_f"
|
|
switch "IStub-:dsiswitch_top@[DSI=(0,1)][side=top]:dsihc_top:v93+:dsiswitch_top@[DSI=(0,1)][side=top]:dsihc_top:v95+:dsiswitch_top@[DSI=(0,1)][side=top]:dsihc_top:v97"
|
|
switch "Stub-:dsiswitch_top@[DSI=(0,1)][side=top]:dsihc_top:v93+:dsiswitch_top@[DSI=(0,1)][side=top]:dsihc_top:v95+:dsiswitch_top@[DSI=(0,1)][side=top]:dsihc_top:v97==>:ioport2:inputs2_mux.in_1"
|
|
switch ":ioport2:inputs2_mux.pin6__pin_input==>:ioport2:hsiom_out6.dsi"
|
|
switch ":ioport2:hsiom_out6.hsiom6_out==>:ioport2:pin6.pin_input"
|
|
term ":ioport2:pin6.pin_input"
|
|
end Net_94
|
|
net \BLE:Net_15\
|
|
term ":p4blecell.interrupt"
|
|
switch ":p4blecell.interrupt==>:interrupt_idmux_12.in_0"
|
|
switch ":interrupt_idmux_12.interrupt_idmux_12__out==>:interrupt_12.interrupt"
|
|
term ":interrupt_12.interrupt"
|
|
end \BLE:Net_15\
|