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-- Project: BLE Lab 1_1
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-- Generated: 05/29/2015 00:00:20
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-- PSoC Creator 3.2
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ENTITY \BLE Lab 1_1\ IS
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PORT(
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Red_LED(0)_PAD : OUT std_ulogic);
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ATTRIBUTE voltage_VDDA_CTB OF __DEFAULT__ : ENTITY IS 3.3e0;
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ATTRIBUTE voltage_VDDA OF __DEFAULT__ : ENTITY IS 3.3e0;
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ATTRIBUTE voltage_VDDIO OF __DEFAULT__ : ENTITY IS 3.3e0;
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ATTRIBUTE voltage_VDDD OF __DEFAULT__ : ENTITY IS 3.3e0;
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ATTRIBUTE voltage_VDDR_HLS OF __DEFAULT__ : ENTITY IS 3.3e0;
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ATTRIBUTE voltage_VDDR_BGLS OF __DEFAULT__ : ENTITY IS 3.3e0;
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ATTRIBUTE voltage_VDDR_SYN OF __DEFAULT__ : ENTITY IS 3.3e0;
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ATTRIBUTE voltage_VDDR_LF OF __DEFAULT__ : ENTITY IS 3.3e0;
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ATTRIBUTE voltage_VDDR_HF OF __DEFAULT__ : ENTITY IS 3.3e0;
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END \BLE Lab 1_1\;
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ARCHITECTURE __DEFAULT__ OF \BLE Lab 1_1\ IS
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SIGNAL ClockBlock_ECO : bit;
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SIGNAL ClockBlock_EXTCLK : bit;
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SIGNAL ClockBlock_HFCLK : bit;
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ATTRIBUTE global_signal OF ClockBlock_HFCLK : SIGNAL IS true;
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SIGNAL ClockBlock_ILO : bit;
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SIGNAL ClockBlock_IMO : bit;
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SIGNAL ClockBlock_LFCLK : bit;
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SIGNAL ClockBlock_Routed1 : bit;
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SIGNAL ClockBlock_SYSCLK : bit;
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SIGNAL ClockBlock_WCO : bit;
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SIGNAL Net_15 : bit;
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SIGNAL Net_43_ff7 : bit;
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ATTRIBUTE global_signal OF Net_43_ff7 : SIGNAL IS true;
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SIGNAL Net_86 : bit;
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SIGNAL Net_87 : bit;
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SIGNAL Net_88 : bit;
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SIGNAL Net_89 : bit;
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SIGNAL Net_94 : bit;
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SIGNAL Red_LED(0)__PA : bit;
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SIGNAL \BLE:Net_15\ : bit;
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SIGNAL __ONE__ : bit;
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ATTRIBUTE POWER OF __ONE__ : SIGNAL IS true;
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SIGNAL __ZERO__ : bit;
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ATTRIBUTE GROUND OF __ZERO__ : SIGNAL IS true;
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SIGNAL tmpOE__Red_LED_net_0 : bit;
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ATTRIBUTE POWER OF tmpOE__Red_LED_net_0 : SIGNAL IS true;
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SIGNAL zero : bit;
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ATTRIBUTE GROUND OF zero : SIGNAL IS true;
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ATTRIBUTE Location OF ClockGenBlock : LABEL IS "F(CLK_GEN,0)";
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ATTRIBUTE lib_model OF Red_LED(0) : LABEL IS "iocell1";
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COMPONENT interrupt
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PORT (
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interrupt : IN std_ulogic;
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clock : IN std_ulogic);
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END COMPONENT;
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COMPONENT iocell
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PORT (
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pin_input : IN std_ulogic;
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oe : IN std_ulogic;
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fb : OUT std_ulogic;
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pad_in : IN std_ulogic;
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pa_out : OUT std_ulogic;
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pad_out : OUT std_ulogic;
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oe_reg : OUT std_ulogic;
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oe_internal : IN std_ulogic;
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in_clock : IN std_ulogic;
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in_clock_en : IN std_ulogic;
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in_reset : IN std_ulogic;
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out_clock : IN std_ulogic;
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out_clock_en : IN std_ulogic;
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out_reset : IN std_ulogic);
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END COMPONENT;
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COMPONENT logicalport
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PORT (
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interrupt : OUT std_ulogic;
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precharge : IN std_ulogic;
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in_clock : IN std_ulogic;
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in_clock_en : IN std_ulogic;
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in_reset : IN std_ulogic;
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out_clock : IN std_ulogic;
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out_clock_en : IN std_ulogic;
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out_reset : IN std_ulogic);
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END COMPONENT;
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COMPONENT m0s8clockblockcell
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PORT (
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imo : OUT std_ulogic;
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ext : OUT std_ulogic;
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eco : OUT std_ulogic;
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ilo : OUT std_ulogic;
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wco : OUT std_ulogic;
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dbl : OUT std_ulogic;
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pll : OUT std_ulogic;
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dpll : OUT std_ulogic;
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dsi_out_0 : IN std_ulogic;
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dsi_out_1 : IN std_ulogic;
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dsi_out_2 : IN std_ulogic;
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dsi_out_3 : IN std_ulogic;
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lfclk : OUT std_ulogic;
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hfclk : OUT std_ulogic;
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sysclk : OUT std_ulogic;
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halfsysclk : OUT std_ulogic;
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udb_div_0 : OUT std_ulogic;
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udb_div_1 : OUT std_ulogic;
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udb_div_2 : OUT std_ulogic;
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udb_div_3 : OUT std_ulogic;
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udb_div_4 : OUT std_ulogic;
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udb_div_5 : OUT std_ulogic;
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udb_div_6 : OUT std_ulogic;
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udb_div_7 : OUT std_ulogic;
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udb_div_8 : OUT std_ulogic;
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udb_div_9 : OUT std_ulogic;
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udb_div_10 : OUT std_ulogic;
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udb_div_11 : OUT std_ulogic;
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udb_div_12 : OUT std_ulogic;
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udb_div_13 : OUT std_ulogic;
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udb_div_14 : OUT std_ulogic;
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udb_div_15 : OUT std_ulogic;
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uab_div_0 : OUT std_ulogic;
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uab_div_1 : OUT std_ulogic;
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uab_div_2 : OUT std_ulogic;
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uab_div_3 : OUT std_ulogic;
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ff_div_0 : OUT std_ulogic;
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ff_div_1 : OUT std_ulogic;
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ff_div_2 : OUT std_ulogic;
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ff_div_3 : OUT std_ulogic;
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ff_div_4 : OUT std_ulogic;
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ff_div_5 : OUT std_ulogic;
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ff_div_6 : OUT std_ulogic;
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ff_div_7 : OUT std_ulogic;
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ff_div_8 : OUT std_ulogic;
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ff_div_9 : OUT std_ulogic;
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ff_div_10 : OUT std_ulogic;
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ff_div_11 : OUT std_ulogic;
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ff_div_12 : OUT std_ulogic;
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ff_div_13 : OUT std_ulogic;
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ff_div_14 : OUT std_ulogic;
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ff_div_15 : OUT std_ulogic;
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ff_div_16 : OUT std_ulogic;
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ff_div_17 : OUT std_ulogic;
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ff_div_18 : OUT std_ulogic;
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ff_div_19 : OUT std_ulogic;
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ff_div_20 : OUT std_ulogic;
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ff_div_21 : OUT std_ulogic;
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ff_div_22 : OUT std_ulogic;
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ff_div_23 : OUT std_ulogic;
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ff_div_24 : OUT std_ulogic;
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ff_div_25 : OUT std_ulogic;
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ff_div_26 : OUT std_ulogic;
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ff_div_27 : OUT std_ulogic;
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ff_div_28 : OUT std_ulogic;
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ff_div_29 : OUT std_ulogic;
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ff_div_30 : OUT std_ulogic;
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ff_div_31 : OUT std_ulogic;
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ff_div_32 : OUT std_ulogic;
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ff_div_33 : OUT std_ulogic;
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ff_div_34 : OUT std_ulogic;
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ff_div_35 : OUT std_ulogic;
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ff_div_36 : OUT std_ulogic;
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ff_div_37 : OUT std_ulogic;
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ff_div_38 : OUT std_ulogic;
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ff_div_39 : OUT std_ulogic;
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ff_div_40 : OUT std_ulogic;
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ff_div_41 : OUT std_ulogic;
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ff_div_42 : OUT std_ulogic;
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ff_div_43 : OUT std_ulogic;
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ff_div_44 : OUT std_ulogic;
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ff_div_45 : OUT std_ulogic;
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ff_div_46 : OUT std_ulogic;
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ff_div_47 : OUT std_ulogic;
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ff_div_48 : OUT std_ulogic;
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ff_div_49 : OUT std_ulogic;
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ff_div_50 : OUT std_ulogic;
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ff_div_51 : OUT std_ulogic;
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ff_div_52 : OUT std_ulogic;
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ff_div_53 : OUT std_ulogic;
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ff_div_54 : OUT std_ulogic;
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ff_div_55 : OUT std_ulogic;
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ff_div_56 : OUT std_ulogic;
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ff_div_57 : OUT std_ulogic;
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ff_div_58 : OUT std_ulogic;
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ff_div_59 : OUT std_ulogic;
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ff_div_60 : OUT std_ulogic;
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ff_div_61 : OUT std_ulogic;
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ff_div_62 : OUT std_ulogic;
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ff_div_63 : OUT std_ulogic;
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dsi_in_0 : OUT std_ulogic;
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dsi_in_1 : OUT std_ulogic;
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dsi_in_2 : OUT std_ulogic;
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dsi_in_3 : OUT std_ulogic);
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END COMPONENT;
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COMPONENT m0s8clockgenblockcell
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PORT (
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gen_clk_in_0 : IN std_ulogic;
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gen_clk_in_1 : IN std_ulogic;
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gen_clk_in_2 : IN std_ulogic;
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gen_clk_in_3 : IN std_ulogic;
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gen_clk_in_4 : IN std_ulogic;
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gen_clk_in_5 : IN std_ulogic;
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gen_clk_in_6 : IN std_ulogic;
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gen_clk_in_7 : IN std_ulogic;
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gen_clk_out_0 : OUT std_ulogic;
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gen_clk_out_1 : OUT std_ulogic;
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gen_clk_out_2 : OUT std_ulogic;
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gen_clk_out_3 : OUT std_ulogic;
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gen_clk_out_4 : OUT std_ulogic;
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gen_clk_out_5 : OUT std_ulogic;
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gen_clk_out_6 : OUT std_ulogic;
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gen_clk_out_7 : OUT std_ulogic);
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END COMPONENT;
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COMPONENT m0s8tcpwmcell
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PORT (
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clock : IN std_ulogic;
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capture : IN std_ulogic;
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count : IN std_ulogic;
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reload : IN std_ulogic;
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stop : IN std_ulogic;
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start : IN std_ulogic;
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tr_underflow : OUT std_ulogic;
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tr_overflow : OUT std_ulogic;
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tr_compare_match : OUT std_ulogic;
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line_out : OUT std_ulogic;
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line_out_compl : OUT std_ulogic;
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interrupt : OUT std_ulogic);
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END COMPONENT;
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COMPONENT p4blecell
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PORT (
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interrupt : OUT std_ulogic;
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rfctrl_extpa_en : OUT std_ulogic);
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END COMPONENT;
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BEGIN
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ClockBlock:m0s8clockblockcell
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PORT MAP(
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hfclk => ClockBlock_HFCLK,
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imo => ClockBlock_IMO,
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ext => ClockBlock_EXTCLK,
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sysclk => ClockBlock_SYSCLK,
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eco => ClockBlock_ECO,
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ilo => ClockBlock_ILO,
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lfclk => ClockBlock_LFCLK,
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wco => ClockBlock_WCO,
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dsi_in_0 => ClockBlock_Routed1,
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ff_div_7 => Net_43_ff7);
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ClockGenBlock:m0s8clockgenblockcell;
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Red_LED:logicalport
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GENERIC MAP(
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drive_mode => "110",
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ibuf_enabled => "1",
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id => "e851a3b9-efb8-48be-bbb8-b303b216c393",
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init_dr_st => "1",
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input_buffer_sel => "00",
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input_clk_en => 0,
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input_sync => "1",
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input_sync_mode => "0",
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intr_mode => "00",
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invert_in_clock => 0,
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invert_in_clock_en => 0,
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invert_in_reset => 0,
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invert_out_clock => 0,
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invert_out_clock_en => 0,
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invert_out_reset => 0,
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io_voltage => "",
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layout_mode => "CONTIGUOUS",
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oe_conn => "0",
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oe_reset => 0,
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oe_sync => "0",
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output_clk_en => 0,
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output_clock_mode => "0",
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output_conn => "1",
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output_mode => "0",
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output_reset => 0,
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output_sync => "0",
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ovt_hyst_trim => "0",
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ovt_needed => "0",
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ovt_slew_control => "00",
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pa_in_clock => -1,
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pa_in_clock_en => -1,
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pa_in_reset => -1,
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pa_out_clock => -1,
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pa_out_clock_en => -1,
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pa_out_reset => -1,
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pin_aliases => "",
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pin_mode => "O",
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por_state => 4,
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port_alias_group => "",
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port_alias_required => 0,
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sio_group_cnt => 0,
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sio_hifreq => "",
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sio_hyst => "1",
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sio_ibuf => "00000000",
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sio_info => "00",
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sio_obuf => "00000000",
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sio_refsel => "00000000",
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sio_vtrip => "00000000",
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slew_rate => "0",
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spanning => 0,
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sw_only => 0,
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use_annotation => "0",
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vtrip => "10",
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width => 1,
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in_clk_inv => 0,
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in_clken_inv => 0,
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in_clken_mode => 1,
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in_rst_inv => 0,
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out_clk_inv => 0,
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out_clken_inv => 0,
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out_clken_mode => 1,
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out_rst_inv => 0)
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PORT MAP(
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in_clock_en => open,
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in_reset => open,
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out_clock_en => open,
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out_reset => open);
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Red_LED(0):iocell
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GENERIC MAP(
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in_sync_mode => 0,
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out_sync_mode => 0,
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oe_sync_mode => 0,
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logicalport => "Red_LED",
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logicalport_pin_id => 0,
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io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001")
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PORT MAP(
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pa_out => Red_LED(0)__PA,
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oe => open,
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pin_input => Net_94,
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pad_out => Red_LED(0)_PAD,
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pad_in => Red_LED(0)_PAD,
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in_clock => open,
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in_clock_en => '1',
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in_reset => '0',
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out_clock => open,
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out_clock_en => '1',
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out_reset => '0');
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\BLE:bless_isr\:interrupt
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GENERIC MAP(
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int_type => "10")
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PORT MAP(
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interrupt => \BLE:Net_15\,
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clock => ClockBlock_HFCLK);
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\BLE:cy_m0s8_ble\:p4blecell
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PORT MAP(
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interrupt => \BLE:Net_15\);
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\PWM:cy_m0s8_tcpwm_1\:m0s8tcpwmcell
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GENERIC MAP(
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cy_registers => "")
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PORT MAP(
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clock => Net_43_ff7,
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capture => '0',
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count => '1',
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reload => '0',
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stop => '0',
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start => '0',
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tr_underflow => Net_88,
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tr_overflow => Net_87,
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tr_compare_match => Net_89,
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line_out => Net_15,
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line_out_compl => Net_94,
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interrupt => Net_86);
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END __DEFAULT__;
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