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;
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; FILENAME: cydeviceiar_trm.inc
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;
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; PSoC Creator 3.2
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;
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; DESCRIPTION:
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; This file provides all of the address values for the entire PSoC device.
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;
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;-------------------------------------------------------------------------------
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; Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
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; You may use this file only in accordance with the license, terms, conditions,
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; disclaimers, and limitations in the end user license agreement accompanying
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; the software package with which this file was provided.
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;-------------------------------------------------------------------------------
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#define CYDEV_FLASH_BASE 0x00000000
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#define CYDEV_FLASH_SIZE 0x00020000
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#define CYREG_FLASH_DATA_MBASE 0x00000000
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#define CYREG_FLASH_DATA_MSIZE 0x00020000
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#define CYDEV_SFLASH_BASE 0x0ffff000
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#define CYDEV_SFLASH_SIZE 0x00000800
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#define CYREG_SFLASH_PROT_ROW0 0x0ffff000
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#define CYFLD_SFLASH_DATA8__OFFSET 0x00000000
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#define CYFLD_SFLASH_DATA8__SIZE 0x00000008
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#define CYREG_SFLASH_PROT_ROW1 0x0ffff001
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#define CYREG_SFLASH_PROT_ROW2 0x0ffff002
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#define CYREG_SFLASH_PROT_ROW3 0x0ffff003
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#define CYREG_SFLASH_PROT_ROW4 0x0ffff004
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#define CYREG_SFLASH_PROT_ROW5 0x0ffff005
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#define CYREG_SFLASH_PROT_ROW6 0x0ffff006
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#define CYREG_SFLASH_PROT_ROW7 0x0ffff007
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#define CYREG_SFLASH_PROT_ROW8 0x0ffff008
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#define CYREG_SFLASH_PROT_ROW9 0x0ffff009
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#define CYREG_SFLASH_PROT_ROW10 0x0ffff00a
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#define CYREG_SFLASH_PROT_ROW11 0x0ffff00b
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#define CYREG_SFLASH_PROT_ROW12 0x0ffff00c
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#define CYREG_SFLASH_PROT_ROW13 0x0ffff00d
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#define CYREG_SFLASH_PROT_ROW14 0x0ffff00e
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#define CYREG_SFLASH_PROT_ROW15 0x0ffff00f
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#define CYREG_SFLASH_PROT_ROW16 0x0ffff010
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#define CYREG_SFLASH_PROT_ROW17 0x0ffff011
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#define CYREG_SFLASH_PROT_ROW18 0x0ffff012
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#define CYREG_SFLASH_PROT_ROW19 0x0ffff013
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#define CYREG_SFLASH_PROT_ROW20 0x0ffff014
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#define CYREG_SFLASH_PROT_ROW21 0x0ffff015
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#define CYREG_SFLASH_PROT_ROW22 0x0ffff016
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#define CYREG_SFLASH_PROT_ROW23 0x0ffff017
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#define CYREG_SFLASH_PROT_ROW24 0x0ffff018
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#define CYREG_SFLASH_PROT_ROW25 0x0ffff019
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#define CYREG_SFLASH_PROT_ROW26 0x0ffff01a
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#define CYREG_SFLASH_PROT_ROW27 0x0ffff01b
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#define CYREG_SFLASH_PROT_ROW28 0x0ffff01c
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#define CYREG_SFLASH_PROT_ROW29 0x0ffff01d
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#define CYREG_SFLASH_PROT_ROW30 0x0ffff01e
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#define CYREG_SFLASH_PROT_ROW31 0x0ffff01f
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#define CYREG_SFLASH_PROT_ROW32 0x0ffff020
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#define CYREG_SFLASH_PROT_ROW33 0x0ffff021
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#define CYREG_SFLASH_PROT_ROW34 0x0ffff022
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#define CYREG_SFLASH_PROT_ROW35 0x0ffff023
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#define CYREG_SFLASH_PROT_ROW36 0x0ffff024
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#define CYREG_SFLASH_PROT_ROW37 0x0ffff025
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#define CYREG_SFLASH_PROT_ROW38 0x0ffff026
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#define CYREG_SFLASH_PROT_ROW39 0x0ffff027
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#define CYREG_SFLASH_PROT_ROW40 0x0ffff028
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#define CYREG_SFLASH_PROT_ROW41 0x0ffff029
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#define CYREG_SFLASH_PROT_ROW42 0x0ffff02a
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#define CYREG_SFLASH_PROT_ROW43 0x0ffff02b
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#define CYREG_SFLASH_PROT_ROW44 0x0ffff02c
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#define CYREG_SFLASH_PROT_ROW45 0x0ffff02d
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#define CYREG_SFLASH_PROT_ROW46 0x0ffff02e
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#define CYREG_SFLASH_PROT_ROW47 0x0ffff02f
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#define CYREG_SFLASH_PROT_ROW48 0x0ffff030
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#define CYREG_SFLASH_PROT_ROW49 0x0ffff031
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#define CYREG_SFLASH_PROT_ROW50 0x0ffff032
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#define CYREG_SFLASH_PROT_ROW51 0x0ffff033
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#define CYREG_SFLASH_PROT_ROW52 0x0ffff034
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#define CYREG_SFLASH_PROT_ROW53 0x0ffff035
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#define CYREG_SFLASH_PROT_ROW54 0x0ffff036
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#define CYREG_SFLASH_PROT_ROW55 0x0ffff037
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#define CYREG_SFLASH_PROT_ROW56 0x0ffff038
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#define CYREG_SFLASH_PROT_ROW57 0x0ffff039
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#define CYREG_SFLASH_PROT_ROW58 0x0ffff03a
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#define CYREG_SFLASH_PROT_ROW59 0x0ffff03b
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#define CYREG_SFLASH_PROT_ROW60 0x0ffff03c
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#define CYREG_SFLASH_PROT_ROW61 0x0ffff03d
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#define CYREG_SFLASH_PROT_ROW62 0x0ffff03e
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#define CYREG_SFLASH_PROT_ROW63 0x0ffff03f
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#define CYREG_SFLASH_PROT_PROTECTION 0x0ffff07f
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#define CYFLD_SFLASH_PROT_LEVEL__OFFSET 0x00000000
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#define CYFLD_SFLASH_PROT_LEVEL__SIZE 0x00000002
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#define CYVAL_SFLASH_PROT_LEVEL_VIRGIN 0x00000001
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#define CYVAL_SFLASH_PROT_LEVEL_OPEN 0x00000000
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#define CYVAL_SFLASH_PROT_LEVEL_PROTECTED 0x00000002
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#define CYVAL_SFLASH_PROT_LEVEL_KILL 0x00000003
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#define CYREG_SFLASH_AV_PAIRS_8B0 0x0ffff080
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#define CYREG_SFLASH_AV_PAIRS_8B1 0x0ffff081
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#define CYREG_SFLASH_AV_PAIRS_8B2 0x0ffff082
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#define CYREG_SFLASH_AV_PAIRS_8B3 0x0ffff083
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#define CYREG_SFLASH_AV_PAIRS_8B4 0x0ffff084
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#define CYREG_SFLASH_AV_PAIRS_8B5 0x0ffff085
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#define CYREG_SFLASH_AV_PAIRS_8B6 0x0ffff086
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#define CYREG_SFLASH_AV_PAIRS_8B7 0x0ffff087
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#define CYREG_SFLASH_AV_PAIRS_8B8 0x0ffff088
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#define CYREG_SFLASH_AV_PAIRS_8B9 0x0ffff089
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#define CYREG_SFLASH_AV_PAIRS_8B10 0x0ffff08a
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#define CYREG_SFLASH_AV_PAIRS_8B11 0x0ffff08b
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#define CYREG_SFLASH_AV_PAIRS_8B12 0x0ffff08c
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#define CYREG_SFLASH_AV_PAIRS_8B13 0x0ffff08d
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#define CYREG_SFLASH_AV_PAIRS_8B14 0x0ffff08e
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#define CYREG_SFLASH_AV_PAIRS_8B15 0x0ffff08f
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#define CYREG_SFLASH_AV_PAIRS_8B16 0x0ffff090
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#define CYREG_SFLASH_AV_PAIRS_8B17 0x0ffff091
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#define CYREG_SFLASH_AV_PAIRS_8B18 0x0ffff092
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#define CYREG_SFLASH_AV_PAIRS_8B19 0x0ffff093
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#define CYREG_SFLASH_AV_PAIRS_8B20 0x0ffff094
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#define CYREG_SFLASH_AV_PAIRS_8B21 0x0ffff095
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#define CYREG_SFLASH_AV_PAIRS_8B22 0x0ffff096
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#define CYREG_SFLASH_AV_PAIRS_8B23 0x0ffff097
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#define CYREG_SFLASH_AV_PAIRS_8B24 0x0ffff098
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#define CYREG_SFLASH_AV_PAIRS_8B25 0x0ffff099
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#define CYREG_SFLASH_AV_PAIRS_8B26 0x0ffff09a
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#define CYREG_SFLASH_AV_PAIRS_8B27 0x0ffff09b
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#define CYREG_SFLASH_AV_PAIRS_8B28 0x0ffff09c
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#define CYREG_SFLASH_AV_PAIRS_8B29 0x0ffff09d
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#define CYREG_SFLASH_AV_PAIRS_8B30 0x0ffff09e
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#define CYREG_SFLASH_AV_PAIRS_8B31 0x0ffff09f
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#define CYREG_SFLASH_AV_PAIRS_8B32 0x0ffff0a0
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#define CYREG_SFLASH_AV_PAIRS_8B33 0x0ffff0a1
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#define CYREG_SFLASH_AV_PAIRS_8B34 0x0ffff0a2
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#define CYREG_SFLASH_AV_PAIRS_8B35 0x0ffff0a3
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#define CYREG_SFLASH_AV_PAIRS_8B36 0x0ffff0a4
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#define CYREG_SFLASH_AV_PAIRS_8B37 0x0ffff0a5
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#define CYREG_SFLASH_AV_PAIRS_8B38 0x0ffff0a6
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#define CYREG_SFLASH_AV_PAIRS_8B39 0x0ffff0a7
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#define CYREG_SFLASH_AV_PAIRS_8B40 0x0ffff0a8
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#define CYREG_SFLASH_AV_PAIRS_8B41 0x0ffff0a9
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#define CYREG_SFLASH_AV_PAIRS_8B42 0x0ffff0aa
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#define CYREG_SFLASH_AV_PAIRS_8B43 0x0ffff0ab
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#define CYREG_SFLASH_AV_PAIRS_8B44 0x0ffff0ac
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#define CYREG_SFLASH_AV_PAIRS_8B45 0x0ffff0ad
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#define CYREG_SFLASH_AV_PAIRS_8B46 0x0ffff0ae
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#define CYREG_SFLASH_AV_PAIRS_8B47 0x0ffff0af
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#define CYREG_SFLASH_AV_PAIRS_8B48 0x0ffff0b0
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#define CYREG_SFLASH_AV_PAIRS_8B49 0x0ffff0b1
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#define CYREG_SFLASH_AV_PAIRS_8B50 0x0ffff0b2
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#define CYREG_SFLASH_AV_PAIRS_8B51 0x0ffff0b3
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#define CYREG_SFLASH_AV_PAIRS_8B52 0x0ffff0b4
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#define CYREG_SFLASH_AV_PAIRS_8B53 0x0ffff0b5
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#define CYREG_SFLASH_AV_PAIRS_8B54 0x0ffff0b6
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#define CYREG_SFLASH_AV_PAIRS_8B55 0x0ffff0b7
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#define CYREG_SFLASH_AV_PAIRS_8B56 0x0ffff0b8
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#define CYREG_SFLASH_AV_PAIRS_8B57 0x0ffff0b9
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#define CYREG_SFLASH_AV_PAIRS_8B58 0x0ffff0ba
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#define CYREG_SFLASH_AV_PAIRS_8B59 0x0ffff0bb
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#define CYREG_SFLASH_AV_PAIRS_8B60 0x0ffff0bc
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#define CYREG_SFLASH_AV_PAIRS_8B61 0x0ffff0bd
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#define CYREG_SFLASH_AV_PAIRS_8B62 0x0ffff0be
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#define CYREG_SFLASH_AV_PAIRS_8B63 0x0ffff0bf
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#define CYREG_SFLASH_AV_PAIRS_8B64 0x0ffff0c0
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#define CYREG_SFLASH_AV_PAIRS_8B65 0x0ffff0c1
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#define CYREG_SFLASH_AV_PAIRS_8B66 0x0ffff0c2
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#define CYREG_SFLASH_AV_PAIRS_8B67 0x0ffff0c3
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#define CYREG_SFLASH_AV_PAIRS_8B68 0x0ffff0c4
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#define CYREG_SFLASH_AV_PAIRS_8B69 0x0ffff0c5
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#define CYREG_SFLASH_AV_PAIRS_8B70 0x0ffff0c6
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#define CYREG_SFLASH_AV_PAIRS_8B71 0x0ffff0c7
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#define CYREG_SFLASH_AV_PAIRS_8B72 0x0ffff0c8
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#define CYREG_SFLASH_AV_PAIRS_8B73 0x0ffff0c9
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#define CYREG_SFLASH_AV_PAIRS_8B74 0x0ffff0ca
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#define CYREG_SFLASH_AV_PAIRS_8B75 0x0ffff0cb
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#define CYREG_SFLASH_AV_PAIRS_8B76 0x0ffff0cc
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#define CYREG_SFLASH_AV_PAIRS_8B77 0x0ffff0cd
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#define CYREG_SFLASH_AV_PAIRS_8B78 0x0ffff0ce
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#define CYREG_SFLASH_AV_PAIRS_8B79 0x0ffff0cf
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#define CYREG_SFLASH_AV_PAIRS_8B80 0x0ffff0d0
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#define CYREG_SFLASH_AV_PAIRS_8B81 0x0ffff0d1
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#define CYREG_SFLASH_AV_PAIRS_8B82 0x0ffff0d2
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#define CYREG_SFLASH_AV_PAIRS_8B83 0x0ffff0d3
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#define CYREG_SFLASH_AV_PAIRS_8B84 0x0ffff0d4
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#define CYREG_SFLASH_AV_PAIRS_8B85 0x0ffff0d5
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#define CYREG_SFLASH_AV_PAIRS_8B86 0x0ffff0d6
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#define CYREG_SFLASH_AV_PAIRS_8B87 0x0ffff0d7
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#define CYREG_SFLASH_BLESS_BB_BUMP2 0x0ffff0d8
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#define CYFLD_SFLASH_V2I_RCAL__OFFSET 0x00000000
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#define CYFLD_SFLASH_V2I_RCAL__SIZE 0x00000005
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#define CYFLD_SFLASH_V2I__OFFSET 0x00000005
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#define CYFLD_SFLASH_V2I__SIZE 0x00000005
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#define CYFLD_SFLASH_VBG_TRIM__OFFSET 0x0000000a
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#define CYFLD_SFLASH_VBG_TRIM__SIZE 0x00000003
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#define CYFLD_SFLASH_SY_IBIAS__OFFSET 0x0000000d
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#define CYFLD_SFLASH_SY_IBIAS__SIZE 0x00000003
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#define CYREG_SFLASH_AV_PAIRS_8B88 0x0ffff0d8
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#define CYREG_SFLASH_AV_PAIRS_8B89 0x0ffff0d9
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#define CYREG_SFLASH_BLESS_BB_XO 0x0ffff0da
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#define CYFLD_SFLASH_DIS_XOCORE_SUPFILT__OFFSET 0x00000000
|
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#define CYFLD_SFLASH_DIS_XOCORE_SUPFILT__SIZE 0x00000001
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#define CYFLD_SFLASH_EN_RE_FASTSTART__OFFSET 0x00000001
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#define CYFLD_SFLASH_EN_RE_FASTSTART__SIZE 0x00000001
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#define CYFLD_SFLASH_EN_CURMEAS__OFFSET 0x00000002
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#define CYFLD_SFLASH_EN_CURMEAS__SIZE 0x00000001
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#define CYFLD_SFLASH_EN_AMPDET_CURMEAS__OFFSET 0x00000003
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#define CYFLD_SFLASH_EN_AMPDET_CURMEAS__SIZE 0x00000001
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#define CYFLD_SFLASH_EN_AMPDET_FASTSTART__OFFSET 0x00000004
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#define CYFLD_SFLASH_EN_AMPDET_FASTSTART__SIZE 0x00000001
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#define CYFLD_SFLASH_CTRL_RC_FASTSTART_RES__OFFSET 0x00000005
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#define CYFLD_SFLASH_CTRL_RC_FASTSTART_RES__SIZE 0x00000002
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#define CYFLD_SFLASH_CTRL_VDDL_XO__OFFSET 0x00000007
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#define CYFLD_SFLASH_CTRL_VDDL_XO__SIZE 0x00000003
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#define CYFLD_SFLASH_CTRL_VDDL_XB__OFFSET 0x0000000a
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#define CYFLD_SFLASH_CTRL_VDDL_XB__SIZE 0x00000003
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#define CYFLD_SFLASH_CTRL_RPREF__OFFSET 0x0000000d
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#define CYFLD_SFLASH_CTRL_RPREF__SIZE 0x00000002
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#define CYFLD_SFLASH_rev_bb_xo__OFFSET 0x0000000f
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#define CYFLD_SFLASH_rev_bb_xo__SIZE 0x00000001
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#define CYREG_SFLASH_AV_PAIRS_8B90 0x0ffff0da
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#define CYREG_SFLASH_AV_PAIRS_8B91 0x0ffff0db
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#define CYREG_SFLASH_AV_PAIRS_8B92 0x0ffff0dc
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#define CYREG_SFLASH_BLESS_SY_BUMP1 0x0ffff0dc
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#define CYFLD_SFLASH_VCO__OFFSET 0x00000000
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#define CYFLD_SFLASH_VCO__SIZE 0x00000004
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#define CYFLD_SFLASH_LOFB_POWERSAVE__OFFSET 0x00000004
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#define CYFLD_SFLASH_LOFB_POWERSAVE__SIZE 0x00000001
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#define CYFLD_SFLASH_IBIAS_LOPATH__OFFSET 0x00000005
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#define CYFLD_SFLASH_IBIAS_LOPATH__SIZE 0x00000002
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#define CYFLD_SFLASH_LDOLO_FORCE_STARTUP__OFFSET 0x00000007
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#define CYFLD_SFLASH_LDOLO_FORCE_STARTUP__SIZE 0x00000001
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#define CYFLD_SFLASH_LOPATH__OFFSET 0x00000008
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#define CYFLD_SFLASH_LOPATH__SIZE 0x00000004
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#define CYFLD_SFLASH_PDCPLPF__OFFSET 0x0000000c
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#define CYFLD_SFLASH_PDCPLPF__SIZE 0x00000004
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#define CYREG_SFLASH_AV_PAIRS_8B93 0x0ffff0dd
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#define CYREG_SFLASH_AV_PAIRS_8B94 0x0ffff0de
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#define CYREG_SFLASH_BLESS_LDO 0x0ffff0de
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#define CYFLD_SFLASH_BUMP_BALUM_HF__OFFSET 0x00000000
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#define CYFLD_SFLASH_BUMP_BALUM_HF__SIZE 0x00000003
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#define CYFLD_SFLASH_BUMP_SY_VCO__OFFSET 0x00000003
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#define CYFLD_SFLASH_BUMP_SY_VCO__SIZE 0x00000002
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#define CYFLD_SFLASH_BUMP_SY_LOPATH__OFFSET 0x00000005
|
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#define CYFLD_SFLASH_BUMP_SY_LOPATH__SIZE 0x00000002
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#define CYFLD_SFLASH_BUMP_SY_LHV__OFFSET 0x00000007
|
|
#define CYFLD_SFLASH_BUMP_SY_LHV__SIZE 0x00000002
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|
#define CYFLD_SFLASH_BUMP_SY_FFFB__OFFSET 0x00000009
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|
#define CYFLD_SFLASH_BUMP_SY_FFFB__SIZE 0x00000003
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|
#define CYFLD_SFLASH_REV_LDO__OFFSET 0x0000000c
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#define CYFLD_SFLASH_REV_LDO__SIZE 0x00000004
|
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#define CYREG_SFLASH_AV_PAIRS_8B95 0x0ffff0df
|
|
#define CYREG_SFLASH_AV_PAIRS_8B96 0x0ffff0e0
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|
#define CYREG_SFLASH_AV_PAIRS_8B97 0x0ffff0e1
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|
#define CYREG_SFLASH_AV_PAIRS_8B98 0x0ffff0e2
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|
#define CYREG_SFLASH_AV_PAIRS_8B99 0x0ffff0e3
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#define CYREG_SFLASH_AV_PAIRS_8B100 0x0ffff0e4
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#define CYREG_SFLASH_AV_PAIRS_8B101 0x0ffff0e5
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|
#define CYREG_SFLASH_AV_PAIRS_8B102 0x0ffff0e6
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#define CYREG_SFLASH_AV_PAIRS_8B103 0x0ffff0e7
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|
#define CYREG_SFLASH_AV_PAIRS_8B104 0x0ffff0e8
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|
#define CYREG_SFLASH_AV_PAIRS_8B105 0x0ffff0e9
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#define CYREG_SFLASH_AV_PAIRS_8B106 0x0ffff0ea
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|
#define CYREG_SFLASH_AV_PAIRS_8B107 0x0ffff0eb
|
|
#define CYREG_SFLASH_AV_PAIRS_8B108 0x0ffff0ec
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|
#define CYREG_SFLASH_AV_PAIRS_8B109 0x0ffff0ed
|
|
#define CYREG_SFLASH_AV_PAIRS_8B110 0x0ffff0ee
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#define CYREG_SFLASH_AV_PAIRS_8B111 0x0ffff0ef
|
|
#define CYREG_SFLASH_AV_PAIRS_8B112 0x0ffff0f0
|
|
#define CYREG_SFLASH_AV_PAIRS_8B113 0x0ffff0f1
|
|
#define CYREG_SFLASH_AV_PAIRS_8B114 0x0ffff0f2
|
|
#define CYREG_SFLASH_AV_PAIRS_8B115 0x0ffff0f3
|
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#define CYREG_SFLASH_AV_PAIRS_8B116 0x0ffff0f4
|
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#define CYREG_SFLASH_AV_PAIRS_8B117 0x0ffff0f5
|
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#define CYREG_SFLASH_AV_PAIRS_8B118 0x0ffff0f6
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|
#define CYREG_SFLASH_AV_PAIRS_8B119 0x0ffff0f7
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|
#define CYREG_SFLASH_AV_PAIRS_8B120 0x0ffff0f8
|
|
#define CYREG_SFLASH_AV_PAIRS_8B121 0x0ffff0f9
|
|
#define CYREG_SFLASH_AV_PAIRS_8B122 0x0ffff0fa
|
|
#define CYREG_SFLASH_AV_PAIRS_8B123 0x0ffff0fb
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|
#define CYREG_SFLASH_AV_PAIRS_8B124 0x0ffff0fc
|
|
#define CYREG_SFLASH_AV_PAIRS_8B125 0x0ffff0fd
|
|
#define CYREG_SFLASH_AV_PAIRS_8B126 0x0ffff0fe
|
|
#define CYREG_SFLASH_AV_PAIRS_8B127 0x0ffff0ff
|
|
#define CYREG_SFLASH_AV_PAIRS_32B0 0x0ffff100
|
|
#define CYFLD_SFLASH_DATA32__OFFSET 0x00000000
|
|
#define CYFLD_SFLASH_DATA32__SIZE 0x00000020
|
|
#define CYREG_SFLASH_AV_PAIRS_32B1 0x0ffff104
|
|
#define CYREG_SFLASH_AV_PAIRS_32B2 0x0ffff108
|
|
#define CYREG_SFLASH_AV_PAIRS_32B3 0x0ffff10c
|
|
#define CYREG_SFLASH_AV_PAIRS_32B4 0x0ffff110
|
|
#define CYREG_SFLASH_AV_PAIRS_32B5 0x0ffff114
|
|
#define CYREG_SFLASH_AV_PAIRS_32B6 0x0ffff118
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#define CYREG_SFLASH_AV_PAIRS_32B7 0x0ffff11c
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#define CYREG_SFLASH_AV_PAIRS_32B8 0x0ffff120
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#define CYREG_SFLASH_AV_PAIRS_32B9 0x0ffff124
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#define CYREG_SFLASH_AV_PAIRS_32B10 0x0ffff128
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#define CYREG_SFLASH_AV_PAIRS_32B11 0x0ffff12c
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#define CYREG_SFLASH_AV_PAIRS_32B12 0x0ffff130
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#define CYREG_SFLASH_AV_PAIRS_32B13 0x0ffff134
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#define CYREG_SFLASH_AV_PAIRS_32B14 0x0ffff138
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#define CYREG_SFLASH_AV_PAIRS_32B15 0x0ffff13c
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#define CYREG_SFLASH_CPUSS_WOUNDING 0x0ffff140
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#define CYREG_SFLASH_SILICON_ID 0x0ffff144
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#define CYFLD_SFLASH_ID__OFFSET 0x00000000
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#define CYFLD_SFLASH_ID__SIZE 0x00000010
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#define CYREG_SFLASH_CPUSS_PRIV_RAM 0x0ffff148
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#define CYFLD_SFLASH_RAM_PROT_LIMIT__OFFSET 0x00000000
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#define CYFLD_SFLASH_RAM_PROT_LIMIT__SIZE 0x00000009
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#define CYREG_SFLASH_CPUSS_PRIV_ROM_BROM 0x0ffff14a
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#define CYFLD_SFLASH_BROM_PROT_LIMIT__OFFSET 0x00000000
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#define CYFLD_SFLASH_BROM_PROT_LIMIT__SIZE 0x00000008
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#define CYREG_SFLASH_CPUSS_PRIV_FLASH 0x0ffff14c
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#define CYFLD_SFLASH_FLASH_PROT_LIMIT__OFFSET 0x00000000
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#define CYFLD_SFLASH_FLASH_PROT_LIMIT__SIZE 0x0000000b
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#define CYREG_SFLASH_CPUSS_PRIV_ROM_SROM 0x0ffff14e
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#define CYFLD_SFLASH_SROM_PROT_LIMIT__OFFSET 0x00000000
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#define CYFLD_SFLASH_SROM_PROT_LIMIT__SIZE 0x0000000a
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#define CYREG_SFLASH_HIB_KEY_DELAY 0x0ffff150
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#define CYFLD_SFLASH_WAKEUP_HOLDOFF__OFFSET 0x00000000
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#define CYFLD_SFLASH_WAKEUP_HOLDOFF__SIZE 0x0000000a
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#define CYREG_SFLASH_DPSLP_KEY_DELAY 0x0ffff152
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#define CYREG_SFLASH_SWD_CONFIG 0x0ffff154
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#define CYFLD_SFLASH_SWD_SELECT__OFFSET 0x00000000
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#define CYFLD_SFLASH_SWD_SELECT__SIZE 0x00000001
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#define CYREG_SFLASH_INITIAL_SPCIF_TRIM_M1_DAC0 0x0ffff155
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#define CYFLD_SFLASH_IDAC__OFFSET 0x00000000
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#define CYFLD_SFLASH_IDAC__SIZE 0x00000005
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#define CYFLD_SFLASH_SLOPE__OFFSET 0x00000005
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#define CYFLD_SFLASH_SLOPE__SIZE 0x00000003
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#define CYREG_SFLASH_SWD_LISTEN 0x0ffff158
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#define CYFLD_SFLASH_CYCLES__OFFSET 0x00000000
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#define CYFLD_SFLASH_CYCLES__SIZE 0x00000020
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#define CYREG_SFLASH_FLASH_START 0x0ffff15c
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#define CYFLD_SFLASH_ADDRESS__OFFSET 0x00000000
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#define CYFLD_SFLASH_ADDRESS__SIZE 0x00000020
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#define CYREG_SFLASH_CSD_TRIM1_HVIDAC 0x0ffff160
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#define CYFLD_SFLASH_TRIM8__OFFSET 0x00000000
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#define CYFLD_SFLASH_TRIM8__SIZE 0x00000008
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#define CYREG_SFLASH_CSD_TRIM2_HVIDAC 0x0ffff161
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#define CYREG_SFLASH_CSD_TRIM1_CSD 0x0ffff162
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#define CYREG_SFLASH_CSD_TRIM2_CSD 0x0ffff163
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#define CYREG_SFLASH_SAR_TEMP_MULTIPLIER 0x0ffff164
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#define CYFLD_SFLASH_TEMP_MULTIPLIER__OFFSET 0x00000000
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#define CYFLD_SFLASH_TEMP_MULTIPLIER__SIZE 0x00000010
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#define CYREG_SFLASH_SAR_TEMP_OFFSET 0x0ffff166
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#define CYFLD_SFLASH_TEMP_OFFSET__OFFSET 0x00000000
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#define CYFLD_SFLASH_TEMP_OFFSET__SIZE 0x00000010
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#define CYREG_SFLASH_SKIP_CHECKSUM 0x0ffff169
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#define CYFLD_SFLASH_SKIP__OFFSET 0x00000000
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#define CYFLD_SFLASH_SKIP__SIZE 0x00000008
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#define CYREG_SFLASH_PROT_VIRGINKEY0 0x0ffff170
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#define CYFLD_SFLASH_KEY8__OFFSET 0x00000000
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#define CYFLD_SFLASH_KEY8__SIZE 0x00000008
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#define CYREG_SFLASH_PROT_VIRGINKEY1 0x0ffff171
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#define CYREG_SFLASH_PROT_VIRGINKEY2 0x0ffff172
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#define CYREG_SFLASH_PROT_VIRGINKEY3 0x0ffff173
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#define CYREG_SFLASH_PROT_VIRGINKEY4 0x0ffff174
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#define CYREG_SFLASH_PROT_VIRGINKEY5 0x0ffff175
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#define CYREG_SFLASH_PROT_VIRGINKEY6 0x0ffff176
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#define CYREG_SFLASH_PROT_VIRGINKEY7 0x0ffff177
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#define CYREG_SFLASH_DIE_LOT0 0x0ffff178
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#define CYFLD_SFLASH_LOT__OFFSET 0x00000000
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#define CYFLD_SFLASH_LOT__SIZE 0x00000008
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#define CYREG_SFLASH_DIE_LOT1 0x0ffff179
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#define CYREG_SFLASH_DIE_LOT2 0x0ffff17a
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#define CYREG_SFLASH_DIE_WAFER 0x0ffff17b
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#define CYFLD_SFLASH_WAFER__OFFSET 0x00000000
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#define CYFLD_SFLASH_WAFER__SIZE 0x00000008
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#define CYREG_SFLASH_DIE_X 0x0ffff17c
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#define CYFLD_SFLASH_X__OFFSET 0x00000000
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#define CYFLD_SFLASH_X__SIZE 0x00000008
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#define CYREG_SFLASH_DIE_Y 0x0ffff17d
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#define CYFLD_SFLASH_Y__OFFSET 0x00000000
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#define CYFLD_SFLASH_Y__SIZE 0x00000008
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#define CYREG_SFLASH_DIE_SORT 0x0ffff17e
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#define CYFLD_SFLASH_S1_PASS__OFFSET 0x00000000
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#define CYFLD_SFLASH_S1_PASS__SIZE 0x00000001
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#define CYFLD_SFLASH_S2_PASS__OFFSET 0x00000001
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#define CYFLD_SFLASH_S2_PASS__SIZE 0x00000001
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#define CYFLD_SFLASH_S3_PASS__OFFSET 0x00000002
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#define CYFLD_SFLASH_S3_PASS__SIZE 0x00000001
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#define CYFLD_SFLASH_CRI_PASS__OFFSET 0x00000003
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#define CYFLD_SFLASH_CRI_PASS__SIZE 0x00000001
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#define CYFLD_SFLASH_CHI_PASS__OFFSET 0x00000004
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#define CYFLD_SFLASH_CHI_PASS__SIZE 0x00000001
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#define CYFLD_SFLASH_ENG_PASS__OFFSET 0x00000005
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#define CYFLD_SFLASH_ENG_PASS__SIZE 0x00000001
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#define CYREG_SFLASH_DIE_MINOR 0x0ffff17f
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#define CYFLD_SFLASH_MINOR__OFFSET 0x00000000
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#define CYFLD_SFLASH_MINOR__SIZE 0x00000008
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#define CYREG_SFLASH_PE_TE_DATA0 0x0ffff180
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#define CYREG_SFLASH_PE_TE_DATA1 0x0ffff181
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#define CYREG_SFLASH_PE_TE_DATA2 0x0ffff182
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#define CYREG_SFLASH_PE_TE_DATA3 0x0ffff183
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#define CYREG_SFLASH_PE_TE_DATA4 0x0ffff184
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#define CYREG_SFLASH_PE_TE_DATA5 0x0ffff185
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#define CYREG_SFLASH_PE_TE_DATA6 0x0ffff186
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#define CYREG_SFLASH_PE_TE_DATA7 0x0ffff187
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#define CYREG_SFLASH_PE_TE_DATA8 0x0ffff188
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#define CYREG_SFLASH_PE_TE_DATA9 0x0ffff189
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#define CYREG_SFLASH_PE_TE_DATA10 0x0ffff18a
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#define CYREG_SFLASH_PE_TE_DATA11 0x0ffff18b
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#define CYREG_SFLASH_PE_TE_DATA12 0x0ffff18c
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#define CYREG_SFLASH_PE_TE_DATA13 0x0ffff18d
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#define CYREG_SFLASH_PE_TE_DATA14 0x0ffff18e
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#define CYREG_SFLASH_PE_TE_DATA15 0x0ffff18f
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#define CYREG_SFLASH_PE_TE_DATA16 0x0ffff190
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#define CYREG_SFLASH_PE_TE_DATA17 0x0ffff191
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#define CYREG_SFLASH_PE_TE_DATA18 0x0ffff192
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#define CYREG_SFLASH_PE_TE_DATA19 0x0ffff193
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#define CYREG_SFLASH_PE_TE_DATA20 0x0ffff194
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#define CYREG_SFLASH_PE_TE_DATA21 0x0ffff195
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#define CYREG_SFLASH_PE_TE_DATA22 0x0ffff196
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#define CYREG_SFLASH_PE_TE_DATA23 0x0ffff197
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#define CYREG_SFLASH_PE_TE_DATA24 0x0ffff198
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#define CYREG_SFLASH_PE_TE_DATA25 0x0ffff199
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#define CYREG_SFLASH_PE_TE_DATA26 0x0ffff19a
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#define CYREG_SFLASH_PE_TE_DATA27 0x0ffff19b
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#define CYREG_SFLASH_PE_TE_DATA28 0x0ffff19c
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#define CYREG_SFLASH_PE_TE_DATA29 0x0ffff19d
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#define CYREG_SFLASH_PE_TE_DATA30 0x0ffff19e
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#define CYREG_SFLASH_PE_TE_DATA31 0x0ffff19f
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#define CYREG_SFLASH_PP 0x0ffff1a0
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#define CYFLD_SFLASH_PERIOD__OFFSET 0x00000000
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#define CYFLD_SFLASH_PERIOD__SIZE 0x00000018
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#define CYFLD_SFLASH_PDAC__OFFSET 0x00000018
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#define CYFLD_SFLASH_PDAC__SIZE 0x00000004
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#define CYFLD_SFLASH_NDAC__OFFSET 0x0000001c
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#define CYFLD_SFLASH_NDAC__SIZE 0x00000004
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#define CYREG_SFLASH_E 0x0ffff1a4
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#define CYREG_SFLASH_P 0x0ffff1a8
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#define CYREG_SFLASH_EA_E 0x0ffff1ac
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#define CYREG_SFLASH_EA_P 0x0ffff1b0
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#define CYREG_SFLASH_ES_E 0x0ffff1b4
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#define CYREG_SFLASH_ES_P_EO 0x0ffff1b8
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#define CYREG_SFLASH_E_VCTAT 0x0ffff1bc
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#define CYFLD_SFLASH_VCTAT_SLOPE__OFFSET 0x00000000
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#define CYFLD_SFLASH_VCTAT_SLOPE__SIZE 0x00000004
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#define CYFLD_SFLASH_VCTAT_VOLTAGE__OFFSET 0x00000004
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#define CYFLD_SFLASH_VCTAT_VOLTAGE__SIZE 0x00000002
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#define CYFLD_SFLASH_VCTAT_ENABLE__OFFSET 0x00000006
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#define CYFLD_SFLASH_VCTAT_ENABLE__SIZE 0x00000001
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#define CYREG_SFLASH_P_VCTAT 0x0ffff1bd
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#define CYREG_SFLASH_IMO_MAXF0 0x0ffff1c0
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#define CYFLD_SFLASH_MAXFREQ__OFFSET 0x00000000
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#define CYFLD_SFLASH_MAXFREQ__SIZE 0x00000006
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#define CYREG_SFLASH_IMO_ABS0 0x0ffff1c1
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#define CYFLD_SFLASH_ABS_TRIM_IMO__OFFSET 0x00000000
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#define CYFLD_SFLASH_ABS_TRIM_IMO__SIZE 0x00000006
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#define CYREG_SFLASH_IMO_TMPCO0 0x0ffff1c2
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#define CYFLD_SFLASH_TMPCO_TRIM_IMO__OFFSET 0x00000000
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#define CYFLD_SFLASH_TMPCO_TRIM_IMO__SIZE 0x00000006
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#define CYREG_SFLASH_IMO_MAXF1 0x0ffff1c3
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#define CYREG_SFLASH_IMO_ABS1 0x0ffff1c4
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#define CYREG_SFLASH_IMO_TMPCO1 0x0ffff1c5
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#define CYREG_SFLASH_IMO_MAXF2 0x0ffff1c6
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#define CYREG_SFLASH_IMO_ABS2 0x0ffff1c7
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#define CYREG_SFLASH_IMO_TMPCO2 0x0ffff1c8
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#define CYREG_SFLASH_IMO_MAXF3 0x0ffff1c9
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#define CYREG_SFLASH_IMO_ABS3 0x0ffff1ca
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#define CYREG_SFLASH_IMO_TMPCO3 0x0ffff1cb
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#define CYREG_SFLASH_IMO_ABS4 0x0ffff1cc
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#define CYREG_SFLASH_IMO_TMPCO4 0x0ffff1cd
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#define CYREG_SFLASH_IMO_TRIM0 0x0ffff1d0
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#define CYFLD_SFLASH_OFFSET__OFFSET 0x00000000
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#define CYFLD_SFLASH_OFFSET__SIZE 0x00000008
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#define CYREG_SFLASH_IMO_TRIM1 0x0ffff1d1
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#define CYREG_SFLASH_IMO_TRIM2 0x0ffff1d2
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#define CYREG_SFLASH_IMO_TRIM3 0x0ffff1d3
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#define CYREG_SFLASH_IMO_TRIM4 0x0ffff1d4
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#define CYREG_SFLASH_IMO_TRIM5 0x0ffff1d5
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#define CYREG_SFLASH_IMO_TRIM6 0x0ffff1d6
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#define CYREG_SFLASH_IMO_TRIM7 0x0ffff1d7
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#define CYREG_SFLASH_IMO_TRIM8 0x0ffff1d8
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#define CYREG_SFLASH_IMO_TRIM9 0x0ffff1d9
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#define CYREG_SFLASH_IMO_TRIM10 0x0ffff1da
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#define CYREG_SFLASH_IMO_TRIM11 0x0ffff1db
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#define CYREG_SFLASH_IMO_TRIM12 0x0ffff1dc
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#define CYREG_SFLASH_IMO_TRIM13 0x0ffff1dd
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#define CYREG_SFLASH_IMO_TRIM14 0x0ffff1de
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#define CYREG_SFLASH_IMO_TRIM15 0x0ffff1df
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#define CYREG_SFLASH_IMO_TRIM16 0x0ffff1e0
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#define CYREG_SFLASH_IMO_TRIM17 0x0ffff1e1
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#define CYREG_SFLASH_IMO_TRIM18 0x0ffff1e2
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#define CYREG_SFLASH_IMO_TRIM19 0x0ffff1e3
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#define CYREG_SFLASH_IMO_TRIM20 0x0ffff1e4
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#define CYREG_SFLASH_IMO_TRIM21 0x0ffff1e5
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#define CYREG_SFLASH_IMO_TRIM22 0x0ffff1e6
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#define CYREG_SFLASH_IMO_TRIM23 0x0ffff1e7
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#define CYREG_SFLASH_IMO_TRIM24 0x0ffff1e8
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#define CYREG_SFLASH_IMO_TRIM25 0x0ffff1e9
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#define CYREG_SFLASH_IMO_TRIM26 0x0ffff1ea
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#define CYREG_SFLASH_IMO_TRIM27 0x0ffff1eb
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#define CYREG_SFLASH_IMO_TRIM28 0x0ffff1ec
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#define CYREG_SFLASH_IMO_TRIM29 0x0ffff1ed
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#define CYREG_SFLASH_IMO_TRIM30 0x0ffff1ee
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#define CYREG_SFLASH_IMO_TRIM31 0x0ffff1ef
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#define CYREG_SFLASH_IMO_TRIM32 0x0ffff1f0
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#define CYREG_SFLASH_IMO_TRIM33 0x0ffff1f1
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#define CYREG_SFLASH_IMO_TRIM34 0x0ffff1f2
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#define CYREG_SFLASH_IMO_TRIM35 0x0ffff1f3
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#define CYREG_SFLASH_IMO_TRIM36 0x0ffff1f4
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#define CYREG_SFLASH_IMO_TRIM37 0x0ffff1f5
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#define CYREG_SFLASH_IMO_TRIM38 0x0ffff1f6
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#define CYREG_SFLASH_IMO_TRIM39 0x0ffff1f7
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#define CYREG_SFLASH_IMO_TRIM40 0x0ffff1f8
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#define CYREG_SFLASH_IMO_TRIM41 0x0ffff1f9
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#define CYREG_SFLASH_IMO_TRIM42 0x0ffff1fa
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#define CYREG_SFLASH_IMO_TRIM43 0x0ffff1fb
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#define CYREG_SFLASH_IMO_TRIM44 0x0ffff1fc
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#define CYREG_SFLASH_IMO_TRIM45 0x0ffff1fd
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#define CYREG_SFLASH_CHECKSUM 0x0ffff1fe
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#define CYFLD_SFLASH_CHECKSUM__OFFSET 0x00000000
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#define CYFLD_SFLASH_CHECKSUM__SIZE 0x00000010
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH0 0x0ffff200
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#define CYFLD_SFLASH_BYTE_MEM__OFFSET 0x00000000
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#define CYFLD_SFLASH_BYTE_MEM__SIZE 0x00000008
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1 0x0ffff201
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH2 0x0ffff202
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH3 0x0ffff203
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH4 0x0ffff204
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH5 0x0ffff205
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH6 0x0ffff206
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH7 0x0ffff207
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH8 0x0ffff208
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH9 0x0ffff209
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH10 0x0ffff20a
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH11 0x0ffff20b
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH12 0x0ffff20c
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH13 0x0ffff20d
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH14 0x0ffff20e
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH15 0x0ffff20f
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH16 0x0ffff210
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH17 0x0ffff211
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH18 0x0ffff212
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH19 0x0ffff213
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH20 0x0ffff214
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH21 0x0ffff215
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH22 0x0ffff216
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH23 0x0ffff217
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH24 0x0ffff218
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH25 0x0ffff219
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH26 0x0ffff21a
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH27 0x0ffff21b
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH28 0x0ffff21c
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH29 0x0ffff21d
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH30 0x0ffff21e
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH31 0x0ffff21f
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH32 0x0ffff220
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH33 0x0ffff221
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH34 0x0ffff222
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH35 0x0ffff223
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH36 0x0ffff224
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH37 0x0ffff225
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH38 0x0ffff226
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH39 0x0ffff227
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH40 0x0ffff228
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH41 0x0ffff229
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH42 0x0ffff22a
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH43 0x0ffff22b
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH44 0x0ffff22c
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH45 0x0ffff22d
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH46 0x0ffff22e
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH47 0x0ffff22f
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH48 0x0ffff230
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH49 0x0ffff231
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH50 0x0ffff232
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH51 0x0ffff233
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH52 0x0ffff234
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH53 0x0ffff235
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH54 0x0ffff236
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH55 0x0ffff237
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH56 0x0ffff238
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH57 0x0ffff239
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH58 0x0ffff23a
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH59 0x0ffff23b
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH60 0x0ffff23c
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH61 0x0ffff23d
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH62 0x0ffff23e
|
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH63 0x0ffff23f
|
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH64 0x0ffff240
|
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH65 0x0ffff241
|
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH66 0x0ffff242
|
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH67 0x0ffff243
|
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH68 0x0ffff244
|
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH69 0x0ffff245
|
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH70 0x0ffff246
|
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH71 0x0ffff247
|
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH72 0x0ffff248
|
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH73 0x0ffff249
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH74 0x0ffff24a
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH75 0x0ffff24b
|
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH76 0x0ffff24c
|
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH77 0x0ffff24d
|
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH78 0x0ffff24e
|
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH79 0x0ffff24f
|
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH80 0x0ffff250
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH81 0x0ffff251
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH82 0x0ffff252
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH83 0x0ffff253
|
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH84 0x0ffff254
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH85 0x0ffff255
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH86 0x0ffff256
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH87 0x0ffff257
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH88 0x0ffff258
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH89 0x0ffff259
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH90 0x0ffff25a
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH91 0x0ffff25b
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH92 0x0ffff25c
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH93 0x0ffff25d
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH94 0x0ffff25e
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH95 0x0ffff25f
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH96 0x0ffff260
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH97 0x0ffff261
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH98 0x0ffff262
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH99 0x0ffff263
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH100 0x0ffff264
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH101 0x0ffff265
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH102 0x0ffff266
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH103 0x0ffff267
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH104 0x0ffff268
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH105 0x0ffff269
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH106 0x0ffff26a
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH107 0x0ffff26b
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH108 0x0ffff26c
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH109 0x0ffff26d
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH110 0x0ffff26e
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH111 0x0ffff26f
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH112 0x0ffff270
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH113 0x0ffff271
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH114 0x0ffff272
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH115 0x0ffff273
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH116 0x0ffff274
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH117 0x0ffff275
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH118 0x0ffff276
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH119 0x0ffff277
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH120 0x0ffff278
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH121 0x0ffff279
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH122 0x0ffff27a
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH123 0x0ffff27b
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH124 0x0ffff27c
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH125 0x0ffff27d
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH126 0x0ffff27e
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH127 0x0ffff27f
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH128 0x0ffff280
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH129 0x0ffff281
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH130 0x0ffff282
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH131 0x0ffff283
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH132 0x0ffff284
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH133 0x0ffff285
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH134 0x0ffff286
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH135 0x0ffff287
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH136 0x0ffff288
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH137 0x0ffff289
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH138 0x0ffff28a
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH139 0x0ffff28b
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH140 0x0ffff28c
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH141 0x0ffff28d
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH142 0x0ffff28e
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH143 0x0ffff28f
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH144 0x0ffff290
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH145 0x0ffff291
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH146 0x0ffff292
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH147 0x0ffff293
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH148 0x0ffff294
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH149 0x0ffff295
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH150 0x0ffff296
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH151 0x0ffff297
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH152 0x0ffff298
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH153 0x0ffff299
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH154 0x0ffff29a
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH155 0x0ffff29b
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH156 0x0ffff29c
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH157 0x0ffff29d
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH158 0x0ffff29e
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH159 0x0ffff29f
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH160 0x0ffff2a0
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH161 0x0ffff2a1
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH162 0x0ffff2a2
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH163 0x0ffff2a3
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH164 0x0ffff2a4
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH165 0x0ffff2a5
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH166 0x0ffff2a6
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH167 0x0ffff2a7
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH168 0x0ffff2a8
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH169 0x0ffff2a9
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH170 0x0ffff2aa
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH171 0x0ffff2ab
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH172 0x0ffff2ac
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH173 0x0ffff2ad
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH174 0x0ffff2ae
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH175 0x0ffff2af
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH176 0x0ffff2b0
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH177 0x0ffff2b1
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH178 0x0ffff2b2
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH179 0x0ffff2b3
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH180 0x0ffff2b4
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH181 0x0ffff2b5
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH182 0x0ffff2b6
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH183 0x0ffff2b7
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH184 0x0ffff2b8
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH185 0x0ffff2b9
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH186 0x0ffff2ba
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH187 0x0ffff2bb
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH188 0x0ffff2bc
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH189 0x0ffff2bd
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH190 0x0ffff2be
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH191 0x0ffff2bf
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH192 0x0ffff2c0
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH193 0x0ffff2c1
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH194 0x0ffff2c2
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH195 0x0ffff2c3
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH196 0x0ffff2c4
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH197 0x0ffff2c5
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH198 0x0ffff2c6
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH199 0x0ffff2c7
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH200 0x0ffff2c8
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH201 0x0ffff2c9
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH202 0x0ffff2ca
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH203 0x0ffff2cb
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH204 0x0ffff2cc
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH205 0x0ffff2cd
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH206 0x0ffff2ce
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH207 0x0ffff2cf
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH208 0x0ffff2d0
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH209 0x0ffff2d1
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH210 0x0ffff2d2
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH211 0x0ffff2d3
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH212 0x0ffff2d4
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH213 0x0ffff2d5
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH214 0x0ffff2d6
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH215 0x0ffff2d7
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH216 0x0ffff2d8
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH217 0x0ffff2d9
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH218 0x0ffff2da
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH219 0x0ffff2db
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH220 0x0ffff2dc
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH221 0x0ffff2dd
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH222 0x0ffff2de
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH223 0x0ffff2df
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH224 0x0ffff2e0
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH225 0x0ffff2e1
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH226 0x0ffff2e2
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH227 0x0ffff2e3
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH228 0x0ffff2e4
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH229 0x0ffff2e5
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH230 0x0ffff2e6
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH231 0x0ffff2e7
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH232 0x0ffff2e8
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH233 0x0ffff2e9
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH234 0x0ffff2ea
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH235 0x0ffff2eb
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH236 0x0ffff2ec
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH237 0x0ffff2ed
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH238 0x0ffff2ee
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH239 0x0ffff2ef
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH240 0x0ffff2f0
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH241 0x0ffff2f1
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH242 0x0ffff2f2
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH243 0x0ffff2f3
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH244 0x0ffff2f4
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH245 0x0ffff2f5
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH246 0x0ffff2f6
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH247 0x0ffff2f7
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH248 0x0ffff2f8
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH249 0x0ffff2f9
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH250 0x0ffff2fa
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH251 0x0ffff2fb
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH252 0x0ffff2fc
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH253 0x0ffff2fd
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH254 0x0ffff2fe
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH255 0x0ffff2ff
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH256 0x0ffff300
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH257 0x0ffff301
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH258 0x0ffff302
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH259 0x0ffff303
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH260 0x0ffff304
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH261 0x0ffff305
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH262 0x0ffff306
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH263 0x0ffff307
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH264 0x0ffff308
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH265 0x0ffff309
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH266 0x0ffff30a
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH267 0x0ffff30b
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH268 0x0ffff30c
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH269 0x0ffff30d
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH270 0x0ffff30e
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH271 0x0ffff30f
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH272 0x0ffff310
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH273 0x0ffff311
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH274 0x0ffff312
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH275 0x0ffff313
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH276 0x0ffff314
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH277 0x0ffff315
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH278 0x0ffff316
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH279 0x0ffff317
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH280 0x0ffff318
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH281 0x0ffff319
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH282 0x0ffff31a
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH283 0x0ffff31b
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH284 0x0ffff31c
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH285 0x0ffff31d
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH286 0x0ffff31e
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH287 0x0ffff31f
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH288 0x0ffff320
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH289 0x0ffff321
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH290 0x0ffff322
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH291 0x0ffff323
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH292 0x0ffff324
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH293 0x0ffff325
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH294 0x0ffff326
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH295 0x0ffff327
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH296 0x0ffff328
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH297 0x0ffff329
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH298 0x0ffff32a
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH299 0x0ffff32b
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH300 0x0ffff32c
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH301 0x0ffff32d
|
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH302 0x0ffff32e
|
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH303 0x0ffff32f
|
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH304 0x0ffff330
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH305 0x0ffff331
|
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH306 0x0ffff332
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH307 0x0ffff333
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH308 0x0ffff334
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH309 0x0ffff335
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH310 0x0ffff336
|
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH311 0x0ffff337
|
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH312 0x0ffff338
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH313 0x0ffff339
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH314 0x0ffff33a
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH315 0x0ffff33b
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH316 0x0ffff33c
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH317 0x0ffff33d
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH318 0x0ffff33e
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH319 0x0ffff33f
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#define CYREG_SFLASH_MACRO_0_FREE_SFLASH320 0x0ffff340
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH321 0x0ffff341
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH322 0x0ffff342
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH323 0x0ffff343
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH324 0x0ffff344
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH325 0x0ffff345
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH326 0x0ffff346
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH327 0x0ffff347
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH328 0x0ffff348
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH329 0x0ffff349
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH330 0x0ffff34a
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH331 0x0ffff34b
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH332 0x0ffff34c
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH333 0x0ffff34d
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH334 0x0ffff34e
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH335 0x0ffff34f
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH336 0x0ffff350
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH337 0x0ffff351
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH338 0x0ffff352
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH339 0x0ffff353
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH340 0x0ffff354
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|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH341 0x0ffff355
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH342 0x0ffff356
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH343 0x0ffff357
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH344 0x0ffff358
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH345 0x0ffff359
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH346 0x0ffff35a
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH347 0x0ffff35b
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH348 0x0ffff35c
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH349 0x0ffff35d
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH350 0x0ffff35e
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH351 0x0ffff35f
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH352 0x0ffff360
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH353 0x0ffff361
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH354 0x0ffff362
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH355 0x0ffff363
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH356 0x0ffff364
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH357 0x0ffff365
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH358 0x0ffff366
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH359 0x0ffff367
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH360 0x0ffff368
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH361 0x0ffff369
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH362 0x0ffff36a
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH363 0x0ffff36b
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH364 0x0ffff36c
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH365 0x0ffff36d
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH366 0x0ffff36e
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH367 0x0ffff36f
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH368 0x0ffff370
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH369 0x0ffff371
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH370 0x0ffff372
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH371 0x0ffff373
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH372 0x0ffff374
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH373 0x0ffff375
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH374 0x0ffff376
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH375 0x0ffff377
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH376 0x0ffff378
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH377 0x0ffff379
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH378 0x0ffff37a
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH379 0x0ffff37b
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH380 0x0ffff37c
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH381 0x0ffff37d
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH382 0x0ffff37e
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH383 0x0ffff37f
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH384 0x0ffff380
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH385 0x0ffff381
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH386 0x0ffff382
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH387 0x0ffff383
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH388 0x0ffff384
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH389 0x0ffff385
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH390 0x0ffff386
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH391 0x0ffff387
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH392 0x0ffff388
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH393 0x0ffff389
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH394 0x0ffff38a
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH395 0x0ffff38b
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH396 0x0ffff38c
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH397 0x0ffff38d
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH398 0x0ffff38e
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH399 0x0ffff38f
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH400 0x0ffff390
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH401 0x0ffff391
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH402 0x0ffff392
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH403 0x0ffff393
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH404 0x0ffff394
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH405 0x0ffff395
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH406 0x0ffff396
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH407 0x0ffff397
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH408 0x0ffff398
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH409 0x0ffff399
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH410 0x0ffff39a
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH411 0x0ffff39b
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH412 0x0ffff39c
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH413 0x0ffff39d
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH414 0x0ffff39e
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH415 0x0ffff39f
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH416 0x0ffff3a0
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH417 0x0ffff3a1
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH418 0x0ffff3a2
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH419 0x0ffff3a3
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH420 0x0ffff3a4
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH421 0x0ffff3a5
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH422 0x0ffff3a6
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH423 0x0ffff3a7
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH424 0x0ffff3a8
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH425 0x0ffff3a9
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH426 0x0ffff3aa
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH427 0x0ffff3ab
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH428 0x0ffff3ac
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH429 0x0ffff3ad
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH430 0x0ffff3ae
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH431 0x0ffff3af
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH432 0x0ffff3b0
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH433 0x0ffff3b1
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH434 0x0ffff3b2
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH435 0x0ffff3b3
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH436 0x0ffff3b4
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH437 0x0ffff3b5
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH438 0x0ffff3b6
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH439 0x0ffff3b7
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH440 0x0ffff3b8
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH441 0x0ffff3b9
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH442 0x0ffff3ba
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH443 0x0ffff3bb
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH444 0x0ffff3bc
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH445 0x0ffff3bd
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH446 0x0ffff3be
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH447 0x0ffff3bf
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH448 0x0ffff3c0
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH449 0x0ffff3c1
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH450 0x0ffff3c2
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH451 0x0ffff3c3
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH452 0x0ffff3c4
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH453 0x0ffff3c5
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH454 0x0ffff3c6
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH455 0x0ffff3c7
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH456 0x0ffff3c8
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH457 0x0ffff3c9
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH458 0x0ffff3ca
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH459 0x0ffff3cb
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH460 0x0ffff3cc
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH461 0x0ffff3cd
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH462 0x0ffff3ce
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH463 0x0ffff3cf
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH464 0x0ffff3d0
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH465 0x0ffff3d1
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH466 0x0ffff3d2
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH467 0x0ffff3d3
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH468 0x0ffff3d4
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH469 0x0ffff3d5
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH470 0x0ffff3d6
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH471 0x0ffff3d7
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH472 0x0ffff3d8
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH473 0x0ffff3d9
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH474 0x0ffff3da
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH475 0x0ffff3db
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH476 0x0ffff3dc
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH477 0x0ffff3dd
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH478 0x0ffff3de
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH479 0x0ffff3df
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH480 0x0ffff3e0
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH481 0x0ffff3e1
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH482 0x0ffff3e2
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH483 0x0ffff3e3
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH484 0x0ffff3e4
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH485 0x0ffff3e5
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH486 0x0ffff3e6
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH487 0x0ffff3e7
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH488 0x0ffff3e8
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH489 0x0ffff3e9
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH490 0x0ffff3ea
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH491 0x0ffff3eb
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH492 0x0ffff3ec
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH493 0x0ffff3ed
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH494 0x0ffff3ee
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH495 0x0ffff3ef
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH496 0x0ffff3f0
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH497 0x0ffff3f1
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH498 0x0ffff3f2
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH499 0x0ffff3f3
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH500 0x0ffff3f4
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH501 0x0ffff3f5
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH502 0x0ffff3f6
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH503 0x0ffff3f7
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH504 0x0ffff3f8
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH505 0x0ffff3f9
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH506 0x0ffff3fa
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH507 0x0ffff3fb
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH508 0x0ffff3fc
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH509 0x0ffff3fd
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH510 0x0ffff3fe
|
|
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH511 0x0ffff3ff
|
|
#define CYREG_SFLASH_ALT_PROT_ROW0 0x0ffff400
|
|
#define CYREG_SFLASH_ALT_PROT_ROW1 0x0ffff401
|
|
#define CYREG_SFLASH_ALT_PROT_ROW2 0x0ffff402
|
|
#define CYREG_SFLASH_ALT_PROT_ROW3 0x0ffff403
|
|
#define CYREG_SFLASH_ALT_PROT_ROW4 0x0ffff404
|
|
#define CYREG_SFLASH_ALT_PROT_ROW5 0x0ffff405
|
|
#define CYREG_SFLASH_ALT_PROT_ROW6 0x0ffff406
|
|
#define CYREG_SFLASH_ALT_PROT_ROW7 0x0ffff407
|
|
#define CYREG_SFLASH_ALT_PROT_ROW8 0x0ffff408
|
|
#define CYREG_SFLASH_ALT_PROT_ROW9 0x0ffff409
|
|
#define CYREG_SFLASH_ALT_PROT_ROW10 0x0ffff40a
|
|
#define CYREG_SFLASH_ALT_PROT_ROW11 0x0ffff40b
|
|
#define CYREG_SFLASH_ALT_PROT_ROW12 0x0ffff40c
|
|
#define CYREG_SFLASH_ALT_PROT_ROW13 0x0ffff40d
|
|
#define CYREG_SFLASH_ALT_PROT_ROW14 0x0ffff40e
|
|
#define CYREG_SFLASH_ALT_PROT_ROW15 0x0ffff40f
|
|
#define CYREG_SFLASH_ALT_PROT_ROW16 0x0ffff410
|
|
#define CYREG_SFLASH_ALT_PROT_ROW17 0x0ffff411
|
|
#define CYREG_SFLASH_ALT_PROT_ROW18 0x0ffff412
|
|
#define CYREG_SFLASH_ALT_PROT_ROW19 0x0ffff413
|
|
#define CYREG_SFLASH_ALT_PROT_ROW20 0x0ffff414
|
|
#define CYREG_SFLASH_ALT_PROT_ROW21 0x0ffff415
|
|
#define CYREG_SFLASH_ALT_PROT_ROW22 0x0ffff416
|
|
#define CYREG_SFLASH_ALT_PROT_ROW23 0x0ffff417
|
|
#define CYREG_SFLASH_ALT_PROT_ROW24 0x0ffff418
|
|
#define CYREG_SFLASH_ALT_PROT_ROW25 0x0ffff419
|
|
#define CYREG_SFLASH_ALT_PROT_ROW26 0x0ffff41a
|
|
#define CYREG_SFLASH_ALT_PROT_ROW27 0x0ffff41b
|
|
#define CYREG_SFLASH_ALT_PROT_ROW28 0x0ffff41c
|
|
#define CYREG_SFLASH_ALT_PROT_ROW29 0x0ffff41d
|
|
#define CYREG_SFLASH_ALT_PROT_ROW30 0x0ffff41e
|
|
#define CYREG_SFLASH_ALT_PROT_ROW31 0x0ffff41f
|
|
#define CYREG_SFLASH_ALT_PROT_ROW32 0x0ffff420
|
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#define CYREG_SFLASH_ALT_PROT_ROW33 0x0ffff421
|
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#define CYREG_SFLASH_ALT_PROT_ROW34 0x0ffff422
|
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#define CYREG_SFLASH_ALT_PROT_ROW35 0x0ffff423
|
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#define CYREG_SFLASH_ALT_PROT_ROW36 0x0ffff424
|
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#define CYREG_SFLASH_ALT_PROT_ROW37 0x0ffff425
|
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#define CYREG_SFLASH_ALT_PROT_ROW38 0x0ffff426
|
|
#define CYREG_SFLASH_ALT_PROT_ROW39 0x0ffff427
|
|
#define CYREG_SFLASH_ALT_PROT_ROW40 0x0ffff428
|
|
#define CYREG_SFLASH_ALT_PROT_ROW41 0x0ffff429
|
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#define CYREG_SFLASH_ALT_PROT_ROW42 0x0ffff42a
|
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#define CYREG_SFLASH_ALT_PROT_ROW43 0x0ffff42b
|
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#define CYREG_SFLASH_ALT_PROT_ROW44 0x0ffff42c
|
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#define CYREG_SFLASH_ALT_PROT_ROW45 0x0ffff42d
|
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#define CYREG_SFLASH_ALT_PROT_ROW46 0x0ffff42e
|
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#define CYREG_SFLASH_ALT_PROT_ROW47 0x0ffff42f
|
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#define CYREG_SFLASH_ALT_PROT_ROW48 0x0ffff430
|
|
#define CYREG_SFLASH_ALT_PROT_ROW49 0x0ffff431
|
|
#define CYREG_SFLASH_ALT_PROT_ROW50 0x0ffff432
|
|
#define CYREG_SFLASH_ALT_PROT_ROW51 0x0ffff433
|
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#define CYREG_SFLASH_ALT_PROT_ROW52 0x0ffff434
|
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#define CYREG_SFLASH_ALT_PROT_ROW53 0x0ffff435
|
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#define CYREG_SFLASH_ALT_PROT_ROW54 0x0ffff436
|
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#define CYREG_SFLASH_ALT_PROT_ROW55 0x0ffff437
|
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#define CYREG_SFLASH_ALT_PROT_ROW56 0x0ffff438
|
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#define CYREG_SFLASH_ALT_PROT_ROW57 0x0ffff439
|
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#define CYREG_SFLASH_ALT_PROT_ROW58 0x0ffff43a
|
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#define CYREG_SFLASH_ALT_PROT_ROW59 0x0ffff43b
|
|
#define CYREG_SFLASH_ALT_PROT_ROW60 0x0ffff43c
|
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#define CYREG_SFLASH_ALT_PROT_ROW61 0x0ffff43d
|
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#define CYREG_SFLASH_ALT_PROT_ROW62 0x0ffff43e
|
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#define CYREG_SFLASH_ALT_PROT_ROW63 0x0ffff43f
|
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#define CYREG_SFLASH_ALT_PROT_ROW64 0x0ffff440
|
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#define CYREG_SFLASH_ALT_PROT_ROW65 0x0ffff441
|
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#define CYREG_SFLASH_ALT_PROT_ROW66 0x0ffff442
|
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#define CYREG_SFLASH_ALT_PROT_ROW67 0x0ffff443
|
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#define CYREG_SFLASH_ALT_PROT_ROW68 0x0ffff444
|
|
#define CYREG_SFLASH_ALT_PROT_ROW69 0x0ffff445
|
|
#define CYREG_SFLASH_ALT_PROT_ROW70 0x0ffff446
|
|
#define CYREG_SFLASH_ALT_PROT_ROW71 0x0ffff447
|
|
#define CYREG_SFLASH_ALT_PROT_ROW72 0x0ffff448
|
|
#define CYREG_SFLASH_ALT_PROT_ROW73 0x0ffff449
|
|
#define CYREG_SFLASH_ALT_PROT_ROW74 0x0ffff44a
|
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#define CYREG_SFLASH_ALT_PROT_ROW75 0x0ffff44b
|
|
#define CYREG_SFLASH_ALT_PROT_ROW76 0x0ffff44c
|
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#define CYREG_SFLASH_ALT_PROT_ROW77 0x0ffff44d
|
|
#define CYREG_SFLASH_ALT_PROT_ROW78 0x0ffff44e
|
|
#define CYREG_SFLASH_ALT_PROT_ROW79 0x0ffff44f
|
|
#define CYREG_SFLASH_ALT_PROT_ROW80 0x0ffff450
|
|
#define CYREG_SFLASH_ALT_PROT_ROW81 0x0ffff451
|
|
#define CYREG_SFLASH_ALT_PROT_ROW82 0x0ffff452
|
|
#define CYREG_SFLASH_ALT_PROT_ROW83 0x0ffff453
|
|
#define CYREG_SFLASH_ALT_PROT_ROW84 0x0ffff454
|
|
#define CYREG_SFLASH_ALT_PROT_ROW85 0x0ffff455
|
|
#define CYREG_SFLASH_ALT_PROT_ROW86 0x0ffff456
|
|
#define CYREG_SFLASH_ALT_PROT_ROW87 0x0ffff457
|
|
#define CYREG_SFLASH_ALT_PROT_ROW88 0x0ffff458
|
|
#define CYREG_SFLASH_ALT_PROT_ROW89 0x0ffff459
|
|
#define CYREG_SFLASH_ALT_PROT_ROW90 0x0ffff45a
|
|
#define CYREG_SFLASH_ALT_PROT_ROW91 0x0ffff45b
|
|
#define CYREG_SFLASH_ALT_PROT_ROW92 0x0ffff45c
|
|
#define CYREG_SFLASH_ALT_PROT_ROW93 0x0ffff45d
|
|
#define CYREG_SFLASH_ALT_PROT_ROW94 0x0ffff45e
|
|
#define CYREG_SFLASH_ALT_PROT_ROW95 0x0ffff45f
|
|
#define CYREG_SFLASH_ALT_PROT_ROW96 0x0ffff460
|
|
#define CYREG_SFLASH_ALT_PROT_ROW97 0x0ffff461
|
|
#define CYREG_SFLASH_ALT_PROT_ROW98 0x0ffff462
|
|
#define CYREG_SFLASH_ALT_PROT_ROW99 0x0ffff463
|
|
#define CYREG_SFLASH_ALT_PROT_ROW100 0x0ffff464
|
|
#define CYREG_SFLASH_ALT_PROT_ROW101 0x0ffff465
|
|
#define CYREG_SFLASH_ALT_PROT_ROW102 0x0ffff466
|
|
#define CYREG_SFLASH_ALT_PROT_ROW103 0x0ffff467
|
|
#define CYREG_SFLASH_ALT_PROT_ROW104 0x0ffff468
|
|
#define CYREG_SFLASH_ALT_PROT_ROW105 0x0ffff469
|
|
#define CYREG_SFLASH_ALT_PROT_ROW106 0x0ffff46a
|
|
#define CYREG_SFLASH_ALT_PROT_ROW107 0x0ffff46b
|
|
#define CYREG_SFLASH_ALT_PROT_ROW108 0x0ffff46c
|
|
#define CYREG_SFLASH_ALT_PROT_ROW109 0x0ffff46d
|
|
#define CYREG_SFLASH_ALT_PROT_ROW110 0x0ffff46e
|
|
#define CYREG_SFLASH_ALT_PROT_ROW111 0x0ffff46f
|
|
#define CYREG_SFLASH_ALT_PROT_ROW112 0x0ffff470
|
|
#define CYREG_SFLASH_ALT_PROT_ROW113 0x0ffff471
|
|
#define CYREG_SFLASH_ALT_PROT_ROW114 0x0ffff472
|
|
#define CYREG_SFLASH_ALT_PROT_ROW115 0x0ffff473
|
|
#define CYREG_SFLASH_ALT_PROT_ROW116 0x0ffff474
|
|
#define CYREG_SFLASH_ALT_PROT_ROW117 0x0ffff475
|
|
#define CYREG_SFLASH_ALT_PROT_ROW118 0x0ffff476
|
|
#define CYREG_SFLASH_ALT_PROT_ROW119 0x0ffff477
|
|
#define CYREG_SFLASH_ALT_PROT_ROW120 0x0ffff478
|
|
#define CYREG_SFLASH_ALT_PROT_ROW121 0x0ffff479
|
|
#define CYREG_SFLASH_ALT_PROT_ROW122 0x0ffff47a
|
|
#define CYREG_SFLASH_ALT_PROT_ROW123 0x0ffff47b
|
|
#define CYREG_SFLASH_ALT_PROT_ROW124 0x0ffff47c
|
|
#define CYREG_SFLASH_ALT_PROT_ROW125 0x0ffff47d
|
|
#define CYREG_SFLASH_ALT_PROT_ROW126 0x0ffff47e
|
|
#define CYREG_SFLASH_ALT_PROT_ROW127 0x0ffff47f
|
|
#define CYREG_SFLASH_ALT_PROT_ROW128 0x0ffff480
|
|
#define CYREG_SFLASH_ALT_PROT_ROW129 0x0ffff481
|
|
#define CYREG_SFLASH_ALT_PROT_ROW130 0x0ffff482
|
|
#define CYREG_SFLASH_ALT_PROT_ROW131 0x0ffff483
|
|
#define CYREG_SFLASH_ALT_PROT_ROW132 0x0ffff484
|
|
#define CYREG_SFLASH_ALT_PROT_ROW133 0x0ffff485
|
|
#define CYREG_SFLASH_ALT_PROT_ROW134 0x0ffff486
|
|
#define CYREG_SFLASH_ALT_PROT_ROW135 0x0ffff487
|
|
#define CYREG_SFLASH_ALT_PROT_ROW136 0x0ffff488
|
|
#define CYREG_SFLASH_ALT_PROT_ROW137 0x0ffff489
|
|
#define CYREG_SFLASH_ALT_PROT_ROW138 0x0ffff48a
|
|
#define CYREG_SFLASH_ALT_PROT_ROW139 0x0ffff48b
|
|
#define CYREG_SFLASH_ALT_PROT_ROW140 0x0ffff48c
|
|
#define CYREG_SFLASH_ALT_PROT_ROW141 0x0ffff48d
|
|
#define CYREG_SFLASH_ALT_PROT_ROW142 0x0ffff48e
|
|
#define CYREG_SFLASH_ALT_PROT_ROW143 0x0ffff48f
|
|
#define CYREG_SFLASH_ALT_PROT_ROW144 0x0ffff490
|
|
#define CYREG_SFLASH_ALT_PROT_ROW145 0x0ffff491
|
|
#define CYREG_SFLASH_ALT_PROT_ROW146 0x0ffff492
|
|
#define CYREG_SFLASH_ALT_PROT_ROW147 0x0ffff493
|
|
#define CYREG_SFLASH_ALT_PROT_ROW148 0x0ffff494
|
|
#define CYREG_SFLASH_ALT_PROT_ROW149 0x0ffff495
|
|
#define CYREG_SFLASH_ALT_PROT_ROW150 0x0ffff496
|
|
#define CYREG_SFLASH_ALT_PROT_ROW151 0x0ffff497
|
|
#define CYREG_SFLASH_ALT_PROT_ROW152 0x0ffff498
|
|
#define CYREG_SFLASH_ALT_PROT_ROW153 0x0ffff499
|
|
#define CYREG_SFLASH_ALT_PROT_ROW154 0x0ffff49a
|
|
#define CYREG_SFLASH_ALT_PROT_ROW155 0x0ffff49b
|
|
#define CYREG_SFLASH_ALT_PROT_ROW156 0x0ffff49c
|
|
#define CYREG_SFLASH_ALT_PROT_ROW157 0x0ffff49d
|
|
#define CYREG_SFLASH_ALT_PROT_ROW158 0x0ffff49e
|
|
#define CYREG_SFLASH_ALT_PROT_ROW159 0x0ffff49f
|
|
#define CYREG_SFLASH_ALT_PROT_ROW160 0x0ffff4a0
|
|
#define CYREG_SFLASH_ALT_PROT_ROW161 0x0ffff4a1
|
|
#define CYREG_SFLASH_ALT_PROT_ROW162 0x0ffff4a2
|
|
#define CYREG_SFLASH_ALT_PROT_ROW163 0x0ffff4a3
|
|
#define CYREG_SFLASH_ALT_PROT_ROW164 0x0ffff4a4
|
|
#define CYREG_SFLASH_ALT_PROT_ROW165 0x0ffff4a5
|
|
#define CYREG_SFLASH_ALT_PROT_ROW166 0x0ffff4a6
|
|
#define CYREG_SFLASH_ALT_PROT_ROW167 0x0ffff4a7
|
|
#define CYREG_SFLASH_ALT_PROT_ROW168 0x0ffff4a8
|
|
#define CYREG_SFLASH_ALT_PROT_ROW169 0x0ffff4a9
|
|
#define CYREG_SFLASH_ALT_PROT_ROW170 0x0ffff4aa
|
|
#define CYREG_SFLASH_ALT_PROT_ROW171 0x0ffff4ab
|
|
#define CYREG_SFLASH_ALT_PROT_ROW172 0x0ffff4ac
|
|
#define CYREG_SFLASH_ALT_PROT_ROW173 0x0ffff4ad
|
|
#define CYREG_SFLASH_ALT_PROT_ROW174 0x0ffff4ae
|
|
#define CYREG_SFLASH_ALT_PROT_ROW175 0x0ffff4af
|
|
#define CYREG_SFLASH_ALT_PROT_ROW176 0x0ffff4b0
|
|
#define CYREG_SFLASH_ALT_PROT_ROW177 0x0ffff4b1
|
|
#define CYREG_SFLASH_ALT_PROT_ROW178 0x0ffff4b2
|
|
#define CYREG_SFLASH_ALT_PROT_ROW179 0x0ffff4b3
|
|
#define CYREG_SFLASH_ALT_PROT_ROW180 0x0ffff4b4
|
|
#define CYREG_SFLASH_ALT_PROT_ROW181 0x0ffff4b5
|
|
#define CYREG_SFLASH_ALT_PROT_ROW182 0x0ffff4b6
|
|
#define CYREG_SFLASH_ALT_PROT_ROW183 0x0ffff4b7
|
|
#define CYREG_SFLASH_ALT_PROT_ROW184 0x0ffff4b8
|
|
#define CYREG_SFLASH_ALT_PROT_ROW185 0x0ffff4b9
|
|
#define CYREG_SFLASH_ALT_PROT_ROW186 0x0ffff4ba
|
|
#define CYREG_SFLASH_ALT_PROT_ROW187 0x0ffff4bb
|
|
#define CYREG_SFLASH_ALT_PROT_ROW188 0x0ffff4bc
|
|
#define CYREG_SFLASH_ALT_PROT_ROW189 0x0ffff4bd
|
|
#define CYREG_SFLASH_ALT_PROT_ROW190 0x0ffff4be
|
|
#define CYREG_SFLASH_ALT_PROT_ROW191 0x0ffff4bf
|
|
#define CYREG_SFLASH_ALT_PROT_ROW192 0x0ffff4c0
|
|
#define CYREG_SFLASH_ALT_PROT_ROW193 0x0ffff4c1
|
|
#define CYREG_SFLASH_ALT_PROT_ROW194 0x0ffff4c2
|
|
#define CYREG_SFLASH_ALT_PROT_ROW195 0x0ffff4c3
|
|
#define CYREG_SFLASH_ALT_PROT_ROW196 0x0ffff4c4
|
|
#define CYREG_SFLASH_ALT_PROT_ROW197 0x0ffff4c5
|
|
#define CYREG_SFLASH_ALT_PROT_ROW198 0x0ffff4c6
|
|
#define CYREG_SFLASH_ALT_PROT_ROW199 0x0ffff4c7
|
|
#define CYREG_SFLASH_ALT_PROT_ROW200 0x0ffff4c8
|
|
#define CYREG_SFLASH_ALT_PROT_ROW201 0x0ffff4c9
|
|
#define CYREG_SFLASH_ALT_PROT_ROW202 0x0ffff4ca
|
|
#define CYREG_SFLASH_ALT_PROT_ROW203 0x0ffff4cb
|
|
#define CYREG_SFLASH_ALT_PROT_ROW204 0x0ffff4cc
|
|
#define CYREG_SFLASH_ALT_PROT_ROW205 0x0ffff4cd
|
|
#define CYREG_SFLASH_ALT_PROT_ROW206 0x0ffff4ce
|
|
#define CYREG_SFLASH_ALT_PROT_ROW207 0x0ffff4cf
|
|
#define CYREG_SFLASH_ALT_PROT_ROW208 0x0ffff4d0
|
|
#define CYREG_SFLASH_ALT_PROT_ROW209 0x0ffff4d1
|
|
#define CYREG_SFLASH_ALT_PROT_ROW210 0x0ffff4d2
|
|
#define CYREG_SFLASH_ALT_PROT_ROW211 0x0ffff4d3
|
|
#define CYREG_SFLASH_ALT_PROT_ROW212 0x0ffff4d4
|
|
#define CYREG_SFLASH_ALT_PROT_ROW213 0x0ffff4d5
|
|
#define CYREG_SFLASH_ALT_PROT_ROW214 0x0ffff4d6
|
|
#define CYREG_SFLASH_ALT_PROT_ROW215 0x0ffff4d7
|
|
#define CYREG_SFLASH_ALT_PROT_ROW216 0x0ffff4d8
|
|
#define CYREG_SFLASH_ALT_PROT_ROW217 0x0ffff4d9
|
|
#define CYREG_SFLASH_ALT_PROT_ROW218 0x0ffff4da
|
|
#define CYREG_SFLASH_ALT_PROT_ROW219 0x0ffff4db
|
|
#define CYREG_SFLASH_ALT_PROT_ROW220 0x0ffff4dc
|
|
#define CYREG_SFLASH_ALT_PROT_ROW221 0x0ffff4dd
|
|
#define CYREG_SFLASH_ALT_PROT_ROW222 0x0ffff4de
|
|
#define CYREG_SFLASH_ALT_PROT_ROW223 0x0ffff4df
|
|
#define CYREG_SFLASH_ALT_PROT_ROW224 0x0ffff4e0
|
|
#define CYREG_SFLASH_ALT_PROT_ROW225 0x0ffff4e1
|
|
#define CYREG_SFLASH_ALT_PROT_ROW226 0x0ffff4e2
|
|
#define CYREG_SFLASH_ALT_PROT_ROW227 0x0ffff4e3
|
|
#define CYREG_SFLASH_ALT_PROT_ROW228 0x0ffff4e4
|
|
#define CYREG_SFLASH_ALT_PROT_ROW229 0x0ffff4e5
|
|
#define CYREG_SFLASH_ALT_PROT_ROW230 0x0ffff4e6
|
|
#define CYREG_SFLASH_ALT_PROT_ROW231 0x0ffff4e7
|
|
#define CYREG_SFLASH_ALT_PROT_ROW232 0x0ffff4e8
|
|
#define CYREG_SFLASH_ALT_PROT_ROW233 0x0ffff4e9
|
|
#define CYREG_SFLASH_ALT_PROT_ROW234 0x0ffff4ea
|
|
#define CYREG_SFLASH_ALT_PROT_ROW235 0x0ffff4eb
|
|
#define CYREG_SFLASH_ALT_PROT_ROW236 0x0ffff4ec
|
|
#define CYREG_SFLASH_ALT_PROT_ROW237 0x0ffff4ed
|
|
#define CYREG_SFLASH_ALT_PROT_ROW238 0x0ffff4ee
|
|
#define CYREG_SFLASH_ALT_PROT_ROW239 0x0ffff4ef
|
|
#define CYREG_SFLASH_ALT_PROT_ROW240 0x0ffff4f0
|
|
#define CYREG_SFLASH_ALT_PROT_ROW241 0x0ffff4f1
|
|
#define CYREG_SFLASH_ALT_PROT_ROW242 0x0ffff4f2
|
|
#define CYREG_SFLASH_ALT_PROT_ROW243 0x0ffff4f3
|
|
#define CYREG_SFLASH_ALT_PROT_ROW244 0x0ffff4f4
|
|
#define CYREG_SFLASH_ALT_PROT_ROW245 0x0ffff4f5
|
|
#define CYREG_SFLASH_ALT_PROT_ROW246 0x0ffff4f6
|
|
#define CYREG_SFLASH_ALT_PROT_ROW247 0x0ffff4f7
|
|
#define CYREG_SFLASH_ALT_PROT_ROW248 0x0ffff4f8
|
|
#define CYREG_SFLASH_ALT_PROT_ROW249 0x0ffff4f9
|
|
#define CYREG_SFLASH_ALT_PROT_ROW250 0x0ffff4fa
|
|
#define CYREG_SFLASH_ALT_PROT_ROW251 0x0ffff4fb
|
|
#define CYREG_SFLASH_ALT_PROT_ROW252 0x0ffff4fc
|
|
#define CYREG_SFLASH_ALT_PROT_ROW253 0x0ffff4fd
|
|
#define CYREG_SFLASH_ALT_PROT_ROW254 0x0ffff4fe
|
|
#define CYREG_SFLASH_ALT_PROT_ROW255 0x0ffff4ff
|
|
#define CYREG_SFLASH_ALT_PP 0x0ffff5a0
|
|
#define CYREG_SFLASH_ALT_E 0x0ffff5a4
|
|
#define CYREG_SFLASH_ALT_P 0x0ffff5a8
|
|
#define CYREG_SFLASH_ALT_EA_E 0x0ffff5ac
|
|
#define CYREG_SFLASH_ALT_EA_P 0x0ffff5b0
|
|
#define CYREG_SFLASH_ALT_ES_E 0x0ffff5b4
|
|
#define CYREG_SFLASH_ALT_ES_P_EO 0x0ffff5b8
|
|
#define CYREG_SFLASH_ALT_E_VCTAT 0x0ffff5bc
|
|
#define CYREG_SFLASH_ALT_P_VCTAT 0x0ffff5bd
|
|
#define CYDEV_ROM_BASE 0x10000000
|
|
#define CYDEV_ROM_SIZE 0x00002000
|
|
#define CYREG_ROM_DATA_MBASE 0x10000000
|
|
#define CYREG_ROM_DATA_MSIZE 0x00002000
|
|
#define CYDEV_SRAM_BASE 0x20000000
|
|
#define CYDEV_SRAM_SIZE 0x00004000
|
|
#define CYREG_SRAM_DATA_MBASE 0x20000000
|
|
#define CYREG_SRAM_DATA_MSIZE 0x00004000
|
|
#define CYDEV_PERI_BASE 0x40010000
|
|
#define CYDEV_PERI_SIZE 0x00010000
|
|
#define CYREG_PERI_DIV_CMD 0x40010000
|
|
#define CYFLD_PERI_SEL_DIV__OFFSET 0x00000000
|
|
#define CYFLD_PERI_SEL_DIV__SIZE 0x00000006
|
|
#define CYFLD_PERI_SEL_TYPE__OFFSET 0x00000006
|
|
#define CYFLD_PERI_SEL_TYPE__SIZE 0x00000002
|
|
#define CYFLD_PERI_PA_SEL_DIV__OFFSET 0x00000008
|
|
#define CYFLD_PERI_PA_SEL_DIV__SIZE 0x00000006
|
|
#define CYFLD_PERI_PA_SEL_TYPE__OFFSET 0x0000000e
|
|
#define CYFLD_PERI_PA_SEL_TYPE__SIZE 0x00000002
|
|
#define CYFLD_PERI_DISABLE__OFFSET 0x0000001e
|
|
#define CYFLD_PERI_DISABLE__SIZE 0x00000001
|
|
#define CYFLD_PERI_ENABLE__OFFSET 0x0000001f
|
|
#define CYFLD_PERI_ENABLE__SIZE 0x00000001
|
|
#define CYREG_PERI_PCLK_CTL0 0x40010100
|
|
#define CYREG_PERI_PCLK_CTL1 0x40010104
|
|
#define CYREG_PERI_PCLK_CTL2 0x40010108
|
|
#define CYREG_PERI_PCLK_CTL3 0x4001010c
|
|
#define CYREG_PERI_PCLK_CTL4 0x40010110
|
|
#define CYREG_PERI_PCLK_CTL5 0x40010114
|
|
#define CYREG_PERI_PCLK_CTL6 0x40010118
|
|
#define CYREG_PERI_PCLK_CTL7 0x4001011c
|
|
#define CYREG_PERI_PCLK_CTL8 0x40010120
|
|
#define CYREG_PERI_PCLK_CTL9 0x40010124
|
|
#define CYREG_PERI_PCLK_CTL10 0x40010128
|
|
#define CYREG_PERI_PCLK_CTL11 0x4001012c
|
|
#define CYREG_PERI_PCLK_CTL12 0x40010130
|
|
#define CYREG_PERI_PCLK_CTL13 0x40010134
|
|
#define CYREG_PERI_PCLK_CTL14 0x40010138
|
|
#define CYREG_PERI_PCLK_CTL15 0x4001013c
|
|
#define CYREG_PERI_DIV_16_CTL0 0x40010300
|
|
#define CYFLD_PERI_EN__OFFSET 0x00000000
|
|
#define CYFLD_PERI_EN__SIZE 0x00000001
|
|
#define CYFLD_PERI_INT16_DIV__OFFSET 0x00000008
|
|
#define CYFLD_PERI_INT16_DIV__SIZE 0x00000010
|
|
#define CYREG_PERI_DIV_16_CTL1 0x40010304
|
|
#define CYREG_PERI_DIV_16_CTL2 0x40010308
|
|
#define CYREG_PERI_DIV_16_CTL3 0x4001030c
|
|
#define CYREG_PERI_DIV_16_CTL4 0x40010310
|
|
#define CYREG_PERI_DIV_16_CTL5 0x40010314
|
|
#define CYREG_PERI_DIV_16_CTL6 0x40010318
|
|
#define CYREG_PERI_DIV_16_CTL7 0x4001031c
|
|
#define CYREG_PERI_DIV_16_CTL8 0x40010320
|
|
#define CYREG_PERI_DIV_16_CTL9 0x40010324
|
|
#define CYREG_PERI_DIV_16_5_CTL0 0x40010400
|
|
#define CYFLD_PERI_FRAC5_DIV__OFFSET 0x00000003
|
|
#define CYFLD_PERI_FRAC5_DIV__SIZE 0x00000005
|
|
#define CYREG_PERI_DIV_16_5_CTL1 0x40010404
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#define CYDEV_HSIOM_BASE 0x40020000
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#define CYDEV_HSIOM_SIZE 0x00004000
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#define CYREG_HSIOM_PORT_SEL0 0x40020000
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#define CYFLD_HSIOM_IO0_SEL__OFFSET 0x00000000
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#define CYFLD_HSIOM_IO0_SEL__SIZE 0x00000004
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#define CYVAL_HSIOM_IO0_SEL_GPIO 0x00000000
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#define CYVAL_HSIOM_IO0_SEL_GPIO_DSI 0x00000001
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#define CYVAL_HSIOM_IO0_SEL_DSI_DSI 0x00000002
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#define CYVAL_HSIOM_IO0_SEL_DSI_GPIO 0x00000003
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#define CYVAL_HSIOM_IO0_SEL_CSD_SENSE 0x00000004
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#define CYVAL_HSIOM_IO0_SEL_CSD_SHIELD 0x00000005
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#define CYVAL_HSIOM_IO0_SEL_AMUXA 0x00000006
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#define CYVAL_HSIOM_IO0_SEL_AMUXB 0x00000007
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#define CYVAL_HSIOM_IO0_SEL_ACT_0 0x00000008
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#define CYVAL_HSIOM_IO0_SEL_ACT_1 0x00000009
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#define CYVAL_HSIOM_IO0_SEL_ACT_2 0x0000000a
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#define CYVAL_HSIOM_IO0_SEL_ACT_3 0x0000000b
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#define CYVAL_HSIOM_IO0_SEL_LCD_COM 0x0000000c
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#define CYVAL_HSIOM_IO0_SEL_LCD_SEG 0x0000000d
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#define CYVAL_HSIOM_IO0_SEL_DS_0 0x0000000c
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#define CYVAL_HSIOM_IO0_SEL_DS_1 0x0000000d
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#define CYVAL_HSIOM_IO0_SEL_DS_2 0x0000000e
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#define CYVAL_HSIOM_IO0_SEL_DS_3 0x0000000f
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#define CYFLD_HSIOM_IO1_SEL__OFFSET 0x00000004
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#define CYFLD_HSIOM_IO1_SEL__SIZE 0x00000004
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#define CYFLD_HSIOM_IO2_SEL__OFFSET 0x00000008
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#define CYFLD_HSIOM_IO2_SEL__SIZE 0x00000004
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#define CYFLD_HSIOM_IO3_SEL__OFFSET 0x0000000c
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#define CYFLD_HSIOM_IO3_SEL__SIZE 0x00000004
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#define CYFLD_HSIOM_IO4_SEL__OFFSET 0x00000010
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#define CYFLD_HSIOM_IO4_SEL__SIZE 0x00000004
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#define CYFLD_HSIOM_IO5_SEL__OFFSET 0x00000014
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#define CYFLD_HSIOM_IO5_SEL__SIZE 0x00000004
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#define CYFLD_HSIOM_IO6_SEL__OFFSET 0x00000018
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#define CYFLD_HSIOM_IO6_SEL__SIZE 0x00000004
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#define CYFLD_HSIOM_IO7_SEL__OFFSET 0x0000001c
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#define CYFLD_HSIOM_IO7_SEL__SIZE 0x00000004
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#define CYREG_HSIOM_PORT_SEL1 0x40020100
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#define CYREG_HSIOM_PORT_SEL2 0x40020200
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#define CYREG_HSIOM_PORT_SEL3 0x40020300
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#define CYREG_HSIOM_PORT_SEL4 0x40020400
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#define CYREG_HSIOM_PORT_SEL5 0x40020500
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#define CYREG_HSIOM_PORT_SEL6 0x40020600
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#define CYREG_HSIOM_AMUX_SPLIT_CTL0 0x40022100
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#define CYFLD_HSIOM_SWITCH_AA_SL__OFFSET 0x00000000
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#define CYFLD_HSIOM_SWITCH_AA_SL__SIZE 0x00000001
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#define CYFLD_HSIOM_SWITCH_AA_SR__OFFSET 0x00000001
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#define CYFLD_HSIOM_SWITCH_AA_SR__SIZE 0x00000001
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#define CYFLD_HSIOM_SWITCH_AA_S0__OFFSET 0x00000002
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#define CYFLD_HSIOM_SWITCH_AA_S0__SIZE 0x00000001
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#define CYFLD_HSIOM_SWITCH_BB_SL__OFFSET 0x00000004
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#define CYFLD_HSIOM_SWITCH_BB_SL__SIZE 0x00000001
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#define CYFLD_HSIOM_SWITCH_BB_SR__OFFSET 0x00000005
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#define CYFLD_HSIOM_SWITCH_BB_SR__SIZE 0x00000001
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#define CYFLD_HSIOM_SWITCH_BB_S0__OFFSET 0x00000006
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#define CYFLD_HSIOM_SWITCH_BB_S0__SIZE 0x00000001
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#define CYREG_HSIOM_AMUX_SPLIT_CTL1 0x40022104
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#define CYREG_HSIOM_AMUX_SPLIT_CTL2 0x40022108
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#define CYDEV_TST_BASE 0x40030000
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#define CYDEV_TST_SIZE 0x00010000
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#define CYREG_TST_CTRL 0x40030000
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#define CYFLD_TST_SCAN_MODE__OFFSET 0x0000001d
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#define CYFLD_TST_SCAN_MODE__SIZE 0x00000001
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#define CYREG_TST_ADFT_CTRL 0x40030004
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#define CYFLD_TST_ADFT_MUX_SEL_0A__OFFSET 0x00000000
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#define CYFLD_TST_ADFT_MUX_SEL_0A__SIZE 0x00000003
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#define CYVAL_TST_ADFT_MUX_SEL_0A_NC0 0x00000000
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#define CYVAL_TST_ADFT_MUX_SEL_0A_IN1 0x00000001
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#define CYVAL_TST_ADFT_MUX_SEL_0A_IN2 0x00000002
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#define CYVAL_TST_ADFT_MUX_SEL_0A_IN3 0x00000003
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#define CYVAL_TST_ADFT_MUX_SEL_0A_IN4 0x00000004
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#define CYVAL_TST_ADFT_MUX_SEL_0A_IN5 0x00000005
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#define CYVAL_TST_ADFT_MUX_SEL_0A_IN6 0x00000006
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#define CYVAL_TST_ADFT_MUX_SEL_0A_NC7 0x00000007
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#define CYFLD_TST_ADFT_MUX_SEL_1A__OFFSET 0x00000003
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#define CYFLD_TST_ADFT_MUX_SEL_1A__SIZE 0x00000003
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#define CYFLD_TST_ADFT_MUX_SEL_0B__OFFSET 0x00000006
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#define CYFLD_TST_ADFT_MUX_SEL_0B__SIZE 0x00000003
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#define CYFLD_TST_ADFT_MUX_SEL_1B__OFFSET 0x00000009
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#define CYFLD_TST_ADFT_MUX_SEL_1B__SIZE 0x00000003
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#define CYFLD_TST_ENABLE__OFFSET 0x0000001f
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#define CYFLD_TST_ENABLE__SIZE 0x00000001
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#define CYREG_TST_DDFT_CTRL 0x40030008
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#define CYFLD_TST_DFT_SEL0__OFFSET 0x00000000
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#define CYFLD_TST_DFT_SEL0__SIZE 0x00000006
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#define CYFLD_TST_DFT_SEL1__OFFSET 0x00000008
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#define CYFLD_TST_DFT_SEL1__SIZE 0x00000006
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#define CYREG_TST_MODE 0x40030014
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#define CYFLD_TST_SWD_CONNECTED__OFFSET 0x00000002
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#define CYFLD_TST_SWD_CONNECTED__SIZE 0x00000001
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#define CYFLD_TST_POR_BYPASS__OFFSET 0x0000001e
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#define CYFLD_TST_POR_BYPASS__SIZE 0x00000001
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#define CYFLD_TST_TEST_MODE__OFFSET 0x0000001f
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#define CYFLD_TST_TEST_MODE__SIZE 0x00000001
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#define CYREG_TST_TRIM_CNTR1 0x40030018
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#define CYFLD_TST_COUNTER__OFFSET 0x00000000
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#define CYFLD_TST_COUNTER__SIZE 0x00000010
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#define CYFLD_TST_COUNTER_DONE__OFFSET 0x0000001f
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#define CYFLD_TST_COUNTER_DONE__SIZE 0x00000001
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#define CYREG_TST_TRIM_CNTR2 0x4003001c
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#define CYDEV_GPIO_BASE 0x40040000
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#define CYDEV_GPIO_SIZE 0x00004000
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#define CYDEV_GPIO_PRT0_BASE 0x40040000
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#define CYDEV_GPIO_PRT0_SIZE 0x00000100
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#define CYREG_GPIO_PRT0_DR 0x40040000
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#define CYFLD_GPIO_PRT_DATA0__OFFSET 0x00000000
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#define CYFLD_GPIO_PRT_DATA0__SIZE 0x00000001
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#define CYFLD_GPIO_PRT_DATA1__OFFSET 0x00000001
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#define CYFLD_GPIO_PRT_DATA1__SIZE 0x00000001
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#define CYFLD_GPIO_PRT_DATA2__OFFSET 0x00000002
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#define CYFLD_GPIO_PRT_DATA2__SIZE 0x00000001
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#define CYFLD_GPIO_PRT_DATA3__OFFSET 0x00000003
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#define CYFLD_GPIO_PRT_DATA3__SIZE 0x00000001
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#define CYFLD_GPIO_PRT_DATA4__OFFSET 0x00000004
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#define CYFLD_GPIO_PRT_DATA4__SIZE 0x00000001
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#define CYFLD_GPIO_PRT_DATA5__OFFSET 0x00000005
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#define CYFLD_GPIO_PRT_DATA5__SIZE 0x00000001
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#define CYFLD_GPIO_PRT_DATA6__OFFSET 0x00000006
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#define CYFLD_GPIO_PRT_DATA6__SIZE 0x00000001
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#define CYFLD_GPIO_PRT_DATA7__OFFSET 0x00000007
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#define CYFLD_GPIO_PRT_DATA7__SIZE 0x00000001
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#define CYREG_GPIO_PRT0_PS 0x40040004
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#define CYFLD_GPIO_PRT_FLT_DATA__OFFSET 0x00000008
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#define CYFLD_GPIO_PRT_FLT_DATA__SIZE 0x00000001
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#define CYREG_GPIO_PRT0_PC 0x40040008
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#define CYFLD_GPIO_PRT_DM0__OFFSET 0x00000000
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#define CYFLD_GPIO_PRT_DM0__SIZE 0x00000003
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#define CYVAL_GPIO_PRT_DM0_OFF 0x00000000
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#define CYVAL_GPIO_PRT_DM0_INPUT 0x00000001
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#define CYVAL_GPIO_PRT_DM0_0_PU 0x00000002
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#define CYVAL_GPIO_PRT_DM0_PD_1 0x00000003
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#define CYVAL_GPIO_PRT_DM0_0_Z 0x00000004
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#define CYVAL_GPIO_PRT_DM0_Z_1 0x00000005
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#define CYVAL_GPIO_PRT_DM0_0_1 0x00000006
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#define CYVAL_GPIO_PRT_DM0_PD_PU 0x00000007
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#define CYFLD_GPIO_PRT_DM1__OFFSET 0x00000003
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#define CYFLD_GPIO_PRT_DM1__SIZE 0x00000003
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#define CYFLD_GPIO_PRT_DM2__OFFSET 0x00000006
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#define CYFLD_GPIO_PRT_DM2__SIZE 0x00000003
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#define CYFLD_GPIO_PRT_DM3__OFFSET 0x00000009
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#define CYFLD_GPIO_PRT_DM3__SIZE 0x00000003
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#define CYFLD_GPIO_PRT_DM4__OFFSET 0x0000000c
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#define CYFLD_GPIO_PRT_DM4__SIZE 0x00000003
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#define CYFLD_GPIO_PRT_DM5__OFFSET 0x0000000f
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#define CYFLD_GPIO_PRT_DM5__SIZE 0x00000003
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#define CYFLD_GPIO_PRT_DM6__OFFSET 0x00000012
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#define CYFLD_GPIO_PRT_DM6__SIZE 0x00000003
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#define CYFLD_GPIO_PRT_DM7__OFFSET 0x00000015
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#define CYFLD_GPIO_PRT_DM7__SIZE 0x00000003
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#define CYFLD_GPIO_PRT_PORT_VTRIP_SEL__OFFSET 0x00000018
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#define CYFLD_GPIO_PRT_PORT_VTRIP_SEL__SIZE 0x00000001
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#define CYFLD_GPIO_PRT_PORT_SLOW__OFFSET 0x00000019
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#define CYFLD_GPIO_PRT_PORT_SLOW__SIZE 0x00000001
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#define CYVAL_GPIO_PRT_PORT_SLOW_PORT_SLEW_CTL_0 0x00000000
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#define CYVAL_GPIO_PRT_PORT_SLOW_PORT_SLEW_CTL_1 0x00000001
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#define CYVAL_GPIO_PRT_PORT_SLOW_PORT_SLEW_CTL_2 0x00000002
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#define CYVAL_GPIO_PRT_PORT_SLOW_PORT_SLEW_CTL_3 0x00000003
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#define CYFLD_GPIO_PRT_PORT_IB_MODE_SEL__OFFSET 0x0000001e
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#define CYFLD_GPIO_PRT_PORT_IB_MODE_SEL__SIZE 0x00000002
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#define CYREG_GPIO_PRT0_INTR_CFG 0x4004000c
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#define CYFLD_GPIO_PRT_EDGE0_SEL__OFFSET 0x00000000
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#define CYFLD_GPIO_PRT_EDGE0_SEL__SIZE 0x00000002
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#define CYVAL_GPIO_PRT_EDGE0_SEL_DISABLE 0x00000000
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#define CYVAL_GPIO_PRT_EDGE0_SEL_RISING 0x00000001
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#define CYVAL_GPIO_PRT_EDGE0_SEL_FALLING 0x00000002
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#define CYVAL_GPIO_PRT_EDGE0_SEL_BOTH 0x00000003
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#define CYFLD_GPIO_PRT_EDGE1_SEL__OFFSET 0x00000002
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#define CYFLD_GPIO_PRT_EDGE1_SEL__SIZE 0x00000002
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#define CYFLD_GPIO_PRT_EDGE2_SEL__OFFSET 0x00000004
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#define CYFLD_GPIO_PRT_EDGE2_SEL__SIZE 0x00000002
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#define CYFLD_GPIO_PRT_EDGE3_SEL__OFFSET 0x00000006
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#define CYFLD_GPIO_PRT_EDGE3_SEL__SIZE 0x00000002
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#define CYFLD_GPIO_PRT_EDGE4_SEL__OFFSET 0x00000008
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#define CYFLD_GPIO_PRT_EDGE4_SEL__SIZE 0x00000002
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#define CYFLD_GPIO_PRT_EDGE5_SEL__OFFSET 0x0000000a
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#define CYFLD_GPIO_PRT_EDGE5_SEL__SIZE 0x00000002
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#define CYFLD_GPIO_PRT_EDGE6_SEL__OFFSET 0x0000000c
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#define CYFLD_GPIO_PRT_EDGE6_SEL__SIZE 0x00000002
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#define CYFLD_GPIO_PRT_EDGE7_SEL__OFFSET 0x0000000e
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#define CYFLD_GPIO_PRT_EDGE7_SEL__SIZE 0x00000002
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#define CYFLD_GPIO_PRT_FLT_EDGE_SEL__OFFSET 0x00000010
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#define CYFLD_GPIO_PRT_FLT_EDGE_SEL__SIZE 0x00000002
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#define CYVAL_GPIO_PRT_FLT_EDGE_SEL_DISABLE 0x00000000
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#define CYVAL_GPIO_PRT_FLT_EDGE_SEL_RISING 0x00000001
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#define CYVAL_GPIO_PRT_FLT_EDGE_SEL_FALLING 0x00000002
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#define CYVAL_GPIO_PRT_FLT_EDGE_SEL_BOTH 0x00000003
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#define CYFLD_GPIO_PRT_FLT_SEL__OFFSET 0x00000012
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#define CYFLD_GPIO_PRT_FLT_SEL__SIZE 0x00000003
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#define CYREG_GPIO_PRT0_INTR 0x40040010
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#define CYFLD_GPIO_PRT_PS_DATA0__OFFSET 0x00000010
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#define CYFLD_GPIO_PRT_PS_DATA0__SIZE 0x00000001
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#define CYFLD_GPIO_PRT_PS_DATA1__OFFSET 0x00000011
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#define CYFLD_GPIO_PRT_PS_DATA1__SIZE 0x00000001
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#define CYFLD_GPIO_PRT_PS_DATA2__OFFSET 0x00000012
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#define CYFLD_GPIO_PRT_PS_DATA2__SIZE 0x00000001
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#define CYFLD_GPIO_PRT_PS_DATA3__OFFSET 0x00000013
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#define CYFLD_GPIO_PRT_PS_DATA3__SIZE 0x00000001
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#define CYFLD_GPIO_PRT_PS_DATA4__OFFSET 0x00000014
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#define CYFLD_GPIO_PRT_PS_DATA4__SIZE 0x00000001
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#define CYFLD_GPIO_PRT_PS_DATA5__OFFSET 0x00000015
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#define CYFLD_GPIO_PRT_PS_DATA5__SIZE 0x00000001
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#define CYFLD_GPIO_PRT_PS_DATA6__OFFSET 0x00000016
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#define CYFLD_GPIO_PRT_PS_DATA6__SIZE 0x00000001
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#define CYFLD_GPIO_PRT_PS_DATA7__OFFSET 0x00000017
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#define CYFLD_GPIO_PRT_PS_DATA7__SIZE 0x00000001
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#define CYFLD_GPIO_PRT_PS_FLT_DATA__OFFSET 0x00000018
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#define CYFLD_GPIO_PRT_PS_FLT_DATA__SIZE 0x00000001
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#define CYREG_GPIO_PRT0_PC2 0x40040018
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#define CYFLD_GPIO_PRT_INP_DIS0__OFFSET 0x00000000
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#define CYFLD_GPIO_PRT_INP_DIS0__SIZE 0x00000001
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#define CYFLD_GPIO_PRT_INP_DIS1__OFFSET 0x00000001
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#define CYFLD_GPIO_PRT_INP_DIS1__SIZE 0x00000001
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#define CYFLD_GPIO_PRT_INP_DIS2__OFFSET 0x00000002
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#define CYFLD_GPIO_PRT_INP_DIS2__SIZE 0x00000001
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#define CYFLD_GPIO_PRT_INP_DIS3__OFFSET 0x00000003
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#define CYFLD_GPIO_PRT_INP_DIS3__SIZE 0x00000001
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#define CYFLD_GPIO_PRT_INP_DIS4__OFFSET 0x00000004
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#define CYFLD_GPIO_PRT_INP_DIS4__SIZE 0x00000001
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#define CYFLD_GPIO_PRT_INP_DIS5__OFFSET 0x00000005
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#define CYFLD_GPIO_PRT_INP_DIS5__SIZE 0x00000001
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#define CYFLD_GPIO_PRT_INP_DIS6__OFFSET 0x00000006
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#define CYFLD_GPIO_PRT_INP_DIS6__SIZE 0x00000001
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#define CYFLD_GPIO_PRT_INP_DIS7__OFFSET 0x00000007
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#define CYFLD_GPIO_PRT_INP_DIS7__SIZE 0x00000001
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#define CYREG_GPIO_PRT0_DR_SET 0x40040040
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#define CYFLD_GPIO_PRT_DATA__OFFSET 0x00000000
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#define CYFLD_GPIO_PRT_DATA__SIZE 0x00000008
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#define CYREG_GPIO_PRT0_DR_CLR 0x40040044
|
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#define CYREG_GPIO_PRT0_DR_INV 0x40040048
|
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#define CYDEV_GPIO_PRT1_BASE 0x40040100
|
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#define CYDEV_GPIO_PRT1_SIZE 0x00000100
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#define CYREG_GPIO_PRT1_DR 0x40040100
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#define CYREG_GPIO_PRT1_PS 0x40040104
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#define CYREG_GPIO_PRT1_PC 0x40040108
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#define CYREG_GPIO_PRT1_INTR_CFG 0x4004010c
|
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#define CYREG_GPIO_PRT1_INTR 0x40040110
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#define CYREG_GPIO_PRT1_PC2 0x40040118
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#define CYREG_GPIO_PRT1_DR_SET 0x40040140
|
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#define CYREG_GPIO_PRT1_DR_CLR 0x40040144
|
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#define CYREG_GPIO_PRT1_DR_INV 0x40040148
|
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#define CYDEV_GPIO_PRT2_BASE 0x40040200
|
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#define CYDEV_GPIO_PRT2_SIZE 0x00000100
|
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#define CYREG_GPIO_PRT2_DR 0x40040200
|
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#define CYREG_GPIO_PRT2_PS 0x40040204
|
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#define CYREG_GPIO_PRT2_PC 0x40040208
|
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#define CYREG_GPIO_PRT2_INTR_CFG 0x4004020c
|
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#define CYREG_GPIO_PRT2_INTR 0x40040210
|
|
#define CYREG_GPIO_PRT2_PC2 0x40040218
|
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#define CYREG_GPIO_PRT2_DR_SET 0x40040240
|
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#define CYREG_GPIO_PRT2_DR_CLR 0x40040244
|
|
#define CYREG_GPIO_PRT2_DR_INV 0x40040248
|
|
#define CYDEV_GPIO_PRT3_BASE 0x40040300
|
|
#define CYDEV_GPIO_PRT3_SIZE 0x00000100
|
|
#define CYREG_GPIO_PRT3_DR 0x40040300
|
|
#define CYREG_GPIO_PRT3_PS 0x40040304
|
|
#define CYREG_GPIO_PRT3_PC 0x40040308
|
|
#define CYREG_GPIO_PRT3_INTR_CFG 0x4004030c
|
|
#define CYREG_GPIO_PRT3_INTR 0x40040310
|
|
#define CYREG_GPIO_PRT3_PC2 0x40040318
|
|
#define CYREG_GPIO_PRT3_DR_SET 0x40040340
|
|
#define CYREG_GPIO_PRT3_DR_CLR 0x40040344
|
|
#define CYREG_GPIO_PRT3_DR_INV 0x40040348
|
|
#define CYDEV_GPIO_PRT4_BASE 0x40040400
|
|
#define CYDEV_GPIO_PRT4_SIZE 0x00000100
|
|
#define CYREG_GPIO_PRT4_DR 0x40040400
|
|
#define CYREG_GPIO_PRT4_PS 0x40040404
|
|
#define CYREG_GPIO_PRT4_PC 0x40040408
|
|
#define CYREG_GPIO_PRT4_INTR_CFG 0x4004040c
|
|
#define CYREG_GPIO_PRT4_INTR 0x40040410
|
|
#define CYREG_GPIO_PRT4_PC2 0x40040418
|
|
#define CYREG_GPIO_PRT4_DR_SET 0x40040440
|
|
#define CYREG_GPIO_PRT4_DR_CLR 0x40040444
|
|
#define CYREG_GPIO_PRT4_DR_INV 0x40040448
|
|
#define CYDEV_GPIO_PRT5_BASE 0x40040500
|
|
#define CYDEV_GPIO_PRT5_SIZE 0x00000100
|
|
#define CYREG_GPIO_PRT5_DR 0x40040500
|
|
#define CYREG_GPIO_PRT5_PS 0x40040504
|
|
#define CYREG_GPIO_PRT5_PC 0x40040508
|
|
#define CYFLD_GPIO_PRT_PORT_HYST_TRIM__OFFSET 0x0000001b
|
|
#define CYFLD_GPIO_PRT_PORT_HYST_TRIM__SIZE 0x00000001
|
|
#define CYFLD_GPIO_PRT_PORT_SLEW_CTL__OFFSET 0x0000001c
|
|
#define CYFLD_GPIO_PRT_PORT_SLEW_CTL__SIZE 0x00000002
|
|
#define CYVAL_GPIO_PRT_PORT_SLEW_CTL_PORT_SLEW_CTL_0 0x00000000
|
|
#define CYVAL_GPIO_PRT_PORT_SLEW_CTL_PORT_SLEW_CTL_1 0x00000001
|
|
#define CYVAL_GPIO_PRT_PORT_SLEW_CTL_PORT_SLEW_CTL_2 0x00000002
|
|
#define CYVAL_GPIO_PRT_PORT_SLEW_CTL_PORT_SLEW_CTL_3 0x00000003
|
|
#define CYREG_GPIO_PRT5_INTR_CFG 0x4004050c
|
|
#define CYREG_GPIO_PRT5_INTR 0x40040510
|
|
#define CYREG_GPIO_PRT5_PC2 0x40040518
|
|
#define CYREG_GPIO_PRT5_DR_SET 0x40040540
|
|
#define CYREG_GPIO_PRT5_DR_CLR 0x40040544
|
|
#define CYREG_GPIO_PRT5_DR_INV 0x40040548
|
|
#define CYDEV_GPIO_PRT6_BASE 0x40040600
|
|
#define CYDEV_GPIO_PRT6_SIZE 0x00000100
|
|
#define CYREG_GPIO_PRT6_DR 0x40040600
|
|
#define CYREG_GPIO_PRT6_PS 0x40040604
|
|
#define CYREG_GPIO_PRT6_PC 0x40040608
|
|
#define CYREG_GPIO_PRT6_INTR_CFG 0x4004060c
|
|
#define CYREG_GPIO_PRT6_INTR 0x40040610
|
|
#define CYREG_GPIO_PRT6_PC2 0x40040618
|
|
#define CYREG_GPIO_PRT6_DR_SET 0x40040640
|
|
#define CYREG_GPIO_PRT6_DR_CLR 0x40040644
|
|
#define CYREG_GPIO_PRT6_DR_INV 0x40040648
|
|
#define CYREG_GPIO_INTR_CAUSE 0x40041000
|
|
#define CYFLD_GPIO_PORT_INT__OFFSET 0x00000000
|
|
#define CYFLD_GPIO_PORT_INT__SIZE 0x00000007
|
|
#define CYREG_PWR_CONTROL 0x400b0000
|
|
#define CYFLD__POWER_MODE__OFFSET 0x00000000
|
|
#define CYFLD__POWER_MODE__SIZE 0x00000004
|
|
#define CYVAL__POWER_MODE_RESET 0x00000000
|
|
#define CYVAL__POWER_MODE_ACTIVE 0x00000001
|
|
#define CYVAL__POWER_MODE_SLEEP 0x00000002
|
|
#define CYVAL__POWER_MODE_DEEP_SLEEP 0x00000003
|
|
#define CYVAL__POWER_MODE_HIBERNATE 0x00000004
|
|
#define CYFLD__DEBUG_SESSION__OFFSET 0x00000004
|
|
#define CYFLD__DEBUG_SESSION__SIZE 0x00000001
|
|
#define CYVAL__DEBUG_SESSION_NO_SESSION 0x00000000
|
|
#define CYVAL__DEBUG_SESSION_SESSION_ACTIVE 0x00000001
|
|
#define CYFLD__LPM_READY__OFFSET 0x00000005
|
|
#define CYFLD__LPM_READY__SIZE 0x00000001
|
|
#define CYFLD__EXT_VCCD__OFFSET 0x00000017
|
|
#define CYFLD__EXT_VCCD__SIZE 0x00000001
|
|
#define CYFLD__HVMON_ENABLE__OFFSET 0x00000018
|
|
#define CYFLD__HVMON_ENABLE__SIZE 0x00000001
|
|
#define CYFLD__HVMON_RELOAD__OFFSET 0x00000019
|
|
#define CYFLD__HVMON_RELOAD__SIZE 0x00000001
|
|
#define CYFLD__FIMO_DISABLE__OFFSET 0x0000001b
|
|
#define CYFLD__FIMO_DISABLE__SIZE 0x00000001
|
|
#define CYFLD__HIBERNATE_DISABLE__OFFSET 0x0000001c
|
|
#define CYFLD__HIBERNATE_DISABLE__SIZE 0x00000001
|
|
#define CYFLD__LFCLK_SHORT__OFFSET 0x0000001d
|
|
#define CYFLD__LFCLK_SHORT__SIZE 0x00000001
|
|
#define CYFLD__HIBERNATE__OFFSET 0x0000001f
|
|
#define CYFLD__HIBERNATE__SIZE 0x00000001
|
|
#define CYVAL__HIBERNATE_DEEP_SLEEP 0x00000000
|
|
#define CYVAL__HIBERNATE_HIBERNATE 0x00000001
|
|
#define CYREG_PWR_INTR 0x400b0004
|
|
#define CYFLD__LVD__OFFSET 0x00000001
|
|
#define CYFLD__LVD__SIZE 0x00000001
|
|
#define CYREG_PWR_INTR_MASK 0x400b0008
|
|
#define CYREG_PWR_KEY_DELAY 0x400b000c
|
|
#define CYFLD__WAKEUP_HOLDOFF__OFFSET 0x00000000
|
|
#define CYFLD__WAKEUP_HOLDOFF__SIZE 0x0000000a
|
|
#define CYREG_PWR_PWRSYS_CONFIG 0x400b0010
|
|
#define CYFLD__HIB_TEST_EN__OFFSET 0x00000008
|
|
#define CYFLD__HIB_TEST_EN__SIZE 0x00000001
|
|
#define CYFLD__HIB_TEST_REP__OFFSET 0x00000009
|
|
#define CYFLD__HIB_TEST_REP__SIZE 0x00000001
|
|
#define CYREG_PWR_BG_CONFIG 0x400b0014
|
|
#define CYFLD__BG_DFT_EN__OFFSET 0x00000000
|
|
#define CYFLD__BG_DFT_EN__SIZE 0x00000001
|
|
#define CYFLD__BG_DFT_VREF_SEL__OFFSET 0x00000001
|
|
#define CYFLD__BG_DFT_VREF_SEL__SIZE 0x00000004
|
|
#define CYFLD__BG_DFT_CORE_SEL__OFFSET 0x00000005
|
|
#define CYFLD__BG_DFT_CORE_SEL__SIZE 0x00000001
|
|
#define CYFLD__BG_DFT_ICORE_SEL__OFFSET 0x00000006
|
|
#define CYFLD__BG_DFT_ICORE_SEL__SIZE 0x00000002
|
|
#define CYFLD__BG_DFT_VCORE_SEL__OFFSET 0x00000008
|
|
#define CYFLD__BG_DFT_VCORE_SEL__SIZE 0x00000001
|
|
#define CYFLD__VREF_EN__OFFSET 0x00000010
|
|
#define CYFLD__VREF_EN__SIZE 0x00000003
|
|
#define CYREG_PWR_VMON_CONFIG 0x400b0018
|
|
#define CYFLD__LVD_EN__OFFSET 0x00000000
|
|
#define CYFLD__LVD_EN__SIZE 0x00000001
|
|
#define CYFLD__LVD_SEL__OFFSET 0x00000001
|
|
#define CYFLD__LVD_SEL__SIZE 0x00000004
|
|
#define CYFLD__VMON_DDFT_SEL__OFFSET 0x00000005
|
|
#define CYFLD__VMON_DDFT_SEL__SIZE 0x00000003
|
|
#define CYFLD__VMON_ADFT_SEL__OFFSET 0x00000008
|
|
#define CYFLD__VMON_ADFT_SEL__SIZE 0x00000002
|
|
#define CYREG_PWR_DFT_SELECT 0x400b001c
|
|
#define CYFLD__TVMON1_SEL__OFFSET 0x00000000
|
|
#define CYFLD__TVMON1_SEL__SIZE 0x00000003
|
|
#define CYFLD__TVMON2_SEL__OFFSET 0x00000003
|
|
#define CYFLD__TVMON2_SEL__SIZE 0x00000003
|
|
#define CYFLD__BYPASS__OFFSET 0x00000006
|
|
#define CYFLD__BYPASS__SIZE 0x00000001
|
|
#define CYFLD__ACTIVE_EN__OFFSET 0x00000007
|
|
#define CYFLD__ACTIVE_EN__SIZE 0x00000001
|
|
#define CYFLD__ACTIVE_INRUSH_DIS__OFFSET 0x00000008
|
|
#define CYFLD__ACTIVE_INRUSH_DIS__SIZE 0x00000001
|
|
#define CYFLD__LPCOMP_DIS__OFFSET 0x00000009
|
|
#define CYFLD__LPCOMP_DIS__SIZE 0x00000001
|
|
#define CYFLD__BLEED_EN__OFFSET 0x0000000a
|
|
#define CYFLD__BLEED_EN__SIZE 0x00000001
|
|
#define CYFLD__IPOR_EN__OFFSET 0x0000000b
|
|
#define CYFLD__IPOR_EN__SIZE 0x00000001
|
|
#define CYFLD__POWER_UP_RAW_BYP__OFFSET 0x0000000c
|
|
#define CYFLD__POWER_UP_RAW_BYP__SIZE 0x00000001
|
|
#define CYFLD__POWER_UP_RAW_CTL__OFFSET 0x0000000d
|
|
#define CYFLD__POWER_UP_RAW_CTL__SIZE 0x00000001
|
|
#define CYFLD__DEEPSLEEP_EN__OFFSET 0x0000000e
|
|
#define CYFLD__DEEPSLEEP_EN__SIZE 0x00000001
|
|
#define CYFLD__RSVD_BYPASS__OFFSET 0x0000000f
|
|
#define CYFLD__RSVD_BYPASS__SIZE 0x00000001
|
|
#define CYFLD__NWELL_OPEN__OFFSET 0x00000010
|
|
#define CYFLD__NWELL_OPEN__SIZE 0x00000001
|
|
#define CYFLD__HIBERNATE_OPEN__OFFSET 0x00000011
|
|
#define CYFLD__HIBERNATE_OPEN__SIZE 0x00000001
|
|
#define CYFLD__DEEPSLEEP_OPEN__OFFSET 0x00000012
|
|
#define CYFLD__DEEPSLEEP_OPEN__SIZE 0x00000001
|
|
#define CYFLD__QUIET_OPEN__OFFSET 0x00000013
|
|
#define CYFLD__QUIET_OPEN__SIZE 0x00000001
|
|
#define CYFLD__LFCLK_OPEN__OFFSET 0x00000014
|
|
#define CYFLD__LFCLK_OPEN__SIZE 0x00000001
|
|
#define CYFLD__QUIET_EN__OFFSET 0x00000016
|
|
#define CYFLD__QUIET_EN__SIZE 0x00000001
|
|
#define CYFLD__BREF_EN__OFFSET 0x00000017
|
|
#define CYFLD__BREF_EN__SIZE 0x00000001
|
|
#define CYFLD__BREF_OUTEN__OFFSET 0x00000018
|
|
#define CYFLD__BREF_OUTEN__SIZE 0x00000001
|
|
#define CYFLD__BREF_REFSW__OFFSET 0x00000019
|
|
#define CYFLD__BREF_REFSW__SIZE 0x00000001
|
|
#define CYFLD__BREF_TESTMODE__OFFSET 0x0000001a
|
|
#define CYFLD__BREF_TESTMODE__SIZE 0x00000001
|
|
#define CYFLD__NWELL_DIS__OFFSET 0x0000001b
|
|
#define CYFLD__NWELL_DIS__SIZE 0x00000001
|
|
#define CYFLD__HVMON_DFT_OVR__OFFSET 0x0000001c
|
|
#define CYFLD__HVMON_DFT_OVR__SIZE 0x00000001
|
|
#define CYFLD__IMO_REFGEN_DIS__OFFSET 0x0000001d
|
|
#define CYFLD__IMO_REFGEN_DIS__SIZE 0x00000001
|
|
#define CYFLD__POWER_UP_ACTIVE__OFFSET 0x0000001e
|
|
#define CYFLD__POWER_UP_ACTIVE__SIZE 0x00000001
|
|
#define CYFLD__POWER_UP_HIBDPSLP__OFFSET 0x0000001f
|
|
#define CYFLD__POWER_UP_HIBDPSLP__SIZE 0x00000001
|
|
#define CYREG_PWR_DDFT_SELECT 0x400b0020
|
|
#define CYFLD__DDFT1_SEL__OFFSET 0x00000000
|
|
#define CYFLD__DDFT1_SEL__SIZE 0x00000004
|
|
#define CYFLD__DDFT2_SEL__OFFSET 0x00000004
|
|
#define CYFLD__DDFT2_SEL__SIZE 0x00000004
|
|
#define CYREG_PWR_DFT_KEY 0x400b0024
|
|
#define CYFLD__KEY16__OFFSET 0x00000000
|
|
#define CYFLD__KEY16__SIZE 0x00000010
|
|
#define CYFLD__HBOD_OFF_AWAKE__OFFSET 0x00000010
|
|
#define CYFLD__HBOD_OFF_AWAKE__SIZE 0x00000001
|
|
#define CYFLD__BODS_OFF__OFFSET 0x00000011
|
|
#define CYFLD__BODS_OFF__SIZE 0x00000001
|
|
#define CYFLD__DFT_MODE__OFFSET 0x00000012
|
|
#define CYFLD__DFT_MODE__SIZE 0x00000001
|
|
#define CYFLD__IO_DISABLE_BYPASS__OFFSET 0x00000013
|
|
#define CYFLD__IO_DISABLE_BYPASS__SIZE 0x00000001
|
|
#define CYFLD__VMON_PD__OFFSET 0x00000014
|
|
#define CYFLD__VMON_PD__SIZE 0x00000001
|
|
#define CYREG_PWR_BOD_KEY 0x400b0028
|
|
#define CYREG_PWR_STOP 0x400b002c
|
|
#define CYFLD__TOKEN__OFFSET 0x00000000
|
|
#define CYFLD__TOKEN__SIZE 0x00000008
|
|
#define CYFLD__UNLOCK__OFFSET 0x00000008
|
|
#define CYFLD__UNLOCK__SIZE 0x00000008
|
|
#define CYFLD__POLARITY__OFFSET 0x00000010
|
|
#define CYFLD__POLARITY__SIZE 0x00000001
|
|
#define CYFLD__FREEZE__OFFSET 0x00000011
|
|
#define CYFLD__FREEZE__SIZE 0x00000001
|
|
#define CYFLD__STOP__OFFSET 0x0000001f
|
|
#define CYFLD__STOP__SIZE 0x00000001
|
|
#define CYREG_CLK_SELECT 0x400b0100
|
|
#define CYFLD__DIRECT_SEL__OFFSET 0x00000000
|
|
#define CYFLD__DIRECT_SEL__SIZE 0x00000003
|
|
#define CYVAL__DIRECT_SEL_IMO 0x00000000
|
|
#define CYVAL__DIRECT_SEL_EXTCLK 0x00000001
|
|
#define CYVAL__DIRECT_SEL_ECO 0x00000002
|
|
#define CYVAL__DIRECT_SEL_DSI0 0x00000004
|
|
#define CYVAL__DIRECT_SEL_DSI1 0x00000005
|
|
#define CYVAL__DIRECT_SEL_DSI2 0x00000006
|
|
#define CYVAL__DIRECT_SEL_DSI3 0x00000007
|
|
#define CYFLD__DBL_SEL__OFFSET 0x00000003
|
|
#define CYFLD__DBL_SEL__SIZE 0x00000003
|
|
#define CYVAL__DBL_SEL_IMO 0x00000000
|
|
#define CYVAL__DBL_SEL_EXTCLK 0x00000001
|
|
#define CYVAL__DBL_SEL_ECO 0x00000002
|
|
#define CYVAL__DBL_SEL_DSI0 0x00000004
|
|
#define CYVAL__DBL_SEL_DSI1 0x00000005
|
|
#define CYVAL__DBL_SEL_DSI2 0x00000006
|
|
#define CYVAL__DBL_SEL_DSI3 0x00000007
|
|
#define CYFLD__PLL_SEL__OFFSET 0x00000006
|
|
#define CYFLD__PLL_SEL__SIZE 0x00000003
|
|
#define CYVAL__PLL_SEL_IMO 0x00000000
|
|
#define CYVAL__PLL_SEL_EXTCLK 0x00000001
|
|
#define CYVAL__PLL_SEL_ECO 0x00000002
|
|
#define CYVAL__PLL_SEL_DPLL 0x00000003
|
|
#define CYVAL__PLL_SEL_DSI0 0x00000004
|
|
#define CYVAL__PLL_SEL_DSI1 0x00000005
|
|
#define CYVAL__PLL_SEL_DSI2 0x00000006
|
|
#define CYVAL__PLL_SEL_DSI3 0x00000007
|
|
#define CYFLD__DPLLIN_SEL__OFFSET 0x00000009
|
|
#define CYFLD__DPLLIN_SEL__SIZE 0x00000003
|
|
#define CYVAL__DPLLIN_SEL_IMO 0x00000000
|
|
#define CYVAL__DPLLIN_SEL_EXTCLK 0x00000001
|
|
#define CYVAL__DPLLIN_SEL_ECO 0x00000002
|
|
#define CYVAL__DPLLIN_SEL_DSI0 0x00000004
|
|
#define CYVAL__DPLLIN_SEL_DSI1 0x00000005
|
|
#define CYVAL__DPLLIN_SEL_DSI2 0x00000006
|
|
#define CYVAL__DPLLIN_SEL_DSI3 0x00000007
|
|
#define CYFLD__DPLLREF_SEL__OFFSET 0x0000000c
|
|
#define CYFLD__DPLLREF_SEL__SIZE 0x00000002
|
|
#define CYVAL__DPLLREF_SEL_DSI0 0x00000000
|
|
#define CYVAL__DPLLREF_SEL_DSI1 0x00000001
|
|
#define CYVAL__DPLLREF_SEL_DSI2 0x00000002
|
|
#define CYVAL__DPLLREF_SEL_DSI3 0x00000003
|
|
#define CYFLD__WDT_LOCK__OFFSET 0x0000000e
|
|
#define CYFLD__WDT_LOCK__SIZE 0x00000002
|
|
#define CYVAL__WDT_LOCK_NO_CHG 0x00000000
|
|
#define CYVAL__WDT_LOCK_CLR0 0x00000001
|
|
#define CYVAL__WDT_LOCK_CLR1 0x00000002
|
|
#define CYVAL__WDT_LOCK_SET01 0x00000003
|
|
#define CYFLD__HFCLK_SEL__OFFSET 0x00000010
|
|
#define CYFLD__HFCLK_SEL__SIZE 0x00000002
|
|
#define CYVAL__HFCLK_SEL_DIRECT_SEL 0x00000000
|
|
#define CYVAL__HFCLK_SEL_DBL 0x00000001
|
|
#define CYVAL__HFCLK_SEL_PLL 0x00000002
|
|
#define CYFLD__HALF_EN__OFFSET 0x00000012
|
|
#define CYFLD__HALF_EN__SIZE 0x00000001
|
|
#define CYFLD__SYSCLK_DIV__OFFSET 0x00000013
|
|
#define CYFLD__SYSCLK_DIV__SIZE 0x00000003
|
|
#define CYVAL__SYSCLK_DIV_NO_DIV 0x00000000
|
|
#define CYVAL__SYSCLK_DIV_DIV_BY_2 0x00000001
|
|
#define CYVAL__SYSCLK_DIV_DIV_BY_4 0x00000002
|
|
#define CYVAL__SYSCLK_DIV_DIV_BY_8 0x00000003
|
|
#define CYVAL__SYSCLK_DIV_DIV_BY_16 0x00000004
|
|
#define CYVAL__SYSCLK_DIV_DIV_BY_32 0x00000005
|
|
#define CYVAL__SYSCLK_DIV_DIV_BY_64 0x00000006
|
|
#define CYVAL__SYSCLK_DIV_DIV_BY_128 0x00000007
|
|
#define CYREG_CLK_ILO_CONFIG 0x400b0104
|
|
#define CYFLD__PD_MODE__OFFSET 0x00000000
|
|
#define CYFLD__PD_MODE__SIZE 0x00000001
|
|
#define CYVAL__PD_MODE_SLEEP 0x00000000
|
|
#define CYVAL__PD_MODE_COMA 0x00000001
|
|
#define CYFLD__TURBO__OFFSET 0x00000001
|
|
#define CYFLD__TURBO__SIZE 0x00000001
|
|
#define CYFLD__SATBIAS__OFFSET 0x00000002
|
|
#define CYFLD__SATBIAS__SIZE 0x00000001
|
|
#define CYVAL__SATBIAS_SATURATED 0x00000000
|
|
#define CYVAL__SATBIAS_SUBTHRESHOLD 0x00000001
|
|
#define CYFLD__ENABLE__OFFSET 0x0000001f
|
|
#define CYFLD__ENABLE__SIZE 0x00000001
|
|
#define CYREG_CLK_IMO_CONFIG 0x400b0108
|
|
#define CYFLD__FLASHPUMP_SEL__OFFSET 0x00000016
|
|
#define CYFLD__FLASHPUMP_SEL__SIZE 0x00000001
|
|
#define CYVAL__FLASHPUMP_SEL_GND 0x00000000
|
|
#define CYVAL__FLASHPUMP_SEL_CLK36 0x00000001
|
|
#define CYFLD__EN_FASTBIAS__OFFSET 0x00000017
|
|
#define CYFLD__EN_FASTBIAS__SIZE 0x00000001
|
|
#define CYFLD__TEST_FASTBIAS__OFFSET 0x00000018
|
|
#define CYFLD__TEST_FASTBIAS__SIZE 0x00000001
|
|
#define CYFLD__PUMP_SEL__OFFSET 0x00000019
|
|
#define CYFLD__PUMP_SEL__SIZE 0x00000003
|
|
#define CYVAL__PUMP_SEL_GND 0x00000000
|
|
#define CYVAL__PUMP_SEL_IMO 0x00000001
|
|
#define CYVAL__PUMP_SEL_DBL 0x00000002
|
|
#define CYVAL__PUMP_SEL_CLK36 0x00000003
|
|
#define CYVAL__PUMP_SEL_FF1 0x00000004
|
|
#define CYFLD__TEST_USB_MODE__OFFSET 0x0000001c
|
|
#define CYFLD__TEST_USB_MODE__SIZE 0x00000001
|
|
#define CYFLD__EN_CLK36__OFFSET 0x0000001d
|
|
#define CYFLD__EN_CLK36__SIZE 0x00000001
|
|
#define CYFLD__EN_CLK2X__OFFSET 0x0000001e
|
|
#define CYFLD__EN_CLK2X__SIZE 0x00000001
|
|
#define CYREG_CLK_IMO_SPREAD 0x400b010c
|
|
#define CYFLD__SS_VALUE__OFFSET 0x00000000
|
|
#define CYFLD__SS_VALUE__SIZE 0x00000005
|
|
#define CYFLD__SS_MAX__OFFSET 0x00000008
|
|
#define CYFLD__SS_MAX__SIZE 0x00000005
|
|
#define CYFLD__SS_RANGE__OFFSET 0x0000001c
|
|
#define CYFLD__SS_RANGE__SIZE 0x00000002
|
|
#define CYVAL__SS_RANGE_M1 0x00000000
|
|
#define CYVAL__SS_RANGE_M2 0x00000001
|
|
#define CYVAL__SS_RANGE_M4 0x00000002
|
|
#define CYFLD__SS_MODE__OFFSET 0x0000001e
|
|
#define CYFLD__SS_MODE__SIZE 0x00000002
|
|
#define CYVAL__SS_MODE_OFF 0x00000000
|
|
#define CYVAL__SS_MODE_TRIANGLE 0x00000001
|
|
#define CYVAL__SS_MODE_LFSR 0x00000002
|
|
#define CYVAL__SS_MODE_DSI 0x00000003
|
|
#define CYREG_CLK_DFT_SELECT 0x400b0110
|
|
#define CYFLD__DFT_SEL1__OFFSET 0x00000000
|
|
#define CYFLD__DFT_SEL1__SIZE 0x00000004
|
|
#define CYVAL__DFT_SEL1_NC 0x00000000
|
|
#define CYVAL__DFT_SEL1_ILO 0x00000001
|
|
#define CYVAL__DFT_SEL1_WCO 0x00000002
|
|
#define CYVAL__DFT_SEL1_IMO 0x00000003
|
|
#define CYVAL__DFT_SEL1_ECO 0x00000004
|
|
#define CYVAL__DFT_SEL1_PLL 0x00000005
|
|
#define CYVAL__DFT_SEL1_DPLL_OUT 0x00000006
|
|
#define CYVAL__DFT_SEL1_DPLL_REF 0x00000007
|
|
#define CYVAL__DFT_SEL1_DBL 0x00000008
|
|
#define CYVAL__DFT_SEL1_IMO2X 0x00000009
|
|
#define CYVAL__DFT_SEL1_IMO36 0x0000000a
|
|
#define CYVAL__DFT_SEL1_HFCLK 0x0000000b
|
|
#define CYVAL__DFT_SEL1_LFCLK 0x0000000c
|
|
#define CYVAL__DFT_SEL1_SYSCLK 0x0000000d
|
|
#define CYVAL__DFT_SEL1_EXTCLK 0x0000000e
|
|
#define CYVAL__DFT_SEL1_HALFSYSCLK 0x0000000f
|
|
#define CYFLD__DFT_DIV1__OFFSET 0x00000004
|
|
#define CYFLD__DFT_DIV1__SIZE 0x00000002
|
|
#define CYVAL__DFT_DIV1_NO_DIV 0x00000000
|
|
#define CYVAL__DFT_DIV1_DIV_BY_2 0x00000001
|
|
#define CYVAL__DFT_DIV1_DIV_BY_4 0x00000002
|
|
#define CYVAL__DFT_DIV1_DIV_BY_8 0x00000003
|
|
#define CYFLD__DFT_SEL2__OFFSET 0x00000008
|
|
#define CYFLD__DFT_SEL2__SIZE 0x00000004
|
|
#define CYVAL__DFT_SEL2_NC 0x00000000
|
|
#define CYVAL__DFT_SEL2_ILO 0x00000001
|
|
#define CYVAL__DFT_SEL2_WCO 0x00000002
|
|
#define CYVAL__DFT_SEL2_IMO 0x00000003
|
|
#define CYVAL__DFT_SEL2_ECO 0x00000004
|
|
#define CYVAL__DFT_SEL2_PLL 0x00000005
|
|
#define CYVAL__DFT_SEL2_DPLL_OUT 0x00000006
|
|
#define CYVAL__DFT_SEL2_DPLL_REF 0x00000007
|
|
#define CYVAL__DFT_SEL2_DBL 0x00000008
|
|
#define CYVAL__DFT_SEL2_IMO2X 0x00000009
|
|
#define CYVAL__DFT_SEL2_IMO36 0x0000000a
|
|
#define CYVAL__DFT_SEL2_HFCLK 0x0000000b
|
|
#define CYVAL__DFT_SEL2_LFCLK 0x0000000c
|
|
#define CYVAL__DFT_SEL2_SYSCLK 0x0000000d
|
|
#define CYVAL__DFT_SEL2_EXTCLK 0x0000000e
|
|
#define CYVAL__DFT_SEL2_HALFSYSCLK 0x0000000f
|
|
#define CYFLD__DFT_DIV2__OFFSET 0x0000000c
|
|
#define CYFLD__DFT_DIV2__SIZE 0x00000002
|
|
#define CYVAL__DFT_DIV2_NO_DIV 0x00000000
|
|
#define CYVAL__DFT_DIV2_DIV_BY_2 0x00000001
|
|
#define CYVAL__DFT_DIV2_DIV_BY_4 0x00000002
|
|
#define CYVAL__DFT_DIV2_DIV_BY_8 0x00000003
|
|
#define CYREG_WDT_CTRLOW 0x400b0200
|
|
#define CYFLD__WDT_CTR0__OFFSET 0x00000000
|
|
#define CYFLD__WDT_CTR0__SIZE 0x00000010
|
|
#define CYFLD__WDT_CTR1__OFFSET 0x00000010
|
|
#define CYFLD__WDT_CTR1__SIZE 0x00000010
|
|
#define CYREG_WDT_CTRHIGH 0x400b0204
|
|
#define CYFLD__WDT_CTR2__OFFSET 0x00000000
|
|
#define CYFLD__WDT_CTR2__SIZE 0x00000020
|
|
#define CYREG_WDT_MATCH 0x400b0208
|
|
#define CYFLD__WDT_MATCH0__OFFSET 0x00000000
|
|
#define CYFLD__WDT_MATCH0__SIZE 0x00000010
|
|
#define CYFLD__WDT_MATCH1__OFFSET 0x00000010
|
|
#define CYFLD__WDT_MATCH1__SIZE 0x00000010
|
|
#define CYREG_WDT_CONFIG 0x400b020c
|
|
#define CYFLD__WDT_MODE0__OFFSET 0x00000000
|
|
#define CYFLD__WDT_MODE0__SIZE 0x00000002
|
|
#define CYVAL__WDT_MODE0_NOTHING 0x00000000
|
|
#define CYVAL__WDT_MODE0_INT 0x00000001
|
|
#define CYVAL__WDT_MODE0_RESET 0x00000002
|
|
#define CYVAL__WDT_MODE0_INT_THEN_RESET 0x00000003
|
|
#define CYFLD__WDT_CLEAR0__OFFSET 0x00000002
|
|
#define CYFLD__WDT_CLEAR0__SIZE 0x00000001
|
|
#define CYFLD__WDT_CASCADE0_1__OFFSET 0x00000003
|
|
#define CYFLD__WDT_CASCADE0_1__SIZE 0x00000001
|
|
#define CYFLD__WDT_MODE1__OFFSET 0x00000008
|
|
#define CYFLD__WDT_MODE1__SIZE 0x00000002
|
|
#define CYVAL__WDT_MODE1_NOTHING 0x00000000
|
|
#define CYVAL__WDT_MODE1_INT 0x00000001
|
|
#define CYVAL__WDT_MODE1_RESET 0x00000002
|
|
#define CYVAL__WDT_MODE1_INT_THEN_RESET 0x00000003
|
|
#define CYFLD__WDT_CLEAR1__OFFSET 0x0000000a
|
|
#define CYFLD__WDT_CLEAR1__SIZE 0x00000001
|
|
#define CYFLD__WDT_CASCADE1_2__OFFSET 0x0000000b
|
|
#define CYFLD__WDT_CASCADE1_2__SIZE 0x00000001
|
|
#define CYFLD__WDT_MODE2__OFFSET 0x00000010
|
|
#define CYFLD__WDT_MODE2__SIZE 0x00000001
|
|
#define CYVAL__WDT_MODE2_NOTHING 0x00000000
|
|
#define CYVAL__WDT_MODE2_INT 0x00000001
|
|
#define CYFLD__WDT_BITS2__OFFSET 0x00000018
|
|
#define CYFLD__WDT_BITS2__SIZE 0x00000005
|
|
#define CYFLD__LFCLK_SEL__OFFSET 0x0000001e
|
|
#define CYFLD__LFCLK_SEL__SIZE 0x00000002
|
|
#define CYREG_WDT_CONTROL 0x400b0210
|
|
#define CYFLD__WDT_ENABLE0__OFFSET 0x00000000
|
|
#define CYFLD__WDT_ENABLE0__SIZE 0x00000001
|
|
#define CYFLD__WDT_ENABLED0__OFFSET 0x00000001
|
|
#define CYFLD__WDT_ENABLED0__SIZE 0x00000001
|
|
#define CYFLD__WDT_INT0__OFFSET 0x00000002
|
|
#define CYFLD__WDT_INT0__SIZE 0x00000001
|
|
#define CYFLD__WDT_RESET0__OFFSET 0x00000003
|
|
#define CYFLD__WDT_RESET0__SIZE 0x00000001
|
|
#define CYFLD__WDT_ENABLE1__OFFSET 0x00000008
|
|
#define CYFLD__WDT_ENABLE1__SIZE 0x00000001
|
|
#define CYFLD__WDT_ENABLED1__OFFSET 0x00000009
|
|
#define CYFLD__WDT_ENABLED1__SIZE 0x00000001
|
|
#define CYFLD__WDT_INT1__OFFSET 0x0000000a
|
|
#define CYFLD__WDT_INT1__SIZE 0x00000001
|
|
#define CYFLD__WDT_RESET1__OFFSET 0x0000000b
|
|
#define CYFLD__WDT_RESET1__SIZE 0x00000001
|
|
#define CYFLD__WDT_ENABLE2__OFFSET 0x00000010
|
|
#define CYFLD__WDT_ENABLE2__SIZE 0x00000001
|
|
#define CYFLD__WDT_ENABLED2__OFFSET 0x00000011
|
|
#define CYFLD__WDT_ENABLED2__SIZE 0x00000001
|
|
#define CYFLD__WDT_INT2__OFFSET 0x00000012
|
|
#define CYFLD__WDT_INT2__SIZE 0x00000001
|
|
#define CYFLD__WDT_RESET2__OFFSET 0x00000013
|
|
#define CYFLD__WDT_RESET2__SIZE 0x00000001
|
|
#define CYREG_RES_CAUSE 0x400b0300
|
|
#define CYFLD__RESET_WDT__OFFSET 0x00000000
|
|
#define CYFLD__RESET_WDT__SIZE 0x00000001
|
|
#define CYFLD__RESET_DSBOD__OFFSET 0x00000001
|
|
#define CYFLD__RESET_DSBOD__SIZE 0x00000001
|
|
#define CYFLD__RESET_LOCKUP__OFFSET 0x00000002
|
|
#define CYFLD__RESET_LOCKUP__SIZE 0x00000001
|
|
#define CYFLD__RESET_PROT_FAULT__OFFSET 0x00000003
|
|
#define CYFLD__RESET_PROT_FAULT__SIZE 0x00000001
|
|
#define CYFLD__RESET_SOFT__OFFSET 0x00000004
|
|
#define CYFLD__RESET_SOFT__SIZE 0x00000001
|
|
#define CYFLD__RESET_HVBOD__OFFSET 0x00000005
|
|
#define CYFLD__RESET_HVBOD__SIZE 0x00000001
|
|
#define CYFLD__RESET_PBOD__OFFSET 0x00000006
|
|
#define CYFLD__RESET_PBOD__SIZE 0x00000001
|
|
#define CYFLD__RESET_XRES__OFFSET 0x00000007
|
|
#define CYFLD__RESET_XRES__SIZE 0x00000001
|
|
#define CYREG_PWR_PWRSYS_TRIM1 0x400bff00
|
|
#define CYFLD__HIB_BIAS_TRIM__OFFSET 0x00000000
|
|
#define CYFLD__HIB_BIAS_TRIM__SIZE 0x00000003
|
|
#define CYFLD__BOD_TURBO_THRESH__OFFSET 0x00000003
|
|
#define CYFLD__BOD_TURBO_THRESH__SIZE 0x00000001
|
|
#define CYFLD__BOD_TRIM_TRIP__OFFSET 0x00000004
|
|
#define CYFLD__BOD_TRIM_TRIP__SIZE 0x00000004
|
|
#define CYREG_PWR_PWRSYS_TRIM2 0x400bff04
|
|
#define CYFLD__LFCLK_TRIM_LOAD__OFFSET 0x00000000
|
|
#define CYFLD__LFCLK_TRIM_LOAD__SIZE 0x00000002
|
|
#define CYFLD__LFCLK_TRIM_VOLTAGE__OFFSET 0x00000002
|
|
#define CYFLD__LFCLK_TRIM_VOLTAGE__SIZE 0x00000002
|
|
#define CYFLD__DPSLP_TRIM_LOAD__OFFSET 0x00000004
|
|
#define CYFLD__DPSLP_TRIM_LOAD__SIZE 0x00000002
|
|
#define CYFLD__DPSLP_TRIM_LEAKAGE__OFFSET 0x00000006
|
|
#define CYFLD__DPSLP_TRIM_LEAKAGE__SIZE 0x00000001
|
|
#define CYFLD__DPSLP_TRIM_VOLTAGE__OFFSET 0x00000007
|
|
#define CYFLD__DPSLP_TRIM_VOLTAGE__SIZE 0x00000001
|
|
#define CYREG_PWR_PWRSYS_TRIM3 0x400bff08
|
|
#define CYFLD__NWELL_TRIM__OFFSET 0x00000000
|
|
#define CYFLD__NWELL_TRIM__SIZE 0x00000003
|
|
#define CYFLD__QUIET_TRIM__OFFSET 0x00000003
|
|
#define CYFLD__QUIET_TRIM__SIZE 0x00000005
|
|
#define CYREG_PWR_PWRSYS_TRIM4 0x400bff0c
|
|
#define CYFLD__HIB_TRIM_NWELL__OFFSET 0x00000000
|
|
#define CYFLD__HIB_TRIM_NWELL__SIZE 0x00000002
|
|
#define CYFLD__HIB_TRIM_LEAKAGE__OFFSET 0x00000002
|
|
#define CYFLD__HIB_TRIM_LEAKAGE__SIZE 0x00000001
|
|
#define CYFLD__HIB_TRIM_VOLTAGE__OFFSET 0x00000003
|
|
#define CYFLD__HIB_TRIM_VOLTAGE__SIZE 0x00000001
|
|
#define CYFLD__HIB_TRIM_REFERENCE__OFFSET 0x00000004
|
|
#define CYFLD__HIB_TRIM_REFERENCE__SIZE 0x00000002
|
|
#define CYREG_PWR_BG_TRIM1 0x400bff10
|
|
#define CYFLD__INL_TRIM_MAIN__OFFSET 0x00000000
|
|
#define CYFLD__INL_TRIM_MAIN__SIZE 0x00000003
|
|
#define CYFLD__INL_CROSS_MAIN__OFFSET 0x00000003
|
|
#define CYFLD__INL_CROSS_MAIN__SIZE 0x00000004
|
|
#define CYREG_PWR_BG_TRIM2 0x400bff14
|
|
#define CYFLD__VCTAT_SLOPE__OFFSET 0x00000000
|
|
#define CYFLD__VCTAT_SLOPE__SIZE 0x00000004
|
|
#define CYFLD__VCTAT_VOLTAGE__OFFSET 0x00000004
|
|
#define CYFLD__VCTAT_VOLTAGE__SIZE 0x00000002
|
|
#define CYFLD__VCTAT_ENABLE__OFFSET 0x00000006
|
|
#define CYFLD__VCTAT_ENABLE__SIZE 0x00000001
|
|
#define CYFLD__VCTAT_VOLTAGE_MSB__OFFSET 0x00000007
|
|
#define CYFLD__VCTAT_VOLTAGE_MSB__SIZE 0x00000001
|
|
#define CYREG_PWR_BG_TRIM3 0x400bff18
|
|
#define CYFLD__INL_TRIM_IMO__OFFSET 0x00000000
|
|
#define CYFLD__INL_TRIM_IMO__SIZE 0x00000003
|
|
#define CYFLD__INL_CROSS_IMO__OFFSET 0x00000003
|
|
#define CYFLD__INL_CROSS_IMO__SIZE 0x00000004
|
|
#define CYREG_PWR_BG_TRIM4 0x400bff1c
|
|
#define CYFLD__ABS_TRIM_IMO__OFFSET 0x00000000
|
|
#define CYFLD__ABS_TRIM_IMO__SIZE 0x00000006
|
|
#define CYREG_PWR_BG_TRIM5 0x400bff20
|
|
#define CYFLD__TMPCO_TRIM_IMO__OFFSET 0x00000000
|
|
#define CYFLD__TMPCO_TRIM_IMO__SIZE 0x00000006
|
|
#define CYREG_CLK_ILO_TRIM 0x400bff24
|
|
#define CYFLD__TRIM__OFFSET 0x00000000
|
|
#define CYFLD__TRIM__SIZE 0x00000004
|
|
#define CYFLD__COARSE_TRIM__OFFSET 0x00000004
|
|
#define CYFLD__COARSE_TRIM__SIZE 0x00000004
|
|
#define CYREG_CLK_IMO_TRIM1 0x400bff28
|
|
#define CYFLD__OFFSET__OFFSET 0x00000000
|
|
#define CYFLD__OFFSET__SIZE 0x00000008
|
|
#define CYREG_CLK_IMO_TRIM2 0x400bff2c
|
|
#define CYFLD__FREQ__OFFSET 0x00000000
|
|
#define CYFLD__FREQ__SIZE 0x00000006
|
|
#define CYREG_CLK_IMO_TRIM3 0x400bff30
|
|
#define CYFLD__TRIM_CLK36__OFFSET 0x00000000
|
|
#define CYFLD__TRIM_CLK36__SIZE 0x00000004
|
|
#define CYREG_CLK_IMO_TRIM4 0x400bff34
|
|
#define CYFLD__GAIN__OFFSET 0x00000000
|
|
#define CYFLD__GAIN__SIZE 0x00000005
|
|
#define CYFLD__FSOFFSET__OFFSET 0x00000005
|
|
#define CYFLD__FSOFFSET__SIZE 0x00000003
|
|
#define CYREG_PWR_RSVD_TRIM 0x400bff38
|
|
#define CYFLD__RSVD_TRIM__OFFSET 0x00000000
|
|
#define CYFLD__RSVD_TRIM__SIZE 0x00000004
|
|
#define CYDEV_UDB_BASE 0x400f0000
|
|
#define CYDEV_UDB_SIZE 0x00010000
|
|
#define CYDEV_UDB_W8_BASE 0x400f0000
|
|
#define CYDEV_UDB_W8_SIZE 0x00001000
|
|
#define CYREG_UDB_W8_A00 0x400f0000
|
|
#define CYFLD_UDB_W8_A0__OFFSET 0x00000000
|
|
#define CYFLD_UDB_W8_A0__SIZE 0x00000008
|
|
#define CYREG_UDB_W8_A01 0x400f0001
|
|
#define CYREG_UDB_W8_A02 0x400f0002
|
|
#define CYREG_UDB_W8_A03 0x400f0003
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|
#define CYREG_UDB_W8_A10 0x400f0010
|
|
#define CYFLD_UDB_W8_A1__OFFSET 0x00000000
|
|
#define CYFLD_UDB_W8_A1__SIZE 0x00000008
|
|
#define CYREG_UDB_W8_A11 0x400f0011
|
|
#define CYREG_UDB_W8_A12 0x400f0012
|
|
#define CYREG_UDB_W8_A13 0x400f0013
|
|
#define CYREG_UDB_W8_D00 0x400f0020
|
|
#define CYFLD_UDB_W8_D0__OFFSET 0x00000000
|
|
#define CYFLD_UDB_W8_D0__SIZE 0x00000008
|
|
#define CYREG_UDB_W8_D01 0x400f0021
|
|
#define CYREG_UDB_W8_D02 0x400f0022
|
|
#define CYREG_UDB_W8_D03 0x400f0023
|
|
#define CYREG_UDB_W8_D10 0x400f0030
|
|
#define CYFLD_UDB_W8_D1__OFFSET 0x00000000
|
|
#define CYFLD_UDB_W8_D1__SIZE 0x00000008
|
|
#define CYREG_UDB_W8_D11 0x400f0031
|
|
#define CYREG_UDB_W8_D12 0x400f0032
|
|
#define CYREG_UDB_W8_D13 0x400f0033
|
|
#define CYREG_UDB_W8_F00 0x400f0040
|
|
#define CYFLD_UDB_W8_F0__OFFSET 0x00000000
|
|
#define CYFLD_UDB_W8_F0__SIZE 0x00000008
|
|
#define CYREG_UDB_W8_F01 0x400f0041
|
|
#define CYREG_UDB_W8_F02 0x400f0042
|
|
#define CYREG_UDB_W8_F03 0x400f0043
|
|
#define CYREG_UDB_W8_F10 0x400f0050
|
|
#define CYFLD_UDB_W8_F1__OFFSET 0x00000000
|
|
#define CYFLD_UDB_W8_F1__SIZE 0x00000008
|
|
#define CYREG_UDB_W8_F11 0x400f0051
|
|
#define CYREG_UDB_W8_F12 0x400f0052
|
|
#define CYREG_UDB_W8_F13 0x400f0053
|
|
#define CYREG_UDB_W8_ST0 0x400f0060
|
|
#define CYFLD_UDB_W8_ST__OFFSET 0x00000000
|
|
#define CYFLD_UDB_W8_ST__SIZE 0x00000008
|
|
#define CYREG_UDB_W8_ST1 0x400f0061
|
|
#define CYREG_UDB_W8_ST2 0x400f0062
|
|
#define CYREG_UDB_W8_ST3 0x400f0063
|
|
#define CYREG_UDB_W8_CTL0 0x400f0070
|
|
#define CYFLD_UDB_W8_CTL__OFFSET 0x00000000
|
|
#define CYFLD_UDB_W8_CTL__SIZE 0x00000008
|
|
#define CYREG_UDB_W8_CTL1 0x400f0071
|
|
#define CYREG_UDB_W8_CTL2 0x400f0072
|
|
#define CYREG_UDB_W8_CTL3 0x400f0073
|
|
#define CYREG_UDB_W8_MSK0 0x400f0080
|
|
#define CYFLD_UDB_W8_MSK__OFFSET 0x00000000
|
|
#define CYFLD_UDB_W8_MSK__SIZE 0x00000007
|
|
#define CYREG_UDB_W8_MSK1 0x400f0081
|
|
#define CYREG_UDB_W8_MSK2 0x400f0082
|
|
#define CYREG_UDB_W8_MSK3 0x400f0083
|
|
#define CYREG_UDB_W8_ACTL0 0x400f0090
|
|
#define CYFLD_UDB_W8_FIFO0_CLR__OFFSET 0x00000000
|
|
#define CYFLD_UDB_W8_FIFO0_CLR__SIZE 0x00000001
|
|
#define CYVAL_UDB_W8_FIFO0_CLR_NORMAL 0x00000000
|
|
#define CYVAL_UDB_W8_FIFO0_CLR_CLEAR 0x00000001
|
|
#define CYFLD_UDB_W8_FIFO1_CLR__OFFSET 0x00000001
|
|
#define CYFLD_UDB_W8_FIFO1_CLR__SIZE 0x00000001
|
|
#define CYVAL_UDB_W8_FIFO1_CLR_NORMAL 0x00000000
|
|
#define CYVAL_UDB_W8_FIFO1_CLR_CLEAR 0x00000001
|
|
#define CYFLD_UDB_W8_FIFO0_LVL__OFFSET 0x00000002
|
|
#define CYFLD_UDB_W8_FIFO0_LVL__SIZE 0x00000001
|
|
#define CYVAL_UDB_W8_FIFO0_LVL_NORMAL 0x00000000
|
|
#define CYVAL_UDB_W8_FIFO0_LVL_MID 0x00000001
|
|
#define CYFLD_UDB_W8_FIFO1_LVL__OFFSET 0x00000003
|
|
#define CYFLD_UDB_W8_FIFO1_LVL__SIZE 0x00000001
|
|
#define CYVAL_UDB_W8_FIFO1_LVL_NORMAL 0x00000000
|
|
#define CYVAL_UDB_W8_FIFO1_LVL_MID 0x00000001
|
|
#define CYFLD_UDB_W8_INT_EN__OFFSET 0x00000004
|
|
#define CYFLD_UDB_W8_INT_EN__SIZE 0x00000001
|
|
#define CYVAL_UDB_W8_INT_EN_DISABLE 0x00000000
|
|
#define CYVAL_UDB_W8_INT_EN_ENABLE 0x00000001
|
|
#define CYFLD_UDB_W8_CNT_START__OFFSET 0x00000005
|
|
#define CYFLD_UDB_W8_CNT_START__SIZE 0x00000001
|
|
#define CYVAL_UDB_W8_CNT_START_DISABLE 0x00000000
|
|
#define CYVAL_UDB_W8_CNT_START_ENABLE 0x00000001
|
|
#define CYREG_UDB_W8_ACTL1 0x400f0091
|
|
#define CYREG_UDB_W8_ACTL2 0x400f0092
|
|
#define CYREG_UDB_W8_ACTL3 0x400f0093
|
|
#define CYREG_UDB_W8_MC0 0x400f00a0
|
|
#define CYFLD_UDB_W8_PLD0_MC__OFFSET 0x00000000
|
|
#define CYFLD_UDB_W8_PLD0_MC__SIZE 0x00000004
|
|
#define CYFLD_UDB_W8_PLD1_MC__OFFSET 0x00000004
|
|
#define CYFLD_UDB_W8_PLD1_MC__SIZE 0x00000004
|
|
#define CYREG_UDB_W8_MC1 0x400f00a1
|
|
#define CYREG_UDB_W8_MC2 0x400f00a2
|
|
#define CYREG_UDB_W8_MC3 0x400f00a3
|
|
#define CYDEV_UDB_CAT16_BASE 0x400f1000
|
|
#define CYDEV_UDB_CAT16_SIZE 0x00001000
|
|
#define CYREG_UDB_CAT16_A0 0x400f1000
|
|
#define CYFLD_UDB_CAT16_A0__OFFSET 0x00000000
|
|
#define CYFLD_UDB_CAT16_A0__SIZE 0x00000008
|
|
#define CYFLD_UDB_CAT16_A1__OFFSET 0x00000008
|
|
#define CYFLD_UDB_CAT16_A1__SIZE 0x00000008
|
|
#define CYREG_UDB_CAT16_A1 0x400f1002
|
|
#define CYREG_UDB_CAT16_A2 0x400f1004
|
|
#define CYREG_UDB_CAT16_A3 0x400f1006
|
|
#define CYREG_UDB_CAT16_D0 0x400f1040
|
|
#define CYFLD_UDB_CAT16_D0__OFFSET 0x00000000
|
|
#define CYFLD_UDB_CAT16_D0__SIZE 0x00000008
|
|
#define CYFLD_UDB_CAT16_D1__OFFSET 0x00000008
|
|
#define CYFLD_UDB_CAT16_D1__SIZE 0x00000008
|
|
#define CYREG_UDB_CAT16_D1 0x400f1042
|
|
#define CYREG_UDB_CAT16_D2 0x400f1044
|
|
#define CYREG_UDB_CAT16_D3 0x400f1046
|
|
#define CYREG_UDB_CAT16_F0 0x400f1080
|
|
#define CYFLD_UDB_CAT16_F0__OFFSET 0x00000000
|
|
#define CYFLD_UDB_CAT16_F0__SIZE 0x00000008
|
|
#define CYFLD_UDB_CAT16_F1__OFFSET 0x00000008
|
|
#define CYFLD_UDB_CAT16_F1__SIZE 0x00000008
|
|
#define CYREG_UDB_CAT16_F1 0x400f1082
|
|
#define CYREG_UDB_CAT16_F2 0x400f1084
|
|
#define CYREG_UDB_CAT16_F3 0x400f1086
|
|
#define CYREG_UDB_CAT16_CTL_ST0 0x400f10c0
|
|
#define CYFLD_UDB_CAT16_ST__OFFSET 0x00000000
|
|
#define CYFLD_UDB_CAT16_ST__SIZE 0x00000008
|
|
#define CYFLD_UDB_CAT16_CTL__OFFSET 0x00000008
|
|
#define CYFLD_UDB_CAT16_CTL__SIZE 0x00000008
|
|
#define CYREG_UDB_CAT16_CTL_ST1 0x400f10c2
|
|
#define CYREG_UDB_CAT16_CTL_ST2 0x400f10c4
|
|
#define CYREG_UDB_CAT16_CTL_ST3 0x400f10c6
|
|
#define CYREG_UDB_CAT16_ACTL_MSK0 0x400f1100
|
|
#define CYFLD_UDB_CAT16_MSK__OFFSET 0x00000000
|
|
#define CYFLD_UDB_CAT16_MSK__SIZE 0x00000008
|
|
#define CYFLD_UDB_CAT16_FIFO0_CLR__OFFSET 0x00000008
|
|
#define CYFLD_UDB_CAT16_FIFO0_CLR__SIZE 0x00000001
|
|
#define CYVAL_UDB_CAT16_FIFO0_CLR_NORMAL 0x00000000
|
|
#define CYVAL_UDB_CAT16_FIFO0_CLR_CLEAR 0x00000001
|
|
#define CYFLD_UDB_CAT16_FIFO1_CLR__OFFSET 0x00000009
|
|
#define CYFLD_UDB_CAT16_FIFO1_CLR__SIZE 0x00000001
|
|
#define CYVAL_UDB_CAT16_FIFO1_CLR_NORMAL 0x00000000
|
|
#define CYVAL_UDB_CAT16_FIFO1_CLR_CLEAR 0x00000001
|
|
#define CYFLD_UDB_CAT16_FIFO0_LVL__OFFSET 0x0000000a
|
|
#define CYFLD_UDB_CAT16_FIFO0_LVL__SIZE 0x00000001
|
|
#define CYVAL_UDB_CAT16_FIFO0_LVL_NORMAL 0x00000000
|
|
#define CYVAL_UDB_CAT16_FIFO0_LVL_MID 0x00000001
|
|
#define CYFLD_UDB_CAT16_FIFO1_LVL__OFFSET 0x0000000b
|
|
#define CYFLD_UDB_CAT16_FIFO1_LVL__SIZE 0x00000001
|
|
#define CYVAL_UDB_CAT16_FIFO1_LVL_NORMAL 0x00000000
|
|
#define CYVAL_UDB_CAT16_FIFO1_LVL_MID 0x00000001
|
|
#define CYFLD_UDB_CAT16_INT_EN__OFFSET 0x0000000c
|
|
#define CYFLD_UDB_CAT16_INT_EN__SIZE 0x00000001
|
|
#define CYVAL_UDB_CAT16_INT_EN_DISABLE 0x00000000
|
|
#define CYVAL_UDB_CAT16_INT_EN_ENABLE 0x00000001
|
|
#define CYFLD_UDB_CAT16_CNT_START__OFFSET 0x0000000d
|
|
#define CYFLD_UDB_CAT16_CNT_START__SIZE 0x00000001
|
|
#define CYVAL_UDB_CAT16_CNT_START_DISABLE 0x00000000
|
|
#define CYVAL_UDB_CAT16_CNT_START_ENABLE 0x00000001
|
|
#define CYREG_UDB_CAT16_ACTL_MSK1 0x400f1102
|
|
#define CYREG_UDB_CAT16_ACTL_MSK2 0x400f1104
|
|
#define CYREG_UDB_CAT16_ACTL_MSK3 0x400f1106
|
|
#define CYREG_UDB_CAT16_MC0 0x400f1140
|
|
#define CYFLD_UDB_CAT16_PLD0_MC__OFFSET 0x00000000
|
|
#define CYFLD_UDB_CAT16_PLD0_MC__SIZE 0x00000004
|
|
#define CYFLD_UDB_CAT16_PLD1_MC__OFFSET 0x00000004
|
|
#define CYFLD_UDB_CAT16_PLD1_MC__SIZE 0x00000004
|
|
#define CYREG_UDB_CAT16_MC1 0x400f1142
|
|
#define CYREG_UDB_CAT16_MC2 0x400f1144
|
|
#define CYREG_UDB_CAT16_MC3 0x400f1146
|
|
#define CYDEV_UDB_W16_BASE 0x400f1000
|
|
#define CYDEV_UDB_W16_SIZE 0x00001000
|
|
#define CYREG_UDB_W16_A00 0x400f1000
|
|
#define CYFLD_UDB_W16_A0_LS__OFFSET 0x00000000
|
|
#define CYFLD_UDB_W16_A0_LS__SIZE 0x00000008
|
|
#define CYFLD_UDB_W16_A0_MS__OFFSET 0x00000008
|
|
#define CYFLD_UDB_W16_A0_MS__SIZE 0x00000008
|
|
#define CYREG_UDB_W16_A01 0x400f1002
|
|
#define CYREG_UDB_W16_A02 0x400f1004
|
|
#define CYREG_UDB_W16_A10 0x400f1020
|
|
#define CYFLD_UDB_W16_A1_LS__OFFSET 0x00000000
|
|
#define CYFLD_UDB_W16_A1_LS__SIZE 0x00000008
|
|
#define CYFLD_UDB_W16_A1_MS__OFFSET 0x00000008
|
|
#define CYFLD_UDB_W16_A1_MS__SIZE 0x00000008
|
|
#define CYREG_UDB_W16_A11 0x400f1022
|
|
#define CYREG_UDB_W16_A12 0x400f1024
|
|
#define CYREG_UDB_W16_D00 0x400f1040
|
|
#define CYFLD_UDB_W16_D0_LS__OFFSET 0x00000000
|
|
#define CYFLD_UDB_W16_D0_LS__SIZE 0x00000008
|
|
#define CYFLD_UDB_W16_D0_MS__OFFSET 0x00000008
|
|
#define CYFLD_UDB_W16_D0_MS__SIZE 0x00000008
|
|
#define CYREG_UDB_W16_D01 0x400f1042
|
|
#define CYREG_UDB_W16_D02 0x400f1044
|
|
#define CYREG_UDB_W16_D10 0x400f1060
|
|
#define CYFLD_UDB_W16_D1_LS__OFFSET 0x00000000
|
|
#define CYFLD_UDB_W16_D1_LS__SIZE 0x00000008
|
|
#define CYFLD_UDB_W16_D1_MS__OFFSET 0x00000008
|
|
#define CYFLD_UDB_W16_D1_MS__SIZE 0x00000008
|
|
#define CYREG_UDB_W16_D11 0x400f1062
|
|
#define CYREG_UDB_W16_D12 0x400f1064
|
|
#define CYREG_UDB_W16_F00 0x400f1080
|
|
#define CYFLD_UDB_W16_F0_LS__OFFSET 0x00000000
|
|
#define CYFLD_UDB_W16_F0_LS__SIZE 0x00000008
|
|
#define CYFLD_UDB_W16_F0_MS__OFFSET 0x00000008
|
|
#define CYFLD_UDB_W16_F0_MS__SIZE 0x00000008
|
|
#define CYREG_UDB_W16_F01 0x400f1082
|
|
#define CYREG_UDB_W16_F02 0x400f1084
|
|
#define CYREG_UDB_W16_F10 0x400f10a0
|
|
#define CYFLD_UDB_W16_F1_LS__OFFSET 0x00000000
|
|
#define CYFLD_UDB_W16_F1_LS__SIZE 0x00000008
|
|
#define CYFLD_UDB_W16_F1_MS__OFFSET 0x00000008
|
|
#define CYFLD_UDB_W16_F1_MS__SIZE 0x00000008
|
|
#define CYREG_UDB_W16_F11 0x400f10a2
|
|
#define CYREG_UDB_W16_F12 0x400f10a4
|
|
#define CYREG_UDB_W16_ST0 0x400f10c0
|
|
#define CYFLD_UDB_W16_ST_LS__OFFSET 0x00000000
|
|
#define CYFLD_UDB_W16_ST_LS__SIZE 0x00000008
|
|
#define CYFLD_UDB_W16_ST_MS__OFFSET 0x00000008
|
|
#define CYFLD_UDB_W16_ST_MS__SIZE 0x00000008
|
|
#define CYREG_UDB_W16_ST1 0x400f10c2
|
|
#define CYREG_UDB_W16_ST2 0x400f10c4
|
|
#define CYREG_UDB_W16_CTL0 0x400f10e0
|
|
#define CYFLD_UDB_W16_CTL_LS__OFFSET 0x00000000
|
|
#define CYFLD_UDB_W16_CTL_LS__SIZE 0x00000008
|
|
#define CYFLD_UDB_W16_CTL_MS__OFFSET 0x00000008
|
|
#define CYFLD_UDB_W16_CTL_MS__SIZE 0x00000008
|
|
#define CYREG_UDB_W16_CTL1 0x400f10e2
|
|
#define CYREG_UDB_W16_CTL2 0x400f10e4
|
|
#define CYREG_UDB_W16_MSK0 0x400f1100
|
|
#define CYFLD_UDB_W16_MSK_LS__OFFSET 0x00000000
|
|
#define CYFLD_UDB_W16_MSK_LS__SIZE 0x00000007
|
|
#define CYFLD_UDB_W16_MSK_MS__OFFSET 0x00000008
|
|
#define CYFLD_UDB_W16_MSK_MS__SIZE 0x00000007
|
|
#define CYREG_UDB_W16_MSK1 0x400f1102
|
|
#define CYREG_UDB_W16_MSK2 0x400f1104
|
|
#define CYREG_UDB_W16_ACTL0 0x400f1120
|
|
#define CYFLD_UDB_W16_FIFO0_CLR_LS__OFFSET 0x00000000
|
|
#define CYFLD_UDB_W16_FIFO0_CLR_LS__SIZE 0x00000001
|
|
#define CYVAL_UDB_W16_FIFO0_CLR_LS_NORMAL 0x00000000
|
|
#define CYVAL_UDB_W16_FIFO0_CLR_LS_CLEAR 0x00000001
|
|
#define CYFLD_UDB_W16_FIFO1_CLR_LS__OFFSET 0x00000001
|
|
#define CYFLD_UDB_W16_FIFO1_CLR_LS__SIZE 0x00000001
|
|
#define CYVAL_UDB_W16_FIFO1_CLR_LS_NORMAL 0x00000000
|
|
#define CYVAL_UDB_W16_FIFO1_CLR_LS_CLEAR 0x00000001
|
|
#define CYFLD_UDB_W16_FIFO0_LVL_LS__OFFSET 0x00000002
|
|
#define CYFLD_UDB_W16_FIFO0_LVL_LS__SIZE 0x00000001
|
|
#define CYVAL_UDB_W16_FIFO0_LVL_LS_NORMAL 0x00000000
|
|
#define CYVAL_UDB_W16_FIFO0_LVL_LS_MID 0x00000001
|
|
#define CYFLD_UDB_W16_FIFO1_LVL_LS__OFFSET 0x00000003
|
|
#define CYFLD_UDB_W16_FIFO1_LVL_LS__SIZE 0x00000001
|
|
#define CYVAL_UDB_W16_FIFO1_LVL_LS_NORMAL 0x00000000
|
|
#define CYVAL_UDB_W16_FIFO1_LVL_LS_MID 0x00000001
|
|
#define CYFLD_UDB_W16_INT_EN_LS__OFFSET 0x00000004
|
|
#define CYFLD_UDB_W16_INT_EN_LS__SIZE 0x00000001
|
|
#define CYVAL_UDB_W16_INT_EN_LS_DISABLE 0x00000000
|
|
#define CYVAL_UDB_W16_INT_EN_LS_ENABLE 0x00000001
|
|
#define CYFLD_UDB_W16_CNT_START_LS__OFFSET 0x00000005
|
|
#define CYFLD_UDB_W16_CNT_START_LS__SIZE 0x00000001
|
|
#define CYVAL_UDB_W16_CNT_START_LS_DISABLE 0x00000000
|
|
#define CYVAL_UDB_W16_CNT_START_LS_ENABLE 0x00000001
|
|
#define CYFLD_UDB_W16_FIFO0_CLR_MS__OFFSET 0x00000008
|
|
#define CYFLD_UDB_W16_FIFO0_CLR_MS__SIZE 0x00000001
|
|
#define CYVAL_UDB_W16_FIFO0_CLR_MS_NORMAL 0x00000000
|
|
#define CYVAL_UDB_W16_FIFO0_CLR_MS_CLEAR 0x00000001
|
|
#define CYFLD_UDB_W16_FIFO1_CLR_MS__OFFSET 0x00000009
|
|
#define CYFLD_UDB_W16_FIFO1_CLR_MS__SIZE 0x00000001
|
|
#define CYVAL_UDB_W16_FIFO1_CLR_MS_NORMAL 0x00000000
|
|
#define CYVAL_UDB_W16_FIFO1_CLR_MS_CLEAR 0x00000001
|
|
#define CYFLD_UDB_W16_FIFO0_LVL_MS__OFFSET 0x0000000a
|
|
#define CYFLD_UDB_W16_FIFO0_LVL_MS__SIZE 0x00000001
|
|
#define CYVAL_UDB_W16_FIFO0_LVL_MS_NORMAL 0x00000000
|
|
#define CYVAL_UDB_W16_FIFO0_LVL_MS_MID 0x00000001
|
|
#define CYFLD_UDB_W16_FIFO1_LVL_MS__OFFSET 0x0000000b
|
|
#define CYFLD_UDB_W16_FIFO1_LVL_MS__SIZE 0x00000001
|
|
#define CYVAL_UDB_W16_FIFO1_LVL_MS_NORMAL 0x00000000
|
|
#define CYVAL_UDB_W16_FIFO1_LVL_MS_MID 0x00000001
|
|
#define CYFLD_UDB_W16_INT_EN_MS__OFFSET 0x0000000c
|
|
#define CYFLD_UDB_W16_INT_EN_MS__SIZE 0x00000001
|
|
#define CYVAL_UDB_W16_INT_EN_MS_DISABLE 0x00000000
|
|
#define CYVAL_UDB_W16_INT_EN_MS_ENABLE 0x00000001
|
|
#define CYFLD_UDB_W16_CNT_START_MS__OFFSET 0x0000000d
|
|
#define CYFLD_UDB_W16_CNT_START_MS__SIZE 0x00000001
|
|
#define CYVAL_UDB_W16_CNT_START_MS_DISABLE 0x00000000
|
|
#define CYVAL_UDB_W16_CNT_START_MS_ENABLE 0x00000001
|
|
#define CYREG_UDB_W16_ACTL1 0x400f1122
|
|
#define CYREG_UDB_W16_ACTL2 0x400f1124
|
|
#define CYREG_UDB_W16_MC0 0x400f1140
|
|
#define CYFLD_UDB_W16_PLD0_MC_LS__OFFSET 0x00000000
|
|
#define CYFLD_UDB_W16_PLD0_MC_LS__SIZE 0x00000004
|
|
#define CYFLD_UDB_W16_PLD1_MC_LS__OFFSET 0x00000004
|
|
#define CYFLD_UDB_W16_PLD1_MC_LS__SIZE 0x00000004
|
|
#define CYFLD_UDB_W16_PLD0_MC_MS__OFFSET 0x00000008
|
|
#define CYFLD_UDB_W16_PLD0_MC_MS__SIZE 0x00000004
|
|
#define CYFLD_UDB_W16_PLD1_MC_MS__OFFSET 0x0000000c
|
|
#define CYFLD_UDB_W16_PLD1_MC_MS__SIZE 0x00000004
|
|
#define CYREG_UDB_W16_MC1 0x400f1142
|
|
#define CYREG_UDB_W16_MC2 0x400f1144
|
|
#define CYDEV_UDB_W32_BASE 0x400f2000
|
|
#define CYDEV_UDB_W32_SIZE 0x00001000
|
|
#define CYREG_UDB_W32_A0 0x400f2000
|
|
#define CYFLD_UDB_W32_A0_0__OFFSET 0x00000000
|
|
#define CYFLD_UDB_W32_A0_0__SIZE 0x00000008
|
|
#define CYFLD_UDB_W32_A0_1__OFFSET 0x00000008
|
|
#define CYFLD_UDB_W32_A0_1__SIZE 0x00000008
|
|
#define CYFLD_UDB_W32_A0_2__OFFSET 0x00000010
|
|
#define CYFLD_UDB_W32_A0_2__SIZE 0x00000008
|
|
#define CYFLD_UDB_W32_A0_3__OFFSET 0x00000018
|
|
#define CYFLD_UDB_W32_A0_3__SIZE 0x00000008
|
|
#define CYREG_UDB_W32_A1 0x400f2040
|
|
#define CYFLD_UDB_W32_A1_0__OFFSET 0x00000000
|
|
#define CYFLD_UDB_W32_A1_0__SIZE 0x00000008
|
|
#define CYFLD_UDB_W32_A1_1__OFFSET 0x00000008
|
|
#define CYFLD_UDB_W32_A1_1__SIZE 0x00000008
|
|
#define CYFLD_UDB_W32_A1_2__OFFSET 0x00000010
|
|
#define CYFLD_UDB_W32_A1_2__SIZE 0x00000008
|
|
#define CYFLD_UDB_W32_A1_3__OFFSET 0x00000018
|
|
#define CYFLD_UDB_W32_A1_3__SIZE 0x00000008
|
|
#define CYREG_UDB_W32_D0 0x400f2080
|
|
#define CYFLD_UDB_W32_D0_0__OFFSET 0x00000000
|
|
#define CYFLD_UDB_W32_D0_0__SIZE 0x00000008
|
|
#define CYFLD_UDB_W32_D0_1__OFFSET 0x00000008
|
|
#define CYFLD_UDB_W32_D0_1__SIZE 0x00000008
|
|
#define CYFLD_UDB_W32_D0_2__OFFSET 0x00000010
|
|
#define CYFLD_UDB_W32_D0_2__SIZE 0x00000008
|
|
#define CYFLD_UDB_W32_D0_3__OFFSET 0x00000018
|
|
#define CYFLD_UDB_W32_D0_3__SIZE 0x00000008
|
|
#define CYREG_UDB_W32_D1 0x400f20c0
|
|
#define CYFLD_UDB_W32_D1_0__OFFSET 0x00000000
|
|
#define CYFLD_UDB_W32_D1_0__SIZE 0x00000008
|
|
#define CYFLD_UDB_W32_D1_1__OFFSET 0x00000008
|
|
#define CYFLD_UDB_W32_D1_1__SIZE 0x00000008
|
|
#define CYFLD_UDB_W32_D1_2__OFFSET 0x00000010
|
|
#define CYFLD_UDB_W32_D1_2__SIZE 0x00000008
|
|
#define CYFLD_UDB_W32_D1_3__OFFSET 0x00000018
|
|
#define CYFLD_UDB_W32_D1_3__SIZE 0x00000008
|
|
#define CYREG_UDB_W32_F0 0x400f2100
|
|
#define CYFLD_UDB_W32_F0_0__OFFSET 0x00000000
|
|
#define CYFLD_UDB_W32_F0_0__SIZE 0x00000008
|
|
#define CYFLD_UDB_W32_F0_1__OFFSET 0x00000008
|
|
#define CYFLD_UDB_W32_F0_1__SIZE 0x00000008
|
|
#define CYFLD_UDB_W32_F0_2__OFFSET 0x00000010
|
|
#define CYFLD_UDB_W32_F0_2__SIZE 0x00000008
|
|
#define CYFLD_UDB_W32_F0_3__OFFSET 0x00000018
|
|
#define CYFLD_UDB_W32_F0_3__SIZE 0x00000008
|
|
#define CYREG_UDB_W32_F1 0x400f2140
|
|
#define CYFLD_UDB_W32_F1_0__OFFSET 0x00000000
|
|
#define CYFLD_UDB_W32_F1_0__SIZE 0x00000008
|
|
#define CYFLD_UDB_W32_F1_1__OFFSET 0x00000008
|
|
#define CYFLD_UDB_W32_F1_1__SIZE 0x00000008
|
|
#define CYFLD_UDB_W32_F1_2__OFFSET 0x00000010
|
|
#define CYFLD_UDB_W32_F1_2__SIZE 0x00000008
|
|
#define CYFLD_UDB_W32_F1_3__OFFSET 0x00000018
|
|
#define CYFLD_UDB_W32_F1_3__SIZE 0x00000008
|
|
#define CYREG_UDB_W32_ST 0x400f2180
|
|
#define CYFLD_UDB_W32_ST_0__OFFSET 0x00000000
|
|
#define CYFLD_UDB_W32_ST_0__SIZE 0x00000008
|
|
#define CYFLD_UDB_W32_ST_1__OFFSET 0x00000008
|
|
#define CYFLD_UDB_W32_ST_1__SIZE 0x00000008
|
|
#define CYFLD_UDB_W32_ST_2__OFFSET 0x00000010
|
|
#define CYFLD_UDB_W32_ST_2__SIZE 0x00000008
|
|
#define CYFLD_UDB_W32_ST_3__OFFSET 0x00000018
|
|
#define CYFLD_UDB_W32_ST_3__SIZE 0x00000008
|
|
#define CYREG_UDB_W32_CTL 0x400f21c0
|
|
#define CYFLD_UDB_W32_CTL_0__OFFSET 0x00000000
|
|
#define CYFLD_UDB_W32_CTL_0__SIZE 0x00000008
|
|
#define CYFLD_UDB_W32_CTL_1__OFFSET 0x00000008
|
|
#define CYFLD_UDB_W32_CTL_1__SIZE 0x00000008
|
|
#define CYFLD_UDB_W32_CTL_2__OFFSET 0x00000010
|
|
#define CYFLD_UDB_W32_CTL_2__SIZE 0x00000008
|
|
#define CYFLD_UDB_W32_CTL_3__OFFSET 0x00000018
|
|
#define CYFLD_UDB_W32_CTL_3__SIZE 0x00000008
|
|
#define CYREG_UDB_W32_MSK 0x400f2200
|
|
#define CYFLD_UDB_W32_MSK_0__OFFSET 0x00000000
|
|
#define CYFLD_UDB_W32_MSK_0__SIZE 0x00000007
|
|
#define CYFLD_UDB_W32_MSK_1__OFFSET 0x00000008
|
|
#define CYFLD_UDB_W32_MSK_1__SIZE 0x00000007
|
|
#define CYFLD_UDB_W32_MSK_2__OFFSET 0x00000010
|
|
#define CYFLD_UDB_W32_MSK_2__SIZE 0x00000007
|
|
#define CYFLD_UDB_W32_MSK_3__OFFSET 0x00000018
|
|
#define CYFLD_UDB_W32_MSK_3__SIZE 0x00000007
|
|
#define CYREG_UDB_W32_ACTL 0x400f2240
|
|
#define CYFLD_UDB_W32_FIFO0_CLR_0__OFFSET 0x00000000
|
|
#define CYFLD_UDB_W32_FIFO0_CLR_0__SIZE 0x00000001
|
|
#define CYVAL_UDB_W32_FIFO0_CLR_0_NORMAL 0x00000000
|
|
#define CYVAL_UDB_W32_FIFO0_CLR_0_CLEAR 0x00000001
|
|
#define CYFLD_UDB_W32_FIFO1_CLR_0__OFFSET 0x00000001
|
|
#define CYFLD_UDB_W32_FIFO1_CLR_0__SIZE 0x00000001
|
|
#define CYVAL_UDB_W32_FIFO1_CLR_0_NORMAL 0x00000000
|
|
#define CYVAL_UDB_W32_FIFO1_CLR_0_CLEAR 0x00000001
|
|
#define CYFLD_UDB_W32_FIFO0_LVL_0__OFFSET 0x00000002
|
|
#define CYFLD_UDB_W32_FIFO0_LVL_0__SIZE 0x00000001
|
|
#define CYVAL_UDB_W32_FIFO0_LVL_0_NORMAL 0x00000000
|
|
#define CYVAL_UDB_W32_FIFO0_LVL_0_MID 0x00000001
|
|
#define CYFLD_UDB_W32_FIFO1_LVL_0__OFFSET 0x00000003
|
|
#define CYFLD_UDB_W32_FIFO1_LVL_0__SIZE 0x00000001
|
|
#define CYVAL_UDB_W32_FIFO1_LVL_0_NORMAL 0x00000000
|
|
#define CYVAL_UDB_W32_FIFO1_LVL_0_MID 0x00000001
|
|
#define CYFLD_UDB_W32_INT_EN_0__OFFSET 0x00000004
|
|
#define CYFLD_UDB_W32_INT_EN_0__SIZE 0x00000001
|
|
#define CYVAL_UDB_W32_INT_EN_0_DISABLE 0x00000000
|
|
#define CYVAL_UDB_W32_INT_EN_0_ENABLE 0x00000001
|
|
#define CYFLD_UDB_W32_CNT_START_0__OFFSET 0x00000005
|
|
#define CYFLD_UDB_W32_CNT_START_0__SIZE 0x00000001
|
|
#define CYVAL_UDB_W32_CNT_START_0_DISABLE 0x00000000
|
|
#define CYVAL_UDB_W32_CNT_START_0_ENABLE 0x00000001
|
|
#define CYFLD_UDB_W32_FIFO0_CLR_1__OFFSET 0x00000008
|
|
#define CYFLD_UDB_W32_FIFO0_CLR_1__SIZE 0x00000001
|
|
#define CYVAL_UDB_W32_FIFO0_CLR_1_NORMAL 0x00000000
|
|
#define CYVAL_UDB_W32_FIFO0_CLR_1_CLEAR 0x00000001
|
|
#define CYFLD_UDB_W32_FIFO1_CLR_1__OFFSET 0x00000009
|
|
#define CYFLD_UDB_W32_FIFO1_CLR_1__SIZE 0x00000001
|
|
#define CYVAL_UDB_W32_FIFO1_CLR_1_NORMAL 0x00000000
|
|
#define CYVAL_UDB_W32_FIFO1_CLR_1_CLEAR 0x00000001
|
|
#define CYFLD_UDB_W32_FIFO0_LVL_1__OFFSET 0x0000000a
|
|
#define CYFLD_UDB_W32_FIFO0_LVL_1__SIZE 0x00000001
|
|
#define CYVAL_UDB_W32_FIFO0_LVL_1_NORMAL 0x00000000
|
|
#define CYVAL_UDB_W32_FIFO0_LVL_1_MID 0x00000001
|
|
#define CYFLD_UDB_W32_FIFO1_LVL_1__OFFSET 0x0000000b
|
|
#define CYFLD_UDB_W32_FIFO1_LVL_1__SIZE 0x00000001
|
|
#define CYVAL_UDB_W32_FIFO1_LVL_1_NORMAL 0x00000000
|
|
#define CYVAL_UDB_W32_FIFO1_LVL_1_MID 0x00000001
|
|
#define CYFLD_UDB_W32_INT_EN_1__OFFSET 0x0000000c
|
|
#define CYFLD_UDB_W32_INT_EN_1__SIZE 0x00000001
|
|
#define CYVAL_UDB_W32_INT_EN_1_DISABLE 0x00000000
|
|
#define CYVAL_UDB_W32_INT_EN_1_ENABLE 0x00000001
|
|
#define CYFLD_UDB_W32_CNT_START_1__OFFSET 0x0000000d
|
|
#define CYFLD_UDB_W32_CNT_START_1__SIZE 0x00000001
|
|
#define CYVAL_UDB_W32_CNT_START_1_DISABLE 0x00000000
|
|
#define CYVAL_UDB_W32_CNT_START_1_ENABLE 0x00000001
|
|
#define CYFLD_UDB_W32_FIFO0_CLR_2__OFFSET 0x00000010
|
|
#define CYFLD_UDB_W32_FIFO0_CLR_2__SIZE 0x00000001
|
|
#define CYVAL_UDB_W32_FIFO0_CLR_2_NORMAL 0x00000000
|
|
#define CYVAL_UDB_W32_FIFO0_CLR_2_CLEAR 0x00000001
|
|
#define CYFLD_UDB_W32_FIFO1_CLR_2__OFFSET 0x00000011
|
|
#define CYFLD_UDB_W32_FIFO1_CLR_2__SIZE 0x00000001
|
|
#define CYVAL_UDB_W32_FIFO1_CLR_2_NORMAL 0x00000000
|
|
#define CYVAL_UDB_W32_FIFO1_CLR_2_CLEAR 0x00000001
|
|
#define CYFLD_UDB_W32_FIFO0_LVL_2__OFFSET 0x00000012
|
|
#define CYFLD_UDB_W32_FIFO0_LVL_2__SIZE 0x00000001
|
|
#define CYVAL_UDB_W32_FIFO0_LVL_2_NORMAL 0x00000000
|
|
#define CYVAL_UDB_W32_FIFO0_LVL_2_MID 0x00000001
|
|
#define CYFLD_UDB_W32_FIFO1_LVL_2__OFFSET 0x00000013
|
|
#define CYFLD_UDB_W32_FIFO1_LVL_2__SIZE 0x00000001
|
|
#define CYVAL_UDB_W32_FIFO1_LVL_2_NORMAL 0x00000000
|
|
#define CYVAL_UDB_W32_FIFO1_LVL_2_MID 0x00000001
|
|
#define CYFLD_UDB_W32_INT_EN_2__OFFSET 0x00000014
|
|
#define CYFLD_UDB_W32_INT_EN_2__SIZE 0x00000001
|
|
#define CYVAL_UDB_W32_INT_EN_2_DISABLE 0x00000000
|
|
#define CYVAL_UDB_W32_INT_EN_2_ENABLE 0x00000001
|
|
#define CYFLD_UDB_W32_CNT_START_2__OFFSET 0x00000015
|
|
#define CYFLD_UDB_W32_CNT_START_2__SIZE 0x00000001
|
|
#define CYVAL_UDB_W32_CNT_START_2_DISABLE 0x00000000
|
|
#define CYVAL_UDB_W32_CNT_START_2_ENABLE 0x00000001
|
|
#define CYFLD_UDB_W32_FIFO0_CLR_3__OFFSET 0x00000018
|
|
#define CYFLD_UDB_W32_FIFO0_CLR_3__SIZE 0x00000001
|
|
#define CYVAL_UDB_W32_FIFO0_CLR_3_NORMAL 0x00000000
|
|
#define CYVAL_UDB_W32_FIFO0_CLR_3_CLEAR 0x00000001
|
|
#define CYFLD_UDB_W32_FIFO1_CLR_3__OFFSET 0x00000019
|
|
#define CYFLD_UDB_W32_FIFO1_CLR_3__SIZE 0x00000001
|
|
#define CYVAL_UDB_W32_FIFO1_CLR_3_NORMAL 0x00000000
|
|
#define CYVAL_UDB_W32_FIFO1_CLR_3_CLEAR 0x00000001
|
|
#define CYFLD_UDB_W32_FIFO0_LVL_3__OFFSET 0x0000001a
|
|
#define CYFLD_UDB_W32_FIFO0_LVL_3__SIZE 0x00000001
|
|
#define CYVAL_UDB_W32_FIFO0_LVL_3_NORMAL 0x00000000
|
|
#define CYVAL_UDB_W32_FIFO0_LVL_3_MID 0x00000001
|
|
#define CYFLD_UDB_W32_FIFO1_LVL_3__OFFSET 0x0000001b
|
|
#define CYFLD_UDB_W32_FIFO1_LVL_3__SIZE 0x00000001
|
|
#define CYVAL_UDB_W32_FIFO1_LVL_3_NORMAL 0x00000000
|
|
#define CYVAL_UDB_W32_FIFO1_LVL_3_MID 0x00000001
|
|
#define CYFLD_UDB_W32_INT_EN_3__OFFSET 0x0000001c
|
|
#define CYFLD_UDB_W32_INT_EN_3__SIZE 0x00000001
|
|
#define CYVAL_UDB_W32_INT_EN_3_DISABLE 0x00000000
|
|
#define CYVAL_UDB_W32_INT_EN_3_ENABLE 0x00000001
|
|
#define CYFLD_UDB_W32_CNT_START_3__OFFSET 0x0000001d
|
|
#define CYFLD_UDB_W32_CNT_START_3__SIZE 0x00000001
|
|
#define CYVAL_UDB_W32_CNT_START_3_DISABLE 0x00000000
|
|
#define CYVAL_UDB_W32_CNT_START_3_ENABLE 0x00000001
|
|
#define CYREG_UDB_W32_MC 0x400f2280
|
|
#define CYFLD_UDB_W32_PLD0_MC_0__OFFSET 0x00000000
|
|
#define CYFLD_UDB_W32_PLD0_MC_0__SIZE 0x00000004
|
|
#define CYFLD_UDB_W32_PLD1_MC_0__OFFSET 0x00000004
|
|
#define CYFLD_UDB_W32_PLD1_MC_0__SIZE 0x00000004
|
|
#define CYFLD_UDB_W32_PLD0_MC_1__OFFSET 0x00000008
|
|
#define CYFLD_UDB_W32_PLD0_MC_1__SIZE 0x00000004
|
|
#define CYFLD_UDB_W32_PLD1_MC_1__OFFSET 0x0000000c
|
|
#define CYFLD_UDB_W32_PLD1_MC_1__SIZE 0x00000004
|
|
#define CYFLD_UDB_W32_PLD0_MC_2__OFFSET 0x00000010
|
|
#define CYFLD_UDB_W32_PLD0_MC_2__SIZE 0x00000004
|
|
#define CYFLD_UDB_W32_PLD1_MC_2__OFFSET 0x00000014
|
|
#define CYFLD_UDB_W32_PLD1_MC_2__SIZE 0x00000004
|
|
#define CYFLD_UDB_W32_PLD0_MC_3__OFFSET 0x00000018
|
|
#define CYFLD_UDB_W32_PLD0_MC_3__SIZE 0x00000004
|
|
#define CYFLD_UDB_W32_PLD1_MC_3__OFFSET 0x0000001c
|
|
#define CYFLD_UDB_W32_PLD1_MC_3__SIZE 0x00000004
|
|
#define CYDEV_UDB_P0_BASE 0x400f3000
|
|
#define CYDEV_UDB_P0_SIZE 0x00000200
|
|
#define CYDEV_UDB_P0_U0_BASE 0x400f3000
|
|
#define CYDEV_UDB_P0_U0_SIZE 0x00000080
|
|
#define CYREG_UDB_P0_U0_PLD_IT0 0x400f3000
|
|
#define CYFLD_UDB_P_U_PLD0_ITxC_0__OFFSET 0x00000000
|
|
#define CYFLD_UDB_P_U_PLD0_ITxC_0__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD0_ITxC_1__OFFSET 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD0_ITxC_1__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD0_ITxC_2__OFFSET 0x00000002
|
|
#define CYFLD_UDB_P_U_PLD0_ITxC_2__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD0_ITxC_3__OFFSET 0x00000003
|
|
#define CYFLD_UDB_P_U_PLD0_ITxC_3__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD0_ITxC_4__OFFSET 0x00000004
|
|
#define CYFLD_UDB_P_U_PLD0_ITxC_4__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD0_ITxC_5__OFFSET 0x00000005
|
|
#define CYFLD_UDB_P_U_PLD0_ITxC_5__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD0_ITxC_6__OFFSET 0x00000006
|
|
#define CYFLD_UDB_P_U_PLD0_ITxC_6__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD0_ITxC_7__OFFSET 0x00000007
|
|
#define CYFLD_UDB_P_U_PLD0_ITxC_7__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD1_ITxC_0__OFFSET 0x00000008
|
|
#define CYFLD_UDB_P_U_PLD1_ITxC_0__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD1_ITxC_1__OFFSET 0x00000009
|
|
#define CYFLD_UDB_P_U_PLD1_ITxC_1__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD1_ITxC_2__OFFSET 0x0000000a
|
|
#define CYFLD_UDB_P_U_PLD1_ITxC_2__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD1_ITxC_3__OFFSET 0x0000000b
|
|
#define CYFLD_UDB_P_U_PLD1_ITxC_3__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD1_ITxC_4__OFFSET 0x0000000c
|
|
#define CYFLD_UDB_P_U_PLD1_ITxC_4__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD1_ITxC_5__OFFSET 0x0000000d
|
|
#define CYFLD_UDB_P_U_PLD1_ITxC_5__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD1_ITxC_6__OFFSET 0x0000000e
|
|
#define CYFLD_UDB_P_U_PLD1_ITxC_6__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD1_ITxC_7__OFFSET 0x0000000f
|
|
#define CYFLD_UDB_P_U_PLD1_ITxC_7__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD0_ITxT_0__OFFSET 0x00000010
|
|
#define CYFLD_UDB_P_U_PLD0_ITxT_0__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD0_ITxT_1__OFFSET 0x00000011
|
|
#define CYFLD_UDB_P_U_PLD0_ITxT_1__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD0_ITxT_2__OFFSET 0x00000012
|
|
#define CYFLD_UDB_P_U_PLD0_ITxT_2__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD0_ITxT_3__OFFSET 0x00000013
|
|
#define CYFLD_UDB_P_U_PLD0_ITxT_3__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD0_ITxT_4__OFFSET 0x00000014
|
|
#define CYFLD_UDB_P_U_PLD0_ITxT_4__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD0_ITxT_5__OFFSET 0x00000015
|
|
#define CYFLD_UDB_P_U_PLD0_ITxT_5__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD0_ITxT_6__OFFSET 0x00000016
|
|
#define CYFLD_UDB_P_U_PLD0_ITxT_6__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD0_ITxT_7__OFFSET 0x00000017
|
|
#define CYFLD_UDB_P_U_PLD0_ITxT_7__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD1_ITxT_0__OFFSET 0x00000018
|
|
#define CYFLD_UDB_P_U_PLD1_ITxT_0__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD1_ITxT_1__OFFSET 0x00000019
|
|
#define CYFLD_UDB_P_U_PLD1_ITxT_1__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD1_ITxT_2__OFFSET 0x0000001a
|
|
#define CYFLD_UDB_P_U_PLD1_ITxT_2__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD1_ITxT_3__OFFSET 0x0000001b
|
|
#define CYFLD_UDB_P_U_PLD1_ITxT_3__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD1_ITxT_4__OFFSET 0x0000001c
|
|
#define CYFLD_UDB_P_U_PLD1_ITxT_4__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD1_ITxT_5__OFFSET 0x0000001d
|
|
#define CYFLD_UDB_P_U_PLD1_ITxT_5__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD1_ITxT_6__OFFSET 0x0000001e
|
|
#define CYFLD_UDB_P_U_PLD1_ITxT_6__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD1_ITxT_7__OFFSET 0x0000001f
|
|
#define CYFLD_UDB_P_U_PLD1_ITxT_7__SIZE 0x00000001
|
|
#define CYREG_UDB_P0_U0_PLD_IT1 0x400f3004
|
|
#define CYREG_UDB_P0_U0_PLD_IT2 0x400f3008
|
|
#define CYREG_UDB_P0_U0_PLD_IT3 0x400f300c
|
|
#define CYREG_UDB_P0_U0_PLD_IT4 0x400f3010
|
|
#define CYREG_UDB_P0_U0_PLD_IT5 0x400f3014
|
|
#define CYREG_UDB_P0_U0_PLD_IT6 0x400f3018
|
|
#define CYREG_UDB_P0_U0_PLD_IT7 0x400f301c
|
|
#define CYREG_UDB_P0_U0_PLD_IT8 0x400f3020
|
|
#define CYREG_UDB_P0_U0_PLD_IT9 0x400f3024
|
|
#define CYREG_UDB_P0_U0_PLD_IT10 0x400f3028
|
|
#define CYREG_UDB_P0_U0_PLD_IT11 0x400f302c
|
|
#define CYREG_UDB_P0_U0_PLD_ORT0 0x400f3030
|
|
#define CYFLD_UDB_P_U_PLD0_ORT_PTx_0__OFFSET 0x00000000
|
|
#define CYFLD_UDB_P_U_PLD0_ORT_PTx_0__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD0_ORT_PTx_1__OFFSET 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD0_ORT_PTx_1__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD0_ORT_PTx_2__OFFSET 0x00000002
|
|
#define CYFLD_UDB_P_U_PLD0_ORT_PTx_2__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD0_ORT_PTx_3__OFFSET 0x00000003
|
|
#define CYFLD_UDB_P_U_PLD0_ORT_PTx_3__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD0_ORT_PTx_4__OFFSET 0x00000004
|
|
#define CYFLD_UDB_P_U_PLD0_ORT_PTx_4__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD0_ORT_PTx_5__OFFSET 0x00000005
|
|
#define CYFLD_UDB_P_U_PLD0_ORT_PTx_5__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD0_ORT_PTx_6__OFFSET 0x00000006
|
|
#define CYFLD_UDB_P_U_PLD0_ORT_PTx_6__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD0_ORT_PTx_7__OFFSET 0x00000007
|
|
#define CYFLD_UDB_P_U_PLD0_ORT_PTx_7__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD1_ORT_PTx_0__OFFSET 0x00000008
|
|
#define CYFLD_UDB_P_U_PLD1_ORT_PTx_0__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD1_ORT_PTx_1__OFFSET 0x00000009
|
|
#define CYFLD_UDB_P_U_PLD1_ORT_PTx_1__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD1_ORT_PTx_2__OFFSET 0x0000000a
|
|
#define CYFLD_UDB_P_U_PLD1_ORT_PTx_2__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD1_ORT_PTx_3__OFFSET 0x0000000b
|
|
#define CYFLD_UDB_P_U_PLD1_ORT_PTx_3__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD1_ORT_PTx_4__OFFSET 0x0000000c
|
|
#define CYFLD_UDB_P_U_PLD1_ORT_PTx_4__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD1_ORT_PTx_5__OFFSET 0x0000000d
|
|
#define CYFLD_UDB_P_U_PLD1_ORT_PTx_5__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD1_ORT_PTx_6__OFFSET 0x0000000e
|
|
#define CYFLD_UDB_P_U_PLD1_ORT_PTx_6__SIZE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD1_ORT_PTx_7__OFFSET 0x0000000f
|
|
#define CYFLD_UDB_P_U_PLD1_ORT_PTx_7__SIZE 0x00000001
|
|
#define CYREG_UDB_P0_U0_PLD_ORT1 0x400f3032
|
|
#define CYREG_UDB_P0_U0_PLD_ORT2 0x400f3034
|
|
#define CYREG_UDB_P0_U0_PLD_ORT3 0x400f3036
|
|
#define CYREG_UDB_P0_U0_PLD_MC_CFG_CEN_CONST 0x400f3038
|
|
#define CYFLD_UDB_P_U_PLD0_MC0_CEN__OFFSET 0x00000000
|
|
#define CYFLD_UDB_P_U_PLD0_MC0_CEN__SIZE 0x00000001
|
|
#define CYVAL_UDB_P_U_PLD0_MC0_CEN_DISABLE 0x00000000
|
|
#define CYVAL_UDB_P_U_PLD0_MC0_CEN_ENABLE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD0_MC0_DFF_C__OFFSET 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD0_MC0_DFF_C__SIZE 0x00000001
|
|
#define CYVAL_UDB_P_U_PLD0_MC0_DFF_C_NOINV 0x00000000
|
|
#define CYVAL_UDB_P_U_PLD0_MC0_DFF_C_INVERTED 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD0_MC1_CEN__OFFSET 0x00000002
|
|
#define CYFLD_UDB_P_U_PLD0_MC1_CEN__SIZE 0x00000001
|
|
#define CYVAL_UDB_P_U_PLD0_MC1_CEN_DISABLE 0x00000000
|
|
#define CYVAL_UDB_P_U_PLD0_MC1_CEN_ENABLE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD0_MC1_DFF_C__OFFSET 0x00000003
|
|
#define CYFLD_UDB_P_U_PLD0_MC1_DFF_C__SIZE 0x00000001
|
|
#define CYVAL_UDB_P_U_PLD0_MC1_DFF_C_NOINV 0x00000000
|
|
#define CYVAL_UDB_P_U_PLD0_MC1_DFF_C_INVERTED 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD0_MC2_CEN__OFFSET 0x00000004
|
|
#define CYFLD_UDB_P_U_PLD0_MC2_CEN__SIZE 0x00000001
|
|
#define CYVAL_UDB_P_U_PLD0_MC2_CEN_DISABLE 0x00000000
|
|
#define CYVAL_UDB_P_U_PLD0_MC2_CEN_ENABLE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD0_MC2_DFF_C__OFFSET 0x00000005
|
|
#define CYFLD_UDB_P_U_PLD0_MC2_DFF_C__SIZE 0x00000001
|
|
#define CYVAL_UDB_P_U_PLD0_MC2_DFF_C_NOINV 0x00000000
|
|
#define CYVAL_UDB_P_U_PLD0_MC2_DFF_C_INVERTED 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD0_MC3_CEN__OFFSET 0x00000006
|
|
#define CYFLD_UDB_P_U_PLD0_MC3_CEN__SIZE 0x00000001
|
|
#define CYVAL_UDB_P_U_PLD0_MC3_CEN_DISABLE 0x00000000
|
|
#define CYVAL_UDB_P_U_PLD0_MC3_CEN_ENABLE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD0_MC3_DFF_C__OFFSET 0x00000007
|
|
#define CYFLD_UDB_P_U_PLD0_MC3_DFF_C__SIZE 0x00000001
|
|
#define CYVAL_UDB_P_U_PLD0_MC3_DFF_C_NOINV 0x00000000
|
|
#define CYVAL_UDB_P_U_PLD0_MC3_DFF_C_INVERTED 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD1_MC0_CEN__OFFSET 0x00000008
|
|
#define CYFLD_UDB_P_U_PLD1_MC0_CEN__SIZE 0x00000001
|
|
#define CYVAL_UDB_P_U_PLD1_MC0_CEN_DISABLE 0x00000000
|
|
#define CYVAL_UDB_P_U_PLD1_MC0_CEN_ENABLE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD1_MC0_DFF_C__OFFSET 0x00000009
|
|
#define CYFLD_UDB_P_U_PLD1_MC0_DFF_C__SIZE 0x00000001
|
|
#define CYVAL_UDB_P_U_PLD1_MC0_DFF_C_NOINV 0x00000000
|
|
#define CYVAL_UDB_P_U_PLD1_MC0_DFF_C_INVERTED 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD1_MC1_CEN__OFFSET 0x0000000a
|
|
#define CYFLD_UDB_P_U_PLD1_MC1_CEN__SIZE 0x00000001
|
|
#define CYVAL_UDB_P_U_PLD1_MC1_CEN_DISABLE 0x00000000
|
|
#define CYVAL_UDB_P_U_PLD1_MC1_CEN_ENABLE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD1_MC1_DFF_C__OFFSET 0x0000000b
|
|
#define CYFLD_UDB_P_U_PLD1_MC1_DFF_C__SIZE 0x00000001
|
|
#define CYVAL_UDB_P_U_PLD1_MC1_DFF_C_NOINV 0x00000000
|
|
#define CYVAL_UDB_P_U_PLD1_MC1_DFF_C_INVERTED 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD1_MC2_CEN__OFFSET 0x0000000c
|
|
#define CYFLD_UDB_P_U_PLD1_MC2_CEN__SIZE 0x00000001
|
|
#define CYVAL_UDB_P_U_PLD1_MC2_CEN_DISABLE 0x00000000
|
|
#define CYVAL_UDB_P_U_PLD1_MC2_CEN_ENABLE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD1_MC2_DFF_C__OFFSET 0x0000000d
|
|
#define CYFLD_UDB_P_U_PLD1_MC2_DFF_C__SIZE 0x00000001
|
|
#define CYVAL_UDB_P_U_PLD1_MC2_DFF_C_NOINV 0x00000000
|
|
#define CYVAL_UDB_P_U_PLD1_MC2_DFF_C_INVERTED 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD1_MC3_CEN__OFFSET 0x0000000e
|
|
#define CYFLD_UDB_P_U_PLD1_MC3_CEN__SIZE 0x00000001
|
|
#define CYVAL_UDB_P_U_PLD1_MC3_CEN_DISABLE 0x00000000
|
|
#define CYVAL_UDB_P_U_PLD1_MC3_CEN_ENABLE 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD1_MC3_DFF_C__OFFSET 0x0000000f
|
|
#define CYFLD_UDB_P_U_PLD1_MC3_DFF_C__SIZE 0x00000001
|
|
#define CYVAL_UDB_P_U_PLD1_MC3_DFF_C_NOINV 0x00000000
|
|
#define CYVAL_UDB_P_U_PLD1_MC3_DFF_C_INVERTED 0x00000001
|
|
#define CYREG_UDB_P0_U0_PLD_MC_CFG_XORFB 0x400f303a
|
|
#define CYFLD_UDB_P_U_PLD0_MC0_XORFB__OFFSET 0x00000000
|
|
#define CYFLD_UDB_P_U_PLD0_MC0_XORFB__SIZE 0x00000002
|
|
#define CYVAL_UDB_P_U_PLD0_MC0_XORFB_DFF 0x00000000
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#define CYVAL_UDB_P_U_PLD0_MC0_XORFB_CARRY 0x00000001
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#define CYVAL_UDB_P_U_PLD0_MC0_XORFB_TFF_H 0x00000002
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#define CYVAL_UDB_P_U_PLD0_MC0_XORFB_TFF_L 0x00000003
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#define CYFLD_UDB_P_U_PLD0_MC1_XORFB__OFFSET 0x00000002
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#define CYFLD_UDB_P_U_PLD0_MC1_XORFB__SIZE 0x00000002
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#define CYVAL_UDB_P_U_PLD0_MC1_XORFB_DFF 0x00000000
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#define CYVAL_UDB_P_U_PLD0_MC1_XORFB_CARRY 0x00000001
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#define CYVAL_UDB_P_U_PLD0_MC1_XORFB_TFF_H 0x00000002
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#define CYVAL_UDB_P_U_PLD0_MC1_XORFB_TFF_L 0x00000003
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#define CYFLD_UDB_P_U_PLD0_MC2_XORFB__OFFSET 0x00000004
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#define CYFLD_UDB_P_U_PLD0_MC2_XORFB__SIZE 0x00000002
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#define CYVAL_UDB_P_U_PLD0_MC2_XORFB_DFF 0x00000000
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#define CYVAL_UDB_P_U_PLD0_MC2_XORFB_CARRY 0x00000001
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#define CYVAL_UDB_P_U_PLD0_MC2_XORFB_TFF_H 0x00000002
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#define CYVAL_UDB_P_U_PLD0_MC2_XORFB_TFF_L 0x00000003
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#define CYFLD_UDB_P_U_PLD0_MC3_XORFB__OFFSET 0x00000006
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#define CYFLD_UDB_P_U_PLD0_MC3_XORFB__SIZE 0x00000002
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#define CYVAL_UDB_P_U_PLD0_MC3_XORFB_DFF 0x00000000
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#define CYVAL_UDB_P_U_PLD0_MC3_XORFB_CARRY 0x00000001
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#define CYVAL_UDB_P_U_PLD0_MC3_XORFB_TFF_H 0x00000002
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#define CYVAL_UDB_P_U_PLD0_MC3_XORFB_TFF_L 0x00000003
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#define CYFLD_UDB_P_U_PLD1_MC0_XORFB__OFFSET 0x00000008
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#define CYFLD_UDB_P_U_PLD1_MC0_XORFB__SIZE 0x00000002
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#define CYVAL_UDB_P_U_PLD1_MC0_XORFB_DFF 0x00000000
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#define CYVAL_UDB_P_U_PLD1_MC0_XORFB_CARRY 0x00000001
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#define CYVAL_UDB_P_U_PLD1_MC0_XORFB_TFF_H 0x00000002
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#define CYVAL_UDB_P_U_PLD1_MC0_XORFB_TFF_L 0x00000003
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#define CYFLD_UDB_P_U_PLD1_MC1_XORFB__OFFSET 0x0000000a
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#define CYFLD_UDB_P_U_PLD1_MC1_XORFB__SIZE 0x00000002
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#define CYVAL_UDB_P_U_PLD1_MC1_XORFB_DFF 0x00000000
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#define CYVAL_UDB_P_U_PLD1_MC1_XORFB_CARRY 0x00000001
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#define CYVAL_UDB_P_U_PLD1_MC1_XORFB_TFF_H 0x00000002
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#define CYVAL_UDB_P_U_PLD1_MC1_XORFB_TFF_L 0x00000003
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#define CYFLD_UDB_P_U_PLD1_MC2_XORFB__OFFSET 0x0000000c
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#define CYFLD_UDB_P_U_PLD1_MC2_XORFB__SIZE 0x00000002
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#define CYVAL_UDB_P_U_PLD1_MC2_XORFB_DFF 0x00000000
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#define CYVAL_UDB_P_U_PLD1_MC2_XORFB_CARRY 0x00000001
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#define CYVAL_UDB_P_U_PLD1_MC2_XORFB_TFF_H 0x00000002
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#define CYVAL_UDB_P_U_PLD1_MC2_XORFB_TFF_L 0x00000003
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#define CYFLD_UDB_P_U_PLD1_MC3_XORFB__OFFSET 0x0000000e
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#define CYFLD_UDB_P_U_PLD1_MC3_XORFB__SIZE 0x00000002
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#define CYVAL_UDB_P_U_PLD1_MC3_XORFB_DFF 0x00000000
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#define CYVAL_UDB_P_U_PLD1_MC3_XORFB_CARRY 0x00000001
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#define CYVAL_UDB_P_U_PLD1_MC3_XORFB_TFF_H 0x00000002
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#define CYVAL_UDB_P_U_PLD1_MC3_XORFB_TFF_L 0x00000003
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#define CYREG_UDB_P0_U0_PLD_MC_SET_RESET 0x400f303c
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#define CYFLD_UDB_P_U_PLD0_MC0_SET_SEL__OFFSET 0x00000000
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#define CYFLD_UDB_P_U_PLD0_MC0_SET_SEL__SIZE 0x00000001
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#define CYVAL_UDB_P_U_PLD0_MC0_SET_SEL_DISABLE 0x00000000
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#define CYVAL_UDB_P_U_PLD0_MC0_SET_SEL_ENABLE 0x00000001
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#define CYFLD_UDB_P_U_PLD0_MC0_RESET_SEL__OFFSET 0x00000001
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#define CYFLD_UDB_P_U_PLD0_MC0_RESET_SEL__SIZE 0x00000001
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#define CYVAL_UDB_P_U_PLD0_MC0_RESET_SEL_DISABLE 0x00000000
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#define CYVAL_UDB_P_U_PLD0_MC0_RESET_SEL_ENABLE 0x00000001
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#define CYFLD_UDB_P_U_PLD0_MC1_SET_SEL__OFFSET 0x00000002
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#define CYFLD_UDB_P_U_PLD0_MC1_SET_SEL__SIZE 0x00000001
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#define CYVAL_UDB_P_U_PLD0_MC1_SET_SEL_DISABLE 0x00000000
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#define CYVAL_UDB_P_U_PLD0_MC1_SET_SEL_ENABLE 0x00000001
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#define CYFLD_UDB_P_U_PLD0_MC1_RESET_SEL__OFFSET 0x00000003
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#define CYFLD_UDB_P_U_PLD0_MC1_RESET_SEL__SIZE 0x00000001
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#define CYVAL_UDB_P_U_PLD0_MC1_RESET_SEL_DISABLE 0x00000000
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#define CYVAL_UDB_P_U_PLD0_MC1_RESET_SEL_ENABLE 0x00000001
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#define CYFLD_UDB_P_U_PLD0_MC2_SET_SEL__OFFSET 0x00000004
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#define CYFLD_UDB_P_U_PLD0_MC2_SET_SEL__SIZE 0x00000001
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#define CYVAL_UDB_P_U_PLD0_MC2_SET_SEL_DISABLE 0x00000000
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#define CYVAL_UDB_P_U_PLD0_MC2_SET_SEL_ENABLE 0x00000001
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#define CYFLD_UDB_P_U_PLD0_MC2_RESET_SEL__OFFSET 0x00000005
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#define CYFLD_UDB_P_U_PLD0_MC2_RESET_SEL__SIZE 0x00000001
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#define CYVAL_UDB_P_U_PLD0_MC2_RESET_SEL_DISABLE 0x00000000
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#define CYVAL_UDB_P_U_PLD0_MC2_RESET_SEL_ENABLE 0x00000001
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#define CYFLD_UDB_P_U_PLD0_MC3_SET_SEL__OFFSET 0x00000006
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#define CYFLD_UDB_P_U_PLD0_MC3_SET_SEL__SIZE 0x00000001
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#define CYVAL_UDB_P_U_PLD0_MC3_SET_SEL_DISABLE 0x00000000
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#define CYVAL_UDB_P_U_PLD0_MC3_SET_SEL_ENABLE 0x00000001
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#define CYFLD_UDB_P_U_PLD0_MC3_RESET_SEL__OFFSET 0x00000007
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#define CYFLD_UDB_P_U_PLD0_MC3_RESET_SEL__SIZE 0x00000001
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#define CYVAL_UDB_P_U_PLD0_MC3_RESET_SEL_DISABLE 0x00000000
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#define CYVAL_UDB_P_U_PLD0_MC3_RESET_SEL_ENABLE 0x00000001
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#define CYFLD_UDB_P_U_PLD1_MC0_SET_SEL__OFFSET 0x00000008
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#define CYFLD_UDB_P_U_PLD1_MC0_SET_SEL__SIZE 0x00000001
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#define CYVAL_UDB_P_U_PLD1_MC0_SET_SEL_DISABLE 0x00000000
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#define CYVAL_UDB_P_U_PLD1_MC0_SET_SEL_ENABLE 0x00000001
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#define CYFLD_UDB_P_U_PLD1_MC0_RESET_SEL__OFFSET 0x00000009
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#define CYFLD_UDB_P_U_PLD1_MC0_RESET_SEL__SIZE 0x00000001
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#define CYVAL_UDB_P_U_PLD1_MC0_RESET_SEL_DISABLE 0x00000000
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#define CYVAL_UDB_P_U_PLD1_MC0_RESET_SEL_ENABLE 0x00000001
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#define CYFLD_UDB_P_U_PLD1_MC1_SET_SEL__OFFSET 0x0000000a
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#define CYFLD_UDB_P_U_PLD1_MC1_SET_SEL__SIZE 0x00000001
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#define CYVAL_UDB_P_U_PLD1_MC1_SET_SEL_DISABLE 0x00000000
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#define CYVAL_UDB_P_U_PLD1_MC1_SET_SEL_ENABLE 0x00000001
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#define CYFLD_UDB_P_U_PLD1_MC1_RESET_SEL__OFFSET 0x0000000b
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#define CYFLD_UDB_P_U_PLD1_MC1_RESET_SEL__SIZE 0x00000001
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#define CYVAL_UDB_P_U_PLD1_MC1_RESET_SEL_DISABLE 0x00000000
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#define CYVAL_UDB_P_U_PLD1_MC1_RESET_SEL_ENABLE 0x00000001
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#define CYFLD_UDB_P_U_PLD1_MC2_SET_SEL__OFFSET 0x0000000c
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#define CYFLD_UDB_P_U_PLD1_MC2_SET_SEL__SIZE 0x00000001
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#define CYVAL_UDB_P_U_PLD1_MC2_SET_SEL_DISABLE 0x00000000
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#define CYVAL_UDB_P_U_PLD1_MC2_SET_SEL_ENABLE 0x00000001
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#define CYFLD_UDB_P_U_PLD1_MC2_RESET_SEL__OFFSET 0x0000000d
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#define CYFLD_UDB_P_U_PLD1_MC2_RESET_SEL__SIZE 0x00000001
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#define CYVAL_UDB_P_U_PLD1_MC2_RESET_SEL_DISABLE 0x00000000
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#define CYVAL_UDB_P_U_PLD1_MC2_RESET_SEL_ENABLE 0x00000001
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#define CYFLD_UDB_P_U_PLD1_MC3_SET_SEL__OFFSET 0x0000000e
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#define CYFLD_UDB_P_U_PLD1_MC3_SET_SEL__SIZE 0x00000001
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#define CYVAL_UDB_P_U_PLD1_MC3_SET_SEL_DISABLE 0x00000000
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#define CYVAL_UDB_P_U_PLD1_MC3_SET_SEL_ENABLE 0x00000001
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#define CYFLD_UDB_P_U_PLD1_MC3_RESET_SEL__OFFSET 0x0000000f
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#define CYFLD_UDB_P_U_PLD1_MC3_RESET_SEL__SIZE 0x00000001
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#define CYVAL_UDB_P_U_PLD1_MC3_RESET_SEL_DISABLE 0x00000000
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#define CYVAL_UDB_P_U_PLD1_MC3_RESET_SEL_ENABLE 0x00000001
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#define CYREG_UDB_P0_U0_PLD_MC_CFG_BYPASS 0x400f303e
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#define CYFLD_UDB_P_U_PLD0_MC0_BYPASS__OFFSET 0x00000000
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#define CYFLD_UDB_P_U_PLD0_MC0_BYPASS__SIZE 0x00000001
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#define CYVAL_UDB_P_U_PLD0_MC0_BYPASS_REGISTER 0x00000000
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#define CYVAL_UDB_P_U_PLD0_MC0_BYPASS_COMBINATIONAL 0x00000001
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#define CYFLD_UDB_P_U_NC1__OFFSET 0x00000001
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#define CYFLD_UDB_P_U_NC1__SIZE 0x00000001
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#define CYFLD_UDB_P_U_PLD0_MC1_BYPASS__OFFSET 0x00000002
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#define CYFLD_UDB_P_U_PLD0_MC1_BYPASS__SIZE 0x00000001
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#define CYVAL_UDB_P_U_PLD0_MC1_BYPASS_REGISTER 0x00000000
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#define CYVAL_UDB_P_U_PLD0_MC1_BYPASS_COMBINATIONAL 0x00000001
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#define CYFLD_UDB_P_U_NC3__OFFSET 0x00000003
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#define CYFLD_UDB_P_U_NC3__SIZE 0x00000001
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#define CYFLD_UDB_P_U_PLD0_MC2_BYPASS__OFFSET 0x00000004
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#define CYFLD_UDB_P_U_PLD0_MC2_BYPASS__SIZE 0x00000001
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#define CYVAL_UDB_P_U_PLD0_MC2_BYPASS_REGISTER 0x00000000
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#define CYVAL_UDB_P_U_PLD0_MC2_BYPASS_COMBINATIONAL 0x00000001
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#define CYFLD_UDB_P_U_NC5__OFFSET 0x00000005
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#define CYFLD_UDB_P_U_NC5__SIZE 0x00000001
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#define CYFLD_UDB_P_U_PLD0_MC3_BYPASS__OFFSET 0x00000006
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#define CYFLD_UDB_P_U_PLD0_MC3_BYPASS__SIZE 0x00000001
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#define CYVAL_UDB_P_U_PLD0_MC3_BYPASS_REGISTER 0x00000000
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#define CYVAL_UDB_P_U_PLD0_MC3_BYPASS_COMBINATIONAL 0x00000001
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#define CYFLD_UDB_P_U_NC7__OFFSET 0x00000007
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#define CYFLD_UDB_P_U_NC7__SIZE 0x00000001
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#define CYFLD_UDB_P_U_PLD1_MC0_BYPASS__OFFSET 0x00000008
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#define CYFLD_UDB_P_U_PLD1_MC0_BYPASS__SIZE 0x00000001
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#define CYVAL_UDB_P_U_PLD1_MC0_BYPASS_REGISTER 0x00000000
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#define CYVAL_UDB_P_U_PLD1_MC0_BYPASS_COMBINATIONAL 0x00000001
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#define CYFLD_UDB_P_U_NC9__OFFSET 0x00000009
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#define CYFLD_UDB_P_U_NC9__SIZE 0x00000001
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#define CYFLD_UDB_P_U_PLD1_MC1_BYPASS__OFFSET 0x0000000a
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#define CYFLD_UDB_P_U_PLD1_MC1_BYPASS__SIZE 0x00000001
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#define CYVAL_UDB_P_U_PLD1_MC1_BYPASS_REGISTER 0x00000000
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#define CYVAL_UDB_P_U_PLD1_MC1_BYPASS_COMBINATIONAL 0x00000001
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#define CYFLD_UDB_P_U_NC11__OFFSET 0x0000000b
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#define CYFLD_UDB_P_U_NC11__SIZE 0x00000001
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#define CYFLD_UDB_P_U_PLD1_MC2_BYPASS__OFFSET 0x0000000c
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#define CYFLD_UDB_P_U_PLD1_MC2_BYPASS__SIZE 0x00000001
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#define CYVAL_UDB_P_U_PLD1_MC2_BYPASS_REGISTER 0x00000000
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#define CYVAL_UDB_P_U_PLD1_MC2_BYPASS_COMBINATIONAL 0x00000001
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#define CYFLD_UDB_P_U_NC13__OFFSET 0x0000000d
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#define CYFLD_UDB_P_U_NC13__SIZE 0x00000001
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#define CYFLD_UDB_P_U_PLD1_MC3_BYPASS__OFFSET 0x0000000e
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#define CYFLD_UDB_P_U_PLD1_MC3_BYPASS__SIZE 0x00000001
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#define CYVAL_UDB_P_U_PLD1_MC3_BYPASS_REGISTER 0x00000000
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#define CYVAL_UDB_P_U_PLD1_MC3_BYPASS_COMBINATIONAL 0x00000001
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#define CYFLD_UDB_P_U_NC15__OFFSET 0x0000000f
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#define CYFLD_UDB_P_U_NC15__SIZE 0x00000001
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#define CYREG_UDB_P0_U0_CFG0 0x400f3040
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#define CYFLD_UDB_P_U_RAD0__OFFSET 0x00000000
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#define CYFLD_UDB_P_U_RAD0__SIZE 0x00000003
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#define CYVAL_UDB_P_U_RAD0_OFF 0x00000000
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#define CYVAL_UDB_P_U_RAD0_DP_IN0 0x00000001
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#define CYVAL_UDB_P_U_RAD0_DP_IN1 0x00000002
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#define CYVAL_UDB_P_U_RAD0_DP_IN2 0x00000003
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#define CYVAL_UDB_P_U_RAD0_DP_IN3 0x00000004
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#define CYVAL_UDB_P_U_RAD0_DP_IN4 0x00000005
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#define CYVAL_UDB_P_U_RAD0_DP_IN5 0x00000006
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#define CYVAL_UDB_P_U_RAD0_RESERVED 0x00000007
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#define CYFLD_UDB_P_U_RAD1__OFFSET 0x00000004
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#define CYFLD_UDB_P_U_RAD1__SIZE 0x00000003
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#define CYVAL_UDB_P_U_RAD1_OFF 0x00000000
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#define CYVAL_UDB_P_U_RAD1_DP_IN0 0x00000001
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#define CYVAL_UDB_P_U_RAD1_DP_IN1 0x00000002
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#define CYVAL_UDB_P_U_RAD1_DP_IN2 0x00000003
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#define CYVAL_UDB_P_U_RAD1_DP_IN3 0x00000004
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#define CYVAL_UDB_P_U_RAD1_DP_IN4 0x00000005
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#define CYVAL_UDB_P_U_RAD1_DP_IN5 0x00000006
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#define CYVAL_UDB_P_U_RAD1_RESERVED 0x00000007
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#define CYREG_UDB_P0_U0_CFG1 0x400f3041
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#define CYFLD_UDB_P_U_RAD2__OFFSET 0x00000000
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#define CYFLD_UDB_P_U_RAD2__SIZE 0x00000003
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#define CYVAL_UDB_P_U_RAD2_OFF 0x00000000
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#define CYVAL_UDB_P_U_RAD2_DP_IN0 0x00000001
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#define CYVAL_UDB_P_U_RAD2_DP_IN1 0x00000002
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#define CYVAL_UDB_P_U_RAD2_DP_IN2 0x00000003
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#define CYVAL_UDB_P_U_RAD2_DP_IN3 0x00000004
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#define CYVAL_UDB_P_U_RAD2_DP_IN4 0x00000005
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#define CYVAL_UDB_P_U_RAD2_DP_IN5 0x00000006
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#define CYVAL_UDB_P_U_RAD2_RESERVED 0x00000007
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#define CYFLD_UDB_P_U_DP_RTE_BYPASS0__OFFSET 0x00000003
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#define CYFLD_UDB_P_U_DP_RTE_BYPASS0__SIZE 0x00000001
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#define CYVAL_UDB_P_U_DP_RTE_BYPASS0_DP_IN0_ROUTE 0x00000000
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#define CYVAL_UDB_P_U_DP_RTE_BYPASS0_DP_IN0_BYPASS 0x00000001
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#define CYFLD_UDB_P_U_DP_RTE_BYPASS1__OFFSET 0x00000004
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#define CYFLD_UDB_P_U_DP_RTE_BYPASS1__SIZE 0x00000001
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#define CYVAL_UDB_P_U_DP_RTE_BYPASS1_DP_IN1_ROUTE 0x00000000
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#define CYVAL_UDB_P_U_DP_RTE_BYPASS1_DP_IN1_BYPASS 0x00000001
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#define CYFLD_UDB_P_U_DP_RTE_BYPASS2__OFFSET 0x00000005
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#define CYFLD_UDB_P_U_DP_RTE_BYPASS2__SIZE 0x00000001
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#define CYVAL_UDB_P_U_DP_RTE_BYPASS2_DP_IN2_ROUTE 0x00000000
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#define CYVAL_UDB_P_U_DP_RTE_BYPASS2_DP_IN2_BYPASS 0x00000001
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#define CYFLD_UDB_P_U_DP_RTE_BYPASS3__OFFSET 0x00000006
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#define CYFLD_UDB_P_U_DP_RTE_BYPASS3__SIZE 0x00000001
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#define CYVAL_UDB_P_U_DP_RTE_BYPASS3_DP_IN3_ROUTE 0x00000000
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#define CYVAL_UDB_P_U_DP_RTE_BYPASS3_DP_IN3_BYPASS 0x00000001
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#define CYFLD_UDB_P_U_DP_RTE_BYPASS4__OFFSET 0x00000007
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#define CYFLD_UDB_P_U_DP_RTE_BYPASS4__SIZE 0x00000001
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#define CYVAL_UDB_P_U_DP_RTE_BYPASS4_DP_IN4_ROUTE 0x00000000
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#define CYVAL_UDB_P_U_DP_RTE_BYPASS4_DP_IN4_BYPASS 0x00000001
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#define CYREG_UDB_P0_U0_CFG2 0x400f3042
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#define CYFLD_UDB_P_U_F0_LD__OFFSET 0x00000000
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#define CYFLD_UDB_P_U_F0_LD__SIZE 0x00000003
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#define CYVAL_UDB_P_U_F0_LD_OFF 0x00000000
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#define CYVAL_UDB_P_U_F0_LD_DP_IN0 0x00000001
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#define CYVAL_UDB_P_U_F0_LD_DP_IN1 0x00000002
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#define CYVAL_UDB_P_U_F0_LD_DP_IN2 0x00000003
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#define CYVAL_UDB_P_U_F0_LD_DP_IN3 0x00000004
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#define CYVAL_UDB_P_U_F0_LD_DP_IN4 0x00000005
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#define CYVAL_UDB_P_U_F0_LD_DP_IN5 0x00000006
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#define CYVAL_UDB_P_U_F0_LD_RESERVED 0x00000007
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#define CYFLD_UDB_P_U_DP_RTE_BYPASS5__OFFSET 0x00000003
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#define CYFLD_UDB_P_U_DP_RTE_BYPASS5__SIZE 0x00000001
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#define CYVAL_UDB_P_U_DP_RTE_BYPASS5_DP_IN5_ROUTE 0x00000000
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#define CYVAL_UDB_P_U_DP_RTE_BYPASS5_DP_IN5_BYPASS 0x00000001
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#define CYFLD_UDB_P_U_F1_LD__OFFSET 0x00000004
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#define CYFLD_UDB_P_U_F1_LD__SIZE 0x00000003
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#define CYVAL_UDB_P_U_F1_LD_OFF 0x00000000
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#define CYVAL_UDB_P_U_F1_LD_DP_IN0 0x00000001
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#define CYVAL_UDB_P_U_F1_LD_DP_IN1 0x00000002
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#define CYVAL_UDB_P_U_F1_LD_DP_IN2 0x00000003
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#define CYVAL_UDB_P_U_F1_LD_DP_IN3 0x00000004
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#define CYVAL_UDB_P_U_F1_LD_DP_IN4 0x00000005
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#define CYVAL_UDB_P_U_F1_LD_DP_IN5 0x00000006
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#define CYVAL_UDB_P_U_F1_LD_RESERVED 0x00000007
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#define CYREG_UDB_P0_U0_CFG3 0x400f3043
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#define CYFLD_UDB_P_U_D0_LD__OFFSET 0x00000000
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#define CYFLD_UDB_P_U_D0_LD__SIZE 0x00000003
|
|
#define CYVAL_UDB_P_U_D0_LD_OFF 0x00000000
|
|
#define CYVAL_UDB_P_U_D0_LD_DP_IN0 0x00000001
|
|
#define CYVAL_UDB_P_U_D0_LD_DP_IN1 0x00000002
|
|
#define CYVAL_UDB_P_U_D0_LD_DP_IN2 0x00000003
|
|
#define CYVAL_UDB_P_U_D0_LD_DP_IN3 0x00000004
|
|
#define CYVAL_UDB_P_U_D0_LD_DP_IN4 0x00000005
|
|
#define CYVAL_UDB_P_U_D0_LD_DP_IN5 0x00000006
|
|
#define CYVAL_UDB_P_U_D0_LD_RESERVED 0x00000007
|
|
#define CYFLD_UDB_P_U_D1_LD__OFFSET 0x00000004
|
|
#define CYFLD_UDB_P_U_D1_LD__SIZE 0x00000003
|
|
#define CYVAL_UDB_P_U_D1_LD_OFF 0x00000000
|
|
#define CYVAL_UDB_P_U_D1_LD_DP_IN0 0x00000001
|
|
#define CYVAL_UDB_P_U_D1_LD_DP_IN1 0x00000002
|
|
#define CYVAL_UDB_P_U_D1_LD_DP_IN2 0x00000003
|
|
#define CYVAL_UDB_P_U_D1_LD_DP_IN3 0x00000004
|
|
#define CYVAL_UDB_P_U_D1_LD_DP_IN4 0x00000005
|
|
#define CYVAL_UDB_P_U_D1_LD_DP_IN5 0x00000006
|
|
#define CYVAL_UDB_P_U_D1_LD_RESERVED 0x00000007
|
|
#define CYREG_UDB_P0_U0_CFG4 0x400f3044
|
|
#define CYFLD_UDB_P_U_SI_MUX__OFFSET 0x00000000
|
|
#define CYFLD_UDB_P_U_SI_MUX__SIZE 0x00000003
|
|
#define CYVAL_UDB_P_U_SI_MUX_OFF 0x00000000
|
|
#define CYVAL_UDB_P_U_SI_MUX_DP_IN0 0x00000001
|
|
#define CYVAL_UDB_P_U_SI_MUX_DP_IN1 0x00000002
|
|
#define CYVAL_UDB_P_U_SI_MUX_DP_IN2 0x00000003
|
|
#define CYVAL_UDB_P_U_SI_MUX_DP_IN3 0x00000004
|
|
#define CYVAL_UDB_P_U_SI_MUX_DP_IN4 0x00000005
|
|
#define CYVAL_UDB_P_U_SI_MUX_DP_IN5 0x00000006
|
|
#define CYVAL_UDB_P_U_SI_MUX_RESERVED 0x00000007
|
|
#define CYFLD_UDB_P_U_CI_MUX__OFFSET 0x00000004
|
|
#define CYFLD_UDB_P_U_CI_MUX__SIZE 0x00000003
|
|
#define CYVAL_UDB_P_U_CI_MUX_OFF 0x00000000
|
|
#define CYVAL_UDB_P_U_CI_MUX_DP_IN0 0x00000001
|
|
#define CYVAL_UDB_P_U_CI_MUX_DP_IN1 0x00000002
|
|
#define CYVAL_UDB_P_U_CI_MUX_DP_IN2 0x00000003
|
|
#define CYVAL_UDB_P_U_CI_MUX_DP_IN3 0x00000004
|
|
#define CYVAL_UDB_P_U_CI_MUX_DP_IN4 0x00000005
|
|
#define CYVAL_UDB_P_U_CI_MUX_DP_IN5 0x00000006
|
|
#define CYVAL_UDB_P_U_CI_MUX_RESERVED 0x00000007
|
|
#define CYREG_UDB_P0_U0_CFG5 0x400f3045
|
|
#define CYFLD_UDB_P_U_OUT0__OFFSET 0x00000000
|
|
#define CYFLD_UDB_P_U_OUT0__SIZE 0x00000004
|
|
#define CYVAL_UDB_P_U_OUT0_CE0 0x00000000
|
|
#define CYVAL_UDB_P_U_OUT0_CL0 0x00000001
|
|
#define CYVAL_UDB_P_U_OUT0_Z0 0x00000002
|
|
#define CYVAL_UDB_P_U_OUT0_FF0 0x00000003
|
|
#define CYVAL_UDB_P_U_OUT0_CE1 0x00000004
|
|
#define CYVAL_UDB_P_U_OUT0_CL1 0x00000005
|
|
#define CYVAL_UDB_P_U_OUT0_Z1 0x00000006
|
|
#define CYVAL_UDB_P_U_OUT0_FF1 0x00000007
|
|
#define CYVAL_UDB_P_U_OUT0_OV_MSB 0x00000008
|
|
#define CYVAL_UDB_P_U_OUT0_CO_MSB 0x00000009
|
|
#define CYVAL_UDB_P_U_OUT0_CMSBO 0x0000000a
|
|
#define CYVAL_UDB_P_U_OUT0_SO 0x0000000b
|
|
#define CYVAL_UDB_P_U_OUT0_F0_BLK_STAT 0x0000000c
|
|
#define CYVAL_UDB_P_U_OUT0_F1_BLK_STAT 0x0000000d
|
|
#define CYVAL_UDB_P_U_OUT0_F0_BUS_STAT 0x0000000e
|
|
#define CYVAL_UDB_P_U_OUT0_F1_BUS_STAT 0x0000000f
|
|
#define CYFLD_UDB_P_U_OUT1__OFFSET 0x00000004
|
|
#define CYFLD_UDB_P_U_OUT1__SIZE 0x00000004
|
|
#define CYVAL_UDB_P_U_OUT1_CE0 0x00000000
|
|
#define CYVAL_UDB_P_U_OUT1_CL0 0x00000001
|
|
#define CYVAL_UDB_P_U_OUT1_Z0 0x00000002
|
|
#define CYVAL_UDB_P_U_OUT1_FF0 0x00000003
|
|
#define CYVAL_UDB_P_U_OUT1_CE1 0x00000004
|
|
#define CYVAL_UDB_P_U_OUT1_CL1 0x00000005
|
|
#define CYVAL_UDB_P_U_OUT1_Z1 0x00000006
|
|
#define CYVAL_UDB_P_U_OUT1_FF1 0x00000007
|
|
#define CYVAL_UDB_P_U_OUT1_OV_MSB 0x00000008
|
|
#define CYVAL_UDB_P_U_OUT1_CO_MSB 0x00000009
|
|
#define CYVAL_UDB_P_U_OUT1_CMSBO 0x0000000a
|
|
#define CYVAL_UDB_P_U_OUT1_SO 0x0000000b
|
|
#define CYVAL_UDB_P_U_OUT1_F0_BLK_STAT 0x0000000c
|
|
#define CYVAL_UDB_P_U_OUT1_F1_BLK_STAT 0x0000000d
|
|
#define CYVAL_UDB_P_U_OUT1_F0_BUS_STAT 0x0000000e
|
|
#define CYVAL_UDB_P_U_OUT1_F1_BUS_STAT 0x0000000f
|
|
#define CYREG_UDB_P0_U0_CFG6 0x400f3046
|
|
#define CYFLD_UDB_P_U_OUT2__OFFSET 0x00000000
|
|
#define CYFLD_UDB_P_U_OUT2__SIZE 0x00000004
|
|
#define CYVAL_UDB_P_U_OUT2_CE0 0x00000000
|
|
#define CYVAL_UDB_P_U_OUT2_CL0 0x00000001
|
|
#define CYVAL_UDB_P_U_OUT2_Z0 0x00000002
|
|
#define CYVAL_UDB_P_U_OUT2_FF0 0x00000003
|
|
#define CYVAL_UDB_P_U_OUT2_CE1 0x00000004
|
|
#define CYVAL_UDB_P_U_OUT2_CL1 0x00000005
|
|
#define CYVAL_UDB_P_U_OUT2_Z1 0x00000006
|
|
#define CYVAL_UDB_P_U_OUT2_FF1 0x00000007
|
|
#define CYVAL_UDB_P_U_OUT2_OV_MSB 0x00000008
|
|
#define CYVAL_UDB_P_U_OUT2_CO_MSB 0x00000009
|
|
#define CYVAL_UDB_P_U_OUT2_CMSBO 0x0000000a
|
|
#define CYVAL_UDB_P_U_OUT2_SO 0x0000000b
|
|
#define CYVAL_UDB_P_U_OUT2_F0_BLK_STAT 0x0000000c
|
|
#define CYVAL_UDB_P_U_OUT2_F1_BLK_STAT 0x0000000d
|
|
#define CYVAL_UDB_P_U_OUT2_F0_BUS_STAT 0x0000000e
|
|
#define CYVAL_UDB_P_U_OUT2_F1_BUS_STAT 0x0000000f
|
|
#define CYFLD_UDB_P_U_OUT3__OFFSET 0x00000004
|
|
#define CYFLD_UDB_P_U_OUT3__SIZE 0x00000004
|
|
#define CYVAL_UDB_P_U_OUT3_CE0 0x00000000
|
|
#define CYVAL_UDB_P_U_OUT3_CL0 0x00000001
|
|
#define CYVAL_UDB_P_U_OUT3_Z0 0x00000002
|
|
#define CYVAL_UDB_P_U_OUT3_FF0 0x00000003
|
|
#define CYVAL_UDB_P_U_OUT3_CE1 0x00000004
|
|
#define CYVAL_UDB_P_U_OUT3_CL1 0x00000005
|
|
#define CYVAL_UDB_P_U_OUT3_Z1 0x00000006
|
|
#define CYVAL_UDB_P_U_OUT3_FF1 0x00000007
|
|
#define CYVAL_UDB_P_U_OUT3_OV_MSB 0x00000008
|
|
#define CYVAL_UDB_P_U_OUT3_CO_MSB 0x00000009
|
|
#define CYVAL_UDB_P_U_OUT3_CMSBO 0x0000000a
|
|
#define CYVAL_UDB_P_U_OUT3_SO 0x0000000b
|
|
#define CYVAL_UDB_P_U_OUT3_F0_BLK_STAT 0x0000000c
|
|
#define CYVAL_UDB_P_U_OUT3_F1_BLK_STAT 0x0000000d
|
|
#define CYVAL_UDB_P_U_OUT3_F0_BUS_STAT 0x0000000e
|
|
#define CYVAL_UDB_P_U_OUT3_F1_BUS_STAT 0x0000000f
|
|
#define CYREG_UDB_P0_U0_CFG7 0x400f3047
|
|
#define CYFLD_UDB_P_U_OUT4__OFFSET 0x00000000
|
|
#define CYFLD_UDB_P_U_OUT4__SIZE 0x00000004
|
|
#define CYVAL_UDB_P_U_OUT4_CE0 0x00000000
|
|
#define CYVAL_UDB_P_U_OUT4_CL0 0x00000001
|
|
#define CYVAL_UDB_P_U_OUT4_Z0 0x00000002
|
|
#define CYVAL_UDB_P_U_OUT4_FF0 0x00000003
|
|
#define CYVAL_UDB_P_U_OUT4_CE1 0x00000004
|
|
#define CYVAL_UDB_P_U_OUT4_CL1 0x00000005
|
|
#define CYVAL_UDB_P_U_OUT4_Z1 0x00000006
|
|
#define CYVAL_UDB_P_U_OUT4_FF1 0x00000007
|
|
#define CYVAL_UDB_P_U_OUT4_OV_MSB 0x00000008
|
|
#define CYVAL_UDB_P_U_OUT4_CO_MSB 0x00000009
|
|
#define CYVAL_UDB_P_U_OUT4_CMSBO 0x0000000a
|
|
#define CYVAL_UDB_P_U_OUT4_SO 0x0000000b
|
|
#define CYVAL_UDB_P_U_OUT4_F0_BLK_STAT 0x0000000c
|
|
#define CYVAL_UDB_P_U_OUT4_F1_BLK_STAT 0x0000000d
|
|
#define CYVAL_UDB_P_U_OUT4_F0_BUS_STAT 0x0000000e
|
|
#define CYVAL_UDB_P_U_OUT4_F1_BUS_STAT 0x0000000f
|
|
#define CYFLD_UDB_P_U_OUT5__OFFSET 0x00000004
|
|
#define CYFLD_UDB_P_U_OUT5__SIZE 0x00000004
|
|
#define CYVAL_UDB_P_U_OUT5_CE0 0x00000000
|
|
#define CYVAL_UDB_P_U_OUT5_CL0 0x00000001
|
|
#define CYVAL_UDB_P_U_OUT5_Z0 0x00000002
|
|
#define CYVAL_UDB_P_U_OUT5_FF0 0x00000003
|
|
#define CYVAL_UDB_P_U_OUT5_CE1 0x00000004
|
|
#define CYVAL_UDB_P_U_OUT5_CL1 0x00000005
|
|
#define CYVAL_UDB_P_U_OUT5_Z1 0x00000006
|
|
#define CYVAL_UDB_P_U_OUT5_FF1 0x00000007
|
|
#define CYVAL_UDB_P_U_OUT5_OV_MSB 0x00000008
|
|
#define CYVAL_UDB_P_U_OUT5_CO_MSB 0x00000009
|
|
#define CYVAL_UDB_P_U_OUT5_CMSBO 0x0000000a
|
|
#define CYVAL_UDB_P_U_OUT5_SO 0x0000000b
|
|
#define CYVAL_UDB_P_U_OUT5_F0_BLK_STAT 0x0000000c
|
|
#define CYVAL_UDB_P_U_OUT5_F1_BLK_STAT 0x0000000d
|
|
#define CYVAL_UDB_P_U_OUT5_F0_BUS_STAT 0x0000000e
|
|
#define CYVAL_UDB_P_U_OUT5_F1_BUS_STAT 0x0000000f
|
|
#define CYREG_UDB_P0_U0_CFG8 0x400f3048
|
|
#define CYFLD_UDB_P_U_OUT_SYNC__OFFSET 0x00000000
|
|
#define CYFLD_UDB_P_U_OUT_SYNC__SIZE 0x00000006
|
|
#define CYVAL_UDB_P_U_OUT_SYNC_REGISTERED 0x00000000
|
|
#define CYVAL_UDB_P_U_OUT_SYNC_COMBINATIONAL 0x00000001
|
|
#define CYFLD_UDB_P_U_NC6__OFFSET 0x00000006
|
|
#define CYFLD_UDB_P_U_NC6__SIZE 0x00000001
|
|
#define CYREG_UDB_P0_U0_CFG9 0x400f3049
|
|
#define CYFLD_UDB_P_U_AMASK__OFFSET 0x00000000
|
|
#define CYFLD_UDB_P_U_AMASK__SIZE 0x00000008
|
|
#define CYREG_UDB_P0_U0_CFG10 0x400f304a
|
|
#define CYFLD_UDB_P_U_CMASK0__OFFSET 0x00000000
|
|
#define CYFLD_UDB_P_U_CMASK0__SIZE 0x00000008
|
|
#define CYREG_UDB_P0_U0_CFG11 0x400f304b
|
|
#define CYREG_UDB_P0_U0_CFG12 0x400f304c
|
|
#define CYFLD_UDB_P_U_SI_SELA__OFFSET 0x00000000
|
|
#define CYFLD_UDB_P_U_SI_SELA__SIZE 0x00000002
|
|
#define CYVAL_UDB_P_U_SI_SELA_DEFAULT 0x00000000
|
|
#define CYVAL_UDB_P_U_SI_SELA_REGISTERED 0x00000001
|
|
#define CYVAL_UDB_P_U_SI_SELA_ROUTE 0x00000002
|
|
#define CYVAL_UDB_P_U_SI_SELA_CHAIN 0x00000003
|
|
#define CYFLD_UDB_P_U_SI_SELB__OFFSET 0x00000002
|
|
#define CYFLD_UDB_P_U_SI_SELB__SIZE 0x00000002
|
|
#define CYVAL_UDB_P_U_SI_SELB_DEFAULT 0x00000000
|
|
#define CYVAL_UDB_P_U_SI_SELB_REGISTERED 0x00000001
|
|
#define CYVAL_UDB_P_U_SI_SELB_ROUTE 0x00000002
|
|
#define CYVAL_UDB_P_U_SI_SELB_CHAIN 0x00000003
|
|
#define CYFLD_UDB_P_U_DEF_SI__OFFSET 0x00000004
|
|
#define CYFLD_UDB_P_U_DEF_SI__SIZE 0x00000001
|
|
#define CYVAL_UDB_P_U_DEF_SI_DEFAULT_0 0x00000000
|
|
#define CYVAL_UDB_P_U_DEF_SI_DEFAULT_1 0x00000001
|
|
#define CYFLD_UDB_P_U_AMASK_EN__OFFSET 0x00000005
|
|
#define CYFLD_UDB_P_U_AMASK_EN__SIZE 0x00000001
|
|
#define CYVAL_UDB_P_U_AMASK_EN_DISABLE 0x00000000
|
|
#define CYVAL_UDB_P_U_AMASK_EN_ENABLE 0x00000001
|
|
#define CYFLD_UDB_P_U_CMASK0_EN__OFFSET 0x00000006
|
|
#define CYFLD_UDB_P_U_CMASK0_EN__SIZE 0x00000001
|
|
#define CYVAL_UDB_P_U_CMASK0_EN_DISABLE 0x00000000
|
|
#define CYVAL_UDB_P_U_CMASK0_EN_ENABLE 0x00000001
|
|
#define CYFLD_UDB_P_U_CMASK1_EN__OFFSET 0x00000007
|
|
#define CYFLD_UDB_P_U_CMASK1_EN__SIZE 0x00000001
|
|
#define CYVAL_UDB_P_U_CMASK1_EN_DISABLE 0x00000000
|
|
#define CYVAL_UDB_P_U_CMASK1_EN_ENABLE 0x00000001
|
|
#define CYREG_UDB_P0_U0_CFG13 0x400f304d
|
|
#define CYFLD_UDB_P_U_CI_SELA__OFFSET 0x00000000
|
|
#define CYFLD_UDB_P_U_CI_SELA__SIZE 0x00000002
|
|
#define CYVAL_UDB_P_U_CI_SELA_DEFAULT 0x00000000
|
|
#define CYVAL_UDB_P_U_CI_SELA_REGISTERED 0x00000001
|
|
#define CYVAL_UDB_P_U_CI_SELA_ROUTE 0x00000002
|
|
#define CYVAL_UDB_P_U_CI_SELA_CHAIN 0x00000003
|
|
#define CYFLD_UDB_P_U_CI_SELB__OFFSET 0x00000002
|
|
#define CYFLD_UDB_P_U_CI_SELB__SIZE 0x00000002
|
|
#define CYVAL_UDB_P_U_CI_SELB_DEFAULT 0x00000000
|
|
#define CYVAL_UDB_P_U_CI_SELB_REGISTERED 0x00000001
|
|
#define CYVAL_UDB_P_U_CI_SELB_ROUTE 0x00000002
|
|
#define CYVAL_UDB_P_U_CI_SELB_CHAIN 0x00000003
|
|
#define CYFLD_UDB_P_U_CMP_SELA__OFFSET 0x00000004
|
|
#define CYFLD_UDB_P_U_CMP_SELA__SIZE 0x00000002
|
|
#define CYVAL_UDB_P_U_CMP_SELA_A1_D1 0x00000000
|
|
#define CYVAL_UDB_P_U_CMP_SELA_A1_A0 0x00000001
|
|
#define CYVAL_UDB_P_U_CMP_SELA_A0_D1 0x00000002
|
|
#define CYVAL_UDB_P_U_CMP_SELA_A0_A0 0x00000003
|
|
#define CYFLD_UDB_P_U_CMP_SELB__OFFSET 0x00000006
|
|
#define CYFLD_UDB_P_U_CMP_SELB__SIZE 0x00000002
|
|
#define CYVAL_UDB_P_U_CMP_SELB_A1_D1 0x00000000
|
|
#define CYVAL_UDB_P_U_CMP_SELB_A1_A0 0x00000001
|
|
#define CYVAL_UDB_P_U_CMP_SELB_A0_D1 0x00000002
|
|
#define CYVAL_UDB_P_U_CMP_SELB_A0_A0 0x00000003
|
|
#define CYREG_UDB_P0_U0_CFG14 0x400f304e
|
|
#define CYFLD_UDB_P_U_CHAIN0__OFFSET 0x00000000
|
|
#define CYFLD_UDB_P_U_CHAIN0__SIZE 0x00000001
|
|
#define CYVAL_UDB_P_U_CHAIN0_DISABLE 0x00000000
|
|
#define CYVAL_UDB_P_U_CHAIN0_ENABLE 0x00000001
|
|
#define CYFLD_UDB_P_U_CHAIN1__OFFSET 0x00000001
|
|
#define CYFLD_UDB_P_U_CHAIN1__SIZE 0x00000001
|
|
#define CYVAL_UDB_P_U_CHAIN1_DISABLE 0x00000000
|
|
#define CYVAL_UDB_P_U_CHAIN1_ENABLE 0x00000001
|
|
#define CYFLD_UDB_P_U_CHAIN_FB__OFFSET 0x00000002
|
|
#define CYFLD_UDB_P_U_CHAIN_FB__SIZE 0x00000001
|
|
#define CYVAL_UDB_P_U_CHAIN_FB_DISABLE 0x00000000
|
|
#define CYVAL_UDB_P_U_CHAIN_FB_ENABLE 0x00000001
|
|
#define CYFLD_UDB_P_U_CHAIN_CMSB__OFFSET 0x00000003
|
|
#define CYFLD_UDB_P_U_CHAIN_CMSB__SIZE 0x00000001
|
|
#define CYVAL_UDB_P_U_CHAIN_CMSB_DISABLE 0x00000000
|
|
#define CYVAL_UDB_P_U_CHAIN_CMSB_ENABLE 0x00000001
|
|
#define CYFLD_UDB_P_U_MSB_SEL__OFFSET 0x00000004
|
|
#define CYFLD_UDB_P_U_MSB_SEL__SIZE 0x00000003
|
|
#define CYVAL_UDB_P_U_MSB_SEL_BIT0 0x00000000
|
|
#define CYVAL_UDB_P_U_MSB_SEL_BIT1 0x00000001
|
|
#define CYVAL_UDB_P_U_MSB_SEL_BIT2 0x00000002
|
|
#define CYVAL_UDB_P_U_MSB_SEL_BIT3 0x00000003
|
|
#define CYVAL_UDB_P_U_MSB_SEL_BIT4 0x00000004
|
|
#define CYVAL_UDB_P_U_MSB_SEL_BIT5 0x00000005
|
|
#define CYVAL_UDB_P_U_MSB_SEL_BIT6 0x00000006
|
|
#define CYVAL_UDB_P_U_MSB_SEL_BIT7 0x00000007
|
|
#define CYFLD_UDB_P_U_MSB_EN__OFFSET 0x00000007
|
|
#define CYFLD_UDB_P_U_MSB_EN__SIZE 0x00000001
|
|
#define CYVAL_UDB_P_U_MSB_EN_DISABLE 0x00000000
|
|
#define CYVAL_UDB_P_U_MSB_EN_ENABLE 0x00000001
|
|
#define CYREG_UDB_P0_U0_CFG15 0x400f304f
|
|
#define CYFLD_UDB_P_U_F0_INSEL__OFFSET 0x00000000
|
|
#define CYFLD_UDB_P_U_F0_INSEL__SIZE 0x00000002
|
|
#define CYVAL_UDB_P_U_F0_INSEL_INPUT 0x00000000
|
|
#define CYVAL_UDB_P_U_F0_INSEL_OUTPUT_A0 0x00000001
|
|
#define CYVAL_UDB_P_U_F0_INSEL_OUTPUT_A1 0x00000002
|
|
#define CYVAL_UDB_P_U_F0_INSEL_OUTPUT_ALU 0x00000003
|
|
#define CYFLD_UDB_P_U_F1_INSEL__OFFSET 0x00000002
|
|
#define CYFLD_UDB_P_U_F1_INSEL__SIZE 0x00000002
|
|
#define CYVAL_UDB_P_U_F1_INSEL_INPUT 0x00000000
|
|
#define CYVAL_UDB_P_U_F1_INSEL_OUTPUT_A0 0x00000001
|
|
#define CYVAL_UDB_P_U_F1_INSEL_OUTPUT_A1 0x00000002
|
|
#define CYVAL_UDB_P_U_F1_INSEL_OUTPUT_ALU 0x00000003
|
|
#define CYFLD_UDB_P_U_MSB_SI__OFFSET 0x00000004
|
|
#define CYFLD_UDB_P_U_MSB_SI__SIZE 0x00000001
|
|
#define CYVAL_UDB_P_U_MSB_SI_DEFAULT 0x00000000
|
|
#define CYVAL_UDB_P_U_MSB_SI_MSB 0x00000001
|
|
#define CYFLD_UDB_P_U_PI_DYN__OFFSET 0x00000005
|
|
#define CYFLD_UDB_P_U_PI_DYN__SIZE 0x00000001
|
|
#define CYVAL_UDB_P_U_PI_DYN_DISABLE 0x00000000
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#define CYVAL_UDB_P_U_PI_DYN_ENABLE 0x00000001
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#define CYFLD_UDB_P_U_SHIFT_SEL__OFFSET 0x00000006
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#define CYFLD_UDB_P_U_SHIFT_SEL__SIZE 0x00000001
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#define CYVAL_UDB_P_U_SHIFT_SEL_SOL_MSB 0x00000000
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#define CYVAL_UDB_P_U_SHIFT_SEL_SOR 0x00000001
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#define CYFLD_UDB_P_U_PI_SEL__OFFSET 0x00000007
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#define CYFLD_UDB_P_U_PI_SEL__SIZE 0x00000001
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#define CYVAL_UDB_P_U_PI_SEL_NORMAL 0x00000000
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#define CYVAL_UDB_P_U_PI_SEL_PARALLEL 0x00000001
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#define CYREG_UDB_P0_U0_CFG16 0x400f3050
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#define CYFLD_UDB_P_U_WRK16_CONCAT__OFFSET 0x00000000
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#define CYFLD_UDB_P_U_WRK16_CONCAT__SIZE 0x00000001
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#define CYVAL_UDB_P_U_WRK16_CONCAT_DEFAULT 0x00000000
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#define CYVAL_UDB_P_U_WRK16_CONCAT_CONCATENATE 0x00000001
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#define CYFLD_UDB_P_U_EXT_CRCPRS__OFFSET 0x00000001
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#define CYFLD_UDB_P_U_EXT_CRCPRS__SIZE 0x00000001
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#define CYVAL_UDB_P_U_EXT_CRCPRS_INTERNAL 0x00000000
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#define CYVAL_UDB_P_U_EXT_CRCPRS_EXTERNAL 0x00000001
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#define CYFLD_UDB_P_U_FIFO_ASYNC__OFFSET 0x00000002
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#define CYFLD_UDB_P_U_FIFO_ASYNC__SIZE 0x00000001
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#define CYVAL_UDB_P_U_FIFO_ASYNC_DISABLE 0x00000000
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#define CYVAL_UDB_P_U_FIFO_ASYNC_ENABLE 0x00000001
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#define CYFLD_UDB_P_U_FIFO_EDGE__OFFSET 0x00000003
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#define CYFLD_UDB_P_U_FIFO_EDGE__SIZE 0x00000001
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#define CYVAL_UDB_P_U_FIFO_EDGE_LEVEL 0x00000000
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#define CYVAL_UDB_P_U_FIFO_EDGE_EDGE 0x00000001
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#define CYFLD_UDB_P_U_FIFO_CAP__OFFSET 0x00000004
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#define CYFLD_UDB_P_U_FIFO_CAP__SIZE 0x00000001
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#define CYVAL_UDB_P_U_FIFO_CAP_DISABLE 0x00000000
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#define CYVAL_UDB_P_U_FIFO_CAP_ENABLE 0x00000001
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#define CYFLD_UDB_P_U_FIFO_FAST__OFFSET 0x00000005
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#define CYFLD_UDB_P_U_FIFO_FAST__SIZE 0x00000001
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#define CYVAL_UDB_P_U_FIFO_FAST_DISABLE 0x00000000
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#define CYVAL_UDB_P_U_FIFO_FAST_ENABLE 0x00000001
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#define CYFLD_UDB_P_U_F0_CK_INV__OFFSET 0x00000006
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#define CYFLD_UDB_P_U_F0_CK_INV__SIZE 0x00000001
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#define CYVAL_UDB_P_U_F0_CK_INV_NORMAL 0x00000000
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#define CYVAL_UDB_P_U_F0_CK_INV_INVERT 0x00000001
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#define CYFLD_UDB_P_U_F1_CK_INV__OFFSET 0x00000007
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#define CYFLD_UDB_P_U_F1_CK_INV__SIZE 0x00000001
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#define CYVAL_UDB_P_U_F1_CK_INV_NORMAL 0x00000000
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#define CYVAL_UDB_P_U_F1_CK_INV_INVERT 0x00000001
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#define CYREG_UDB_P0_U0_CFG17 0x400f3051
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#define CYFLD_UDB_P_U_F0_DYN__OFFSET 0x00000000
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#define CYFLD_UDB_P_U_F0_DYN__SIZE 0x00000001
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#define CYVAL_UDB_P_U_F0_DYN_STATIC 0x00000000
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#define CYVAL_UDB_P_U_F0_DYN_DYNAMIC 0x00000001
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#define CYFLD_UDB_P_U_F1_DYN__OFFSET 0x00000001
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#define CYFLD_UDB_P_U_F1_DYN__SIZE 0x00000001
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#define CYVAL_UDB_P_U_F1_DYN_STATIC 0x00000000
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#define CYVAL_UDB_P_U_F1_DYN_DYNAMIC 0x00000001
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#define CYFLD_UDB_P_U_NC2__OFFSET 0x00000002
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#define CYFLD_UDB_P_U_NC2__SIZE 0x00000001
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#define CYFLD_UDB_P_U_FIFO_ADD_SYNC__OFFSET 0x00000004
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#define CYFLD_UDB_P_U_FIFO_ADD_SYNC__SIZE 0x00000001
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#define CYVAL_UDB_P_U_FIFO_ADD_SYNC_DISABLE 0x00000000
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#define CYVAL_UDB_P_U_FIFO_ADD_SYNC_ENABLE 0x00000001
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#define CYREG_UDB_P0_U0_CFG18 0x400f3052
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#define CYFLD_UDB_P_U_CTL_MD0__OFFSET 0x00000000
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#define CYFLD_UDB_P_U_CTL_MD0__SIZE 0x00000008
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#define CYVAL_UDB_P_U_CTL_MD0_DIRECT 0x00000000
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#define CYVAL_UDB_P_U_CTL_MD0_SYNC 0x00000001
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#define CYVAL_UDB_P_U_CTL_MD0_DOUBLE_SYNC 0x00000002
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#define CYVAL_UDB_P_U_CTL_MD0_PULSE 0x00000003
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#define CYREG_UDB_P0_U0_CFG19 0x400f3053
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#define CYFLD_UDB_P_U_CTL_MD1__OFFSET 0x00000000
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#define CYFLD_UDB_P_U_CTL_MD1__SIZE 0x00000008
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#define CYVAL_UDB_P_U_CTL_MD1_DIRECT 0x00000000
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#define CYVAL_UDB_P_U_CTL_MD1_SYNC 0x00000001
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#define CYVAL_UDB_P_U_CTL_MD1_DOUBLE_SYNC 0x00000002
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#define CYVAL_UDB_P_U_CTL_MD1_PULSE 0x00000003
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#define CYREG_UDB_P0_U0_CFG20 0x400f3054
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#define CYFLD_UDB_P_U_STAT_MD__OFFSET 0x00000000
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#define CYFLD_UDB_P_U_STAT_MD__SIZE 0x00000008
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#define CYREG_UDB_P0_U0_CFG21 0x400f3055
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#define CYFLD_UDB_P_U_NC0__OFFSET 0x00000000
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#define CYFLD_UDB_P_U_NC0__SIZE 0x00000001
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#define CYREG_UDB_P0_U0_CFG22 0x400f3056
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#define CYFLD_UDB_P_U_SC_OUT_CTL__OFFSET 0x00000000
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#define CYFLD_UDB_P_U_SC_OUT_CTL__SIZE 0x00000002
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#define CYVAL_UDB_P_U_SC_OUT_CTL_CONTROL 0x00000000
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#define CYVAL_UDB_P_U_SC_OUT_CTL_PARALLEL 0x00000001
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#define CYVAL_UDB_P_U_SC_OUT_CTL_COUNTER 0x00000002
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#define CYVAL_UDB_P_U_SC_OUT_CTL_RESERVED 0x00000003
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#define CYFLD_UDB_P_U_SC_INT_MD__OFFSET 0x00000002
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#define CYFLD_UDB_P_U_SC_INT_MD__SIZE 0x00000001
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#define CYVAL_UDB_P_U_SC_INT_MD_NORMAL 0x00000000
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#define CYVAL_UDB_P_U_SC_INT_MD_INT_MODE 0x00000001
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#define CYFLD_UDB_P_U_SC_SYNC_MD__OFFSET 0x00000003
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#define CYFLD_UDB_P_U_SC_SYNC_MD__SIZE 0x00000001
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#define CYVAL_UDB_P_U_SC_SYNC_MD_NORMAL 0x00000000
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#define CYVAL_UDB_P_U_SC_SYNC_MD_SYNC_MODE 0x00000001
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#define CYFLD_UDB_P_U_SC_EXT_RES__OFFSET 0x00000004
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#define CYFLD_UDB_P_U_SC_EXT_RES__SIZE 0x00000001
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#define CYVAL_UDB_P_U_SC_EXT_RES_DISABLED 0x00000000
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#define CYVAL_UDB_P_U_SC_EXT_RES_ENABLED 0x00000001
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#define CYREG_UDB_P0_U0_CFG23 0x400f3057
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#define CYFLD_UDB_P_U_CNT_LD_SEL__OFFSET 0x00000000
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#define CYFLD_UDB_P_U_CNT_LD_SEL__SIZE 0x00000002
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#define CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN0 0x00000000
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#define CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN1 0x00000001
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#define CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN2 0x00000002
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#define CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN3 0x00000003
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#define CYFLD_UDB_P_U_CNT_EN_SEL__OFFSET 0x00000002
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#define CYFLD_UDB_P_U_CNT_EN_SEL__SIZE 0x00000002
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#define CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN4 0x00000000
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#define CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN5 0x00000001
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#define CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN6 0x00000002
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#define CYVAL_UDB_P_U_CNT_EN_SEL_SC_IO 0x00000003
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#define CYFLD_UDB_P_U_ROUTE_LD__OFFSET 0x00000004
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#define CYFLD_UDB_P_U_ROUTE_LD__SIZE 0x00000001
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#define CYVAL_UDB_P_U_ROUTE_LD_DISABLE 0x00000000
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#define CYVAL_UDB_P_U_ROUTE_LD_ROUTED 0x00000001
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#define CYFLD_UDB_P_U_ROUTE_EN__OFFSET 0x00000005
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#define CYFLD_UDB_P_U_ROUTE_EN__SIZE 0x00000001
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#define CYVAL_UDB_P_U_ROUTE_EN_DISABLE 0x00000000
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#define CYVAL_UDB_P_U_ROUTE_EN_ROUTED 0x00000001
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#define CYFLD_UDB_P_U_ALT_CNT__OFFSET 0x00000006
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#define CYFLD_UDB_P_U_ALT_CNT__SIZE 0x00000001
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#define CYVAL_UDB_P_U_ALT_CNT_DEFAULT_MODE 0x00000000
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#define CYVAL_UDB_P_U_ALT_CNT_ALT_MODE 0x00000001
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#define CYREG_UDB_P0_U0_CFG24 0x400f3058
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#define CYFLD_UDB_P_U_RC_EN_SEL__OFFSET 0x00000000
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#define CYFLD_UDB_P_U_RC_EN_SEL__SIZE 0x00000002
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#define CYVAL_UDB_P_U_RC_EN_SEL_RC_IN0 0x00000000
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#define CYVAL_UDB_P_U_RC_EN_SEL_RC_IN1 0x00000001
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#define CYVAL_UDB_P_U_RC_EN_SEL_RC_IN2 0x00000002
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#define CYVAL_UDB_P_U_RC_EN_SEL_RC_IN3 0x00000003
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#define CYFLD_UDB_P_U_RC_EN_MODE__OFFSET 0x00000002
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#define CYFLD_UDB_P_U_RC_EN_MODE__SIZE 0x00000002
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#define CYVAL_UDB_P_U_RC_EN_MODE_OFF 0x00000000
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#define CYVAL_UDB_P_U_RC_EN_MODE_ON 0x00000001
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#define CYVAL_UDB_P_U_RC_EN_MODE_POSEDGE 0x00000002
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#define CYVAL_UDB_P_U_RC_EN_MODE_LEVEL 0x00000003
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#define CYFLD_UDB_P_U_RC_EN_INV__OFFSET 0x00000004
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#define CYFLD_UDB_P_U_RC_EN_INV__SIZE 0x00000001
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#define CYVAL_UDB_P_U_RC_EN_INV_NOINV 0x00000000
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#define CYVAL_UDB_P_U_RC_EN_INV_INVERT 0x00000001
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#define CYFLD_UDB_P_U_RC_INV__OFFSET 0x00000005
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#define CYFLD_UDB_P_U_RC_INV__SIZE 0x00000001
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#define CYVAL_UDB_P_U_RC_INV_NOINV 0x00000000
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#define CYVAL_UDB_P_U_RC_INV_INVERT 0x00000001
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#define CYFLD_UDB_P_U_RC_RES_SEL0_OR_FRES__OFFSET 0x00000006
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#define CYFLD_UDB_P_U_RC_RES_SEL0_OR_FRES__SIZE 0x00000001
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#define CYFLD_UDB_P_U_RC_RES_SEL1__OFFSET 0x00000007
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#define CYFLD_UDB_P_U_RC_RES_SEL1__SIZE 0x00000001
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#define CYREG_UDB_P0_U0_CFG25 0x400f3059
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#define CYREG_UDB_P0_U0_CFG26 0x400f305a
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#define CYREG_UDB_P0_U0_CFG27 0x400f305b
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#define CYREG_UDB_P0_U0_CFG28 0x400f305c
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#define CYFLD_UDB_P_U_PLD0_CK_SEL__OFFSET 0x00000000
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#define CYFLD_UDB_P_U_PLD0_CK_SEL__SIZE 0x00000004
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#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK0 0x00000000
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#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK1 0x00000001
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#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK2 0x00000002
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#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK3 0x00000003
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#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK4 0x00000004
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#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK5 0x00000005
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#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK6 0x00000006
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#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK7 0x00000007
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#define CYVAL_UDB_P_U_PLD0_CK_SEL_EXT_CLK 0x00000008
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#define CYVAL_UDB_P_U_PLD0_CK_SEL_SYSCLK 0x00000009
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#define CYFLD_UDB_P_U_PLD1_CK_SEL__OFFSET 0x00000004
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#define CYFLD_UDB_P_U_PLD1_CK_SEL__SIZE 0x00000004
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#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK0 0x00000000
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#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK1 0x00000001
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#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK2 0x00000002
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#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK3 0x00000003
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#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK4 0x00000004
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#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK5 0x00000005
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#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK6 0x00000006
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#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK7 0x00000007
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#define CYVAL_UDB_P_U_PLD1_CK_SEL_EXT_CLK 0x00000008
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#define CYVAL_UDB_P_U_PLD1_CK_SEL_SYSCLK 0x00000009
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#define CYREG_UDB_P0_U0_CFG29 0x400f305d
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#define CYFLD_UDB_P_U_DP_CK_SEL__OFFSET 0x00000000
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#define CYFLD_UDB_P_U_DP_CK_SEL__SIZE 0x00000004
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#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK0 0x00000000
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#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK1 0x00000001
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#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK2 0x00000002
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#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK3 0x00000003
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#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK4 0x00000004
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#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK5 0x00000005
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#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK6 0x00000006
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#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK7 0x00000007
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#define CYVAL_UDB_P_U_DP_CK_SEL_EXT_CLK 0x00000008
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#define CYVAL_UDB_P_U_DP_CK_SEL_SYSCLK 0x00000009
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#define CYFLD_UDB_P_U_SC_CK_SEL__OFFSET 0x00000004
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#define CYFLD_UDB_P_U_SC_CK_SEL__SIZE 0x00000004
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#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK0 0x00000000
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#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK1 0x00000001
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#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK2 0x00000002
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#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK3 0x00000003
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#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK4 0x00000004
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#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK5 0x00000005
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#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK6 0x00000006
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#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK7 0x00000007
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#define CYVAL_UDB_P_U_SC_CK_SEL_EXT_CLK 0x00000008
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#define CYVAL_UDB_P_U_SC_CK_SEL_SYSCLK 0x00000009
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#define CYREG_UDB_P0_U0_CFG30 0x400f305e
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#define CYFLD_UDB_P_U_RES_SEL__OFFSET 0x00000000
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#define CYFLD_UDB_P_U_RES_SEL__SIZE 0x00000002
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#define CYVAL_UDB_P_U_RES_SEL_RC_IN0 0x00000000
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#define CYVAL_UDB_P_U_RES_SEL_RC_IN1 0x00000001
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#define CYVAL_UDB_P_U_RES_SEL_RC_IN2 0x00000002
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#define CYVAL_UDB_P_U_RES_SEL_RC_IN3 0x00000003
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#define CYFLD_UDB_P_U_RES_POL__OFFSET 0x00000002
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#define CYFLD_UDB_P_U_RES_POL__SIZE 0x00000001
|
|
#define CYVAL_UDB_P_U_RES_POL_NEGATED 0x00000000
|
|
#define CYVAL_UDB_P_U_RES_POL_ASSERTED 0x00000001
|
|
#define CYFLD_UDB_P_U_EN_RES_CNTCTL__OFFSET 0x00000003
|
|
#define CYFLD_UDB_P_U_EN_RES_CNTCTL__SIZE 0x00000001
|
|
#define CYVAL_UDB_P_U_EN_RES_CNTCTL_DISABLE 0x00000000
|
|
#define CYVAL_UDB_P_U_EN_RES_CNTCTL_ENABLE 0x00000001
|
|
#define CYFLD_UDB_P_U_GUDB_WR__OFFSET 0x00000004
|
|
#define CYFLD_UDB_P_U_GUDB_WR__SIZE 0x00000001
|
|
#define CYVAL_UDB_P_U_GUDB_WR_DISABLE 0x00000000
|
|
#define CYVAL_UDB_P_U_GUDB_WR_ENABLE 0x00000001
|
|
#define CYFLD_UDB_P_U_DP_RES_POL__OFFSET 0x00000006
|
|
#define CYFLD_UDB_P_U_DP_RES_POL__SIZE 0x00000001
|
|
#define CYVAL_UDB_P_U_DP_RES_POL_NOINV 0x00000000
|
|
#define CYVAL_UDB_P_U_DP_RES_POL_INVERT 0x00000001
|
|
#define CYFLD_UDB_P_U_SC_RES_POL__OFFSET 0x00000007
|
|
#define CYFLD_UDB_P_U_SC_RES_POL__SIZE 0x00000001
|
|
#define CYVAL_UDB_P_U_SC_RES_POL_NOINV 0x00000000
|
|
#define CYVAL_UDB_P_U_SC_RES_POL_INVERT 0x00000001
|
|
#define CYREG_UDB_P0_U0_CFG31 0x400f305f
|
|
#define CYFLD_UDB_P_U_ALT_RES__OFFSET 0x00000000
|
|
#define CYFLD_UDB_P_U_ALT_RES__SIZE 0x00000001
|
|
#define CYVAL_UDB_P_U_ALT_RES_COMPATIBLE 0x00000000
|
|
#define CYVAL_UDB_P_U_ALT_RES_ALTERNATE 0x00000001
|
|
#define CYFLD_UDB_P_U_EXT_SYNC__OFFSET 0x00000001
|
|
#define CYFLD_UDB_P_U_EXT_SYNC__SIZE 0x00000001
|
|
#define CYVAL_UDB_P_U_EXT_SYNC_DISABLE 0x00000000
|
|
#define CYVAL_UDB_P_U_EXT_SYNC_ENABLE 0x00000001
|
|
#define CYFLD_UDB_P_U_EN_RES_STAT__OFFSET 0x00000002
|
|
#define CYFLD_UDB_P_U_EN_RES_STAT__SIZE 0x00000001
|
|
#define CYVAL_UDB_P_U_EN_RES_STAT_NEGATED 0x00000000
|
|
#define CYVAL_UDB_P_U_EN_RES_STAT_ASSERTED 0x00000001
|
|
#define CYFLD_UDB_P_U_EN_RES_DP__OFFSET 0x00000003
|
|
#define CYFLD_UDB_P_U_EN_RES_DP__SIZE 0x00000001
|
|
#define CYVAL_UDB_P_U_EN_RES_DP_DISABLE 0x00000000
|
|
#define CYVAL_UDB_P_U_EN_RES_DP_ENABLE 0x00000001
|
|
#define CYFLD_UDB_P_U_EXT_CK_SEL__OFFSET 0x00000004
|
|
#define CYFLD_UDB_P_U_EXT_CK_SEL__SIZE 0x00000002
|
|
#define CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN0 0x00000000
|
|
#define CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN1 0x00000001
|
|
#define CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN2 0x00000002
|
|
#define CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN3 0x00000003
|
|
#define CYFLD_UDB_P_U_PLD0_RES_POL__OFFSET 0x00000006
|
|
#define CYFLD_UDB_P_U_PLD0_RES_POL__SIZE 0x00000001
|
|
#define CYVAL_UDB_P_U_PLD0_RES_POL_NOINV 0x00000000
|
|
#define CYVAL_UDB_P_U_PLD0_RES_POL_INVERT 0x00000001
|
|
#define CYFLD_UDB_P_U_PLD1_RES_POL__OFFSET 0x00000007
|
|
#define CYFLD_UDB_P_U_PLD1_RES_POL__SIZE 0x00000001
|
|
#define CYVAL_UDB_P_U_PLD1_RES_POL_NOINV 0x00000000
|
|
#define CYVAL_UDB_P_U_PLD1_RES_POL_INVERT 0x00000001
|
|
#define CYREG_UDB_P0_U0_DCFG0 0x400f3060
|
|
#define CYFLD_UDB_P_U_CMP_SEL__OFFSET 0x00000000
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#define CYFLD_UDB_P_U_CMP_SEL__SIZE 0x00000001
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#define CYVAL_UDB_P_U_CMP_SEL_CFG_A 0x00000000
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#define CYVAL_UDB_P_U_CMP_SEL_CFG_B 0x00000001
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#define CYFLD_UDB_P_U_SI_SEL__OFFSET 0x00000001
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#define CYFLD_UDB_P_U_SI_SEL__SIZE 0x00000001
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#define CYVAL_UDB_P_U_SI_SEL_CFG_A 0x00000000
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#define CYVAL_UDB_P_U_SI_SEL_CFG_B 0x00000001
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#define CYFLD_UDB_P_U_CI_SEL__OFFSET 0x00000002
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#define CYFLD_UDB_P_U_CI_SEL__SIZE 0x00000001
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#define CYVAL_UDB_P_U_CI_SEL_CFG_A 0x00000000
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#define CYVAL_UDB_P_U_CI_SEL_CFG_B 0x00000001
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#define CYFLD_UDB_P_U_CFB_EN__OFFSET 0x00000003
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#define CYFLD_UDB_P_U_CFB_EN__SIZE 0x00000001
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#define CYVAL_UDB_P_U_CFB_EN_DISABLE 0x00000000
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#define CYVAL_UDB_P_U_CFB_EN_ENABLE 0x00000001
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#define CYFLD_UDB_P_U_A1_WR_SRC__OFFSET 0x00000004
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#define CYFLD_UDB_P_U_A1_WR_SRC__SIZE 0x00000002
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#define CYVAL_UDB_P_U_A1_WR_SRC_NOWRITE 0x00000000
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#define CYVAL_UDB_P_U_A1_WR_SRC_ALU 0x00000001
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#define CYVAL_UDB_P_U_A1_WR_SRC_D1 0x00000002
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#define CYVAL_UDB_P_U_A1_WR_SRC_F1 0x00000003
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#define CYFLD_UDB_P_U_A0_WR_SRC__OFFSET 0x00000006
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#define CYFLD_UDB_P_U_A0_WR_SRC__SIZE 0x00000002
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#define CYVAL_UDB_P_U_A0_WR_SRC_NOWRITE 0x00000000
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#define CYVAL_UDB_P_U_A0_WR_SRC_ALU 0x00000001
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#define CYVAL_UDB_P_U_A0_WR_SRC_D0 0x00000002
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#define CYVAL_UDB_P_U_A0_WR_SRC_F0 0x00000003
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#define CYFLD_UDB_P_U_SHIFT__OFFSET 0x00000008
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#define CYFLD_UDB_P_U_SHIFT__SIZE 0x00000002
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#define CYVAL_UDB_P_U_SHIFT_NOSHIFT 0x00000000
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#define CYVAL_UDB_P_U_SHIFT_LEFT 0x00000001
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#define CYVAL_UDB_P_U_SHIFT_RIGHT 0x00000002
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#define CYVAL_UDB_P_U_SHIFT_SWAP 0x00000003
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#define CYFLD_UDB_P_U_SRC_B__OFFSET 0x0000000a
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#define CYFLD_UDB_P_U_SRC_B__SIZE 0x00000002
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#define CYVAL_UDB_P_U_SRC_B_D0 0x00000000
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#define CYVAL_UDB_P_U_SRC_B_D1 0x00000001
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#define CYVAL_UDB_P_U_SRC_B_A0 0x00000002
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#define CYVAL_UDB_P_U_SRC_B_A1 0x00000003
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#define CYFLD_UDB_P_U_SRC_A__OFFSET 0x0000000c
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#define CYFLD_UDB_P_U_SRC_A__SIZE 0x00000001
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#define CYVAL_UDB_P_U_SRC_A_A0 0x00000000
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#define CYVAL_UDB_P_U_SRC_A_A1 0x00000001
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#define CYFLD_UDB_P_U_FUNC__OFFSET 0x0000000d
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#define CYFLD_UDB_P_U_FUNC__SIZE 0x00000003
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#define CYVAL_UDB_P_U_FUNC_PASS 0x00000000
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#define CYVAL_UDB_P_U_FUNC_INC_A 0x00000001
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#define CYVAL_UDB_P_U_FUNC_DEC_A 0x00000002
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#define CYVAL_UDB_P_U_FUNC_ADD 0x00000003
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#define CYVAL_UDB_P_U_FUNC_SUB 0x00000004
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#define CYVAL_UDB_P_U_FUNC_XOR 0x00000005
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#define CYVAL_UDB_P_U_FUNC_AND 0x00000006
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#define CYVAL_UDB_P_U_FUNC_OR 0x00000007
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#define CYREG_UDB_P0_U0_DCFG1 0x400f3062
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#define CYREG_UDB_P0_U0_DCFG2 0x400f3064
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#define CYREG_UDB_P0_U0_DCFG3 0x400f3066
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#define CYREG_UDB_P0_U0_DCFG4 0x400f3068
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#define CYREG_UDB_P0_U0_DCFG5 0x400f306a
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#define CYREG_UDB_P0_U0_DCFG6 0x400f306c
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#define CYREG_UDB_P0_U0_DCFG7 0x400f306e
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#define CYDEV_UDB_P0_U1_BASE 0x400f3080
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#define CYDEV_UDB_P0_U1_SIZE 0x00000080
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#define CYREG_UDB_P0_U1_PLD_IT0 0x400f3080
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#define CYREG_UDB_P0_U1_PLD_IT1 0x400f3084
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#define CYREG_UDB_P0_U1_PLD_IT2 0x400f3088
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#define CYREG_UDB_P0_U1_PLD_IT3 0x400f308c
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#define CYREG_UDB_P0_U1_PLD_IT4 0x400f3090
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#define CYREG_UDB_P0_U1_PLD_IT5 0x400f3094
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#define CYREG_UDB_P0_U1_PLD_IT6 0x400f3098
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#define CYREG_UDB_P0_U1_PLD_IT7 0x400f309c
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#define CYREG_UDB_P0_U1_PLD_IT8 0x400f30a0
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#define CYREG_UDB_P0_U1_PLD_IT9 0x400f30a4
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#define CYREG_UDB_P0_U1_PLD_IT10 0x400f30a8
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#define CYREG_UDB_P0_U1_PLD_IT11 0x400f30ac
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#define CYREG_UDB_P0_U1_PLD_ORT0 0x400f30b0
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#define CYREG_UDB_P0_U1_PLD_ORT1 0x400f30b2
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#define CYREG_UDB_P0_U1_PLD_ORT2 0x400f30b4
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#define CYREG_UDB_P0_U1_PLD_ORT3 0x400f30b6
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#define CYREG_UDB_P0_U1_PLD_MC_CFG_CEN_CONST 0x400f30b8
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#define CYREG_UDB_P0_U1_PLD_MC_CFG_XORFB 0x400f30ba
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#define CYREG_UDB_P0_U1_PLD_MC_SET_RESET 0x400f30bc
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#define CYREG_UDB_P0_U1_PLD_MC_CFG_BYPASS 0x400f30be
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#define CYREG_UDB_P0_U1_CFG0 0x400f30c0
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#define CYREG_UDB_P0_U1_CFG1 0x400f30c1
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#define CYREG_UDB_P0_U1_CFG2 0x400f30c2
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#define CYREG_UDB_P0_U1_CFG3 0x400f30c3
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#define CYREG_UDB_P0_U1_CFG4 0x400f30c4
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#define CYREG_UDB_P0_U1_CFG5 0x400f30c5
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#define CYREG_UDB_P0_U1_CFG6 0x400f30c6
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#define CYREG_UDB_P0_U1_CFG7 0x400f30c7
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#define CYREG_UDB_P0_U1_CFG8 0x400f30c8
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#define CYREG_UDB_P0_U1_CFG9 0x400f30c9
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#define CYREG_UDB_P0_U1_CFG10 0x400f30ca
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#define CYREG_UDB_P0_U1_CFG11 0x400f30cb
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#define CYREG_UDB_P0_U1_CFG12 0x400f30cc
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#define CYREG_UDB_P0_U1_CFG13 0x400f30cd
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#define CYREG_UDB_P0_U1_CFG14 0x400f30ce
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#define CYREG_UDB_P0_U1_CFG15 0x400f30cf
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#define CYREG_UDB_P0_U1_CFG16 0x400f30d0
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#define CYREG_UDB_P0_U1_CFG17 0x400f30d1
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#define CYREG_UDB_P0_U1_CFG18 0x400f30d2
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#define CYREG_UDB_P0_U1_CFG19 0x400f30d3
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#define CYREG_UDB_P0_U1_CFG20 0x400f30d4
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#define CYREG_UDB_P0_U1_CFG21 0x400f30d5
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#define CYREG_UDB_P0_U1_CFG22 0x400f30d6
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#define CYREG_UDB_P0_U1_CFG23 0x400f30d7
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#define CYREG_UDB_P0_U1_CFG24 0x400f30d8
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#define CYREG_UDB_P0_U1_CFG25 0x400f30d9
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#define CYREG_UDB_P0_U1_CFG26 0x400f30da
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#define CYREG_UDB_P0_U1_CFG27 0x400f30db
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#define CYREG_UDB_P0_U1_CFG28 0x400f30dc
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#define CYREG_UDB_P0_U1_CFG29 0x400f30dd
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#define CYREG_UDB_P0_U1_CFG30 0x400f30de
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#define CYREG_UDB_P0_U1_CFG31 0x400f30df
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#define CYREG_UDB_P0_U1_DCFG0 0x400f30e0
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#define CYREG_UDB_P0_U1_DCFG1 0x400f30e2
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#define CYREG_UDB_P0_U1_DCFG2 0x400f30e4
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#define CYREG_UDB_P0_U1_DCFG3 0x400f30e6
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#define CYREG_UDB_P0_U1_DCFG4 0x400f30e8
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#define CYREG_UDB_P0_U1_DCFG5 0x400f30ea
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#define CYREG_UDB_P0_U1_DCFG6 0x400f30ec
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#define CYREG_UDB_P0_U1_DCFG7 0x400f30ee
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#define CYDEV_UDB_P0_ROUTE_BASE 0x400f3100
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#define CYDEV_UDB_P0_ROUTE_SIZE 0x00000100
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#define CYREG_UDB_P0_ROUTE_HC0 0x400f3100
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#define CYFLD_UDB_P_ROUTE_HC_BYTE__OFFSET 0x00000000
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#define CYFLD_UDB_P_ROUTE_HC_BYTE__SIZE 0x00000008
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#define CYREG_UDB_P0_ROUTE_HC1 0x400f3101
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#define CYREG_UDB_P0_ROUTE_HC2 0x400f3102
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#define CYREG_UDB_P0_ROUTE_HC3 0x400f3103
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#define CYREG_UDB_P0_ROUTE_HC4 0x400f3104
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#define CYREG_UDB_P0_ROUTE_HC5 0x400f3105
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#define CYREG_UDB_P0_ROUTE_HC6 0x400f3106
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#define CYREG_UDB_P0_ROUTE_HC7 0x400f3107
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#define CYREG_UDB_P0_ROUTE_HC8 0x400f3108
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#define CYREG_UDB_P0_ROUTE_HC9 0x400f3109
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#define CYREG_UDB_P0_ROUTE_HC10 0x400f310a
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#define CYREG_UDB_P0_ROUTE_HC11 0x400f310b
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#define CYREG_UDB_P0_ROUTE_HC12 0x400f310c
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#define CYREG_UDB_P0_ROUTE_HC13 0x400f310d
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#define CYREG_UDB_P0_ROUTE_HC14 0x400f310e
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#define CYREG_UDB_P0_ROUTE_HC15 0x400f310f
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#define CYREG_UDB_P0_ROUTE_HC16 0x400f3110
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#define CYREG_UDB_P0_ROUTE_HC17 0x400f3111
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#define CYREG_UDB_P0_ROUTE_HC18 0x400f3112
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#define CYREG_UDB_P0_ROUTE_HC19 0x400f3113
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#define CYREG_UDB_P0_ROUTE_HC20 0x400f3114
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#define CYREG_UDB_P0_ROUTE_HC21 0x400f3115
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#define CYREG_UDB_P0_ROUTE_HC22 0x400f3116
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#define CYREG_UDB_P0_ROUTE_HC23 0x400f3117
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#define CYREG_UDB_P0_ROUTE_HC24 0x400f3118
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#define CYREG_UDB_P0_ROUTE_HC25 0x400f3119
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#define CYREG_UDB_P0_ROUTE_HC26 0x400f311a
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#define CYREG_UDB_P0_ROUTE_HC27 0x400f311b
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#define CYREG_UDB_P0_ROUTE_HC28 0x400f311c
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#define CYREG_UDB_P0_ROUTE_HC29 0x400f311d
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#define CYREG_UDB_P0_ROUTE_HC30 0x400f311e
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#define CYREG_UDB_P0_ROUTE_HC31 0x400f311f
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#define CYREG_UDB_P0_ROUTE_HC32 0x400f3120
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#define CYREG_UDB_P0_ROUTE_HC33 0x400f3121
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#define CYREG_UDB_P0_ROUTE_HC34 0x400f3122
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#define CYREG_UDB_P0_ROUTE_HC35 0x400f3123
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#define CYREG_UDB_P0_ROUTE_HC36 0x400f3124
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#define CYREG_UDB_P0_ROUTE_HC37 0x400f3125
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#define CYREG_UDB_P0_ROUTE_HC38 0x400f3126
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#define CYREG_UDB_P0_ROUTE_HC39 0x400f3127
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#define CYREG_UDB_P0_ROUTE_HC40 0x400f3128
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#define CYREG_UDB_P0_ROUTE_HC41 0x400f3129
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#define CYREG_UDB_P0_ROUTE_HC42 0x400f312a
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#define CYREG_UDB_P0_ROUTE_HC43 0x400f312b
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#define CYREG_UDB_P0_ROUTE_HC44 0x400f312c
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#define CYREG_UDB_P0_ROUTE_HC45 0x400f312d
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#define CYREG_UDB_P0_ROUTE_HC46 0x400f312e
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#define CYREG_UDB_P0_ROUTE_HC47 0x400f312f
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#define CYREG_UDB_P0_ROUTE_HC48 0x400f3130
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#define CYREG_UDB_P0_ROUTE_HC49 0x400f3131
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#define CYREG_UDB_P0_ROUTE_HC50 0x400f3132
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#define CYREG_UDB_P0_ROUTE_HC51 0x400f3133
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#define CYREG_UDB_P0_ROUTE_HC52 0x400f3134
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#define CYREG_UDB_P0_ROUTE_HC53 0x400f3135
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#define CYREG_UDB_P0_ROUTE_HC54 0x400f3136
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#define CYREG_UDB_P0_ROUTE_HC55 0x400f3137
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#define CYREG_UDB_P0_ROUTE_HC56 0x400f3138
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#define CYREG_UDB_P0_ROUTE_HC57 0x400f3139
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#define CYREG_UDB_P0_ROUTE_HC58 0x400f313a
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#define CYREG_UDB_P0_ROUTE_HC59 0x400f313b
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#define CYREG_UDB_P0_ROUTE_HC60 0x400f313c
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#define CYREG_UDB_P0_ROUTE_HC61 0x400f313d
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#define CYREG_UDB_P0_ROUTE_HC62 0x400f313e
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#define CYREG_UDB_P0_ROUTE_HC63 0x400f313f
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#define CYREG_UDB_P0_ROUTE_HC64 0x400f3140
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#define CYREG_UDB_P0_ROUTE_HC65 0x400f3141
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#define CYREG_UDB_P0_ROUTE_HC66 0x400f3142
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#define CYREG_UDB_P0_ROUTE_HC67 0x400f3143
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#define CYREG_UDB_P0_ROUTE_HC68 0x400f3144
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#define CYREG_UDB_P0_ROUTE_HC69 0x400f3145
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#define CYREG_UDB_P0_ROUTE_HC70 0x400f3146
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#define CYREG_UDB_P0_ROUTE_HC71 0x400f3147
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#define CYREG_UDB_P0_ROUTE_HC72 0x400f3148
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#define CYREG_UDB_P0_ROUTE_HC73 0x400f3149
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#define CYREG_UDB_P0_ROUTE_HC74 0x400f314a
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#define CYREG_UDB_P0_ROUTE_HC75 0x400f314b
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#define CYREG_UDB_P0_ROUTE_HC76 0x400f314c
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#define CYREG_UDB_P0_ROUTE_HC77 0x400f314d
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#define CYREG_UDB_P0_ROUTE_HC78 0x400f314e
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#define CYREG_UDB_P0_ROUTE_HC79 0x400f314f
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#define CYREG_UDB_P0_ROUTE_HC80 0x400f3150
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#define CYREG_UDB_P0_ROUTE_HC81 0x400f3151
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#define CYREG_UDB_P0_ROUTE_HC82 0x400f3152
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#define CYREG_UDB_P0_ROUTE_HC83 0x400f3153
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#define CYREG_UDB_P0_ROUTE_HC84 0x400f3154
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#define CYREG_UDB_P0_ROUTE_HC85 0x400f3155
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#define CYREG_UDB_P0_ROUTE_HC86 0x400f3156
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#define CYREG_UDB_P0_ROUTE_HC87 0x400f3157
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#define CYREG_UDB_P0_ROUTE_HC88 0x400f3158
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#define CYREG_UDB_P0_ROUTE_HC89 0x400f3159
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#define CYREG_UDB_P0_ROUTE_HC90 0x400f315a
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#define CYREG_UDB_P0_ROUTE_HC91 0x400f315b
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#define CYREG_UDB_P0_ROUTE_HC92 0x400f315c
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#define CYREG_UDB_P0_ROUTE_HC93 0x400f315d
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#define CYREG_UDB_P0_ROUTE_HC94 0x400f315e
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#define CYREG_UDB_P0_ROUTE_HC95 0x400f315f
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#define CYREG_UDB_P0_ROUTE_HC96 0x400f3160
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#define CYREG_UDB_P0_ROUTE_HC97 0x400f3161
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#define CYREG_UDB_P0_ROUTE_HC98 0x400f3162
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#define CYREG_UDB_P0_ROUTE_HC99 0x400f3163
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#define CYREG_UDB_P0_ROUTE_HC100 0x400f3164
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#define CYREG_UDB_P0_ROUTE_HC101 0x400f3165
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#define CYREG_UDB_P0_ROUTE_HC102 0x400f3166
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#define CYREG_UDB_P0_ROUTE_HC103 0x400f3167
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#define CYREG_UDB_P0_ROUTE_HC104 0x400f3168
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#define CYREG_UDB_P0_ROUTE_HC105 0x400f3169
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#define CYREG_UDB_P0_ROUTE_HC106 0x400f316a
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#define CYREG_UDB_P0_ROUTE_HC107 0x400f316b
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#define CYREG_UDB_P0_ROUTE_HC108 0x400f316c
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#define CYREG_UDB_P0_ROUTE_HC109 0x400f316d
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#define CYREG_UDB_P0_ROUTE_HC110 0x400f316e
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#define CYREG_UDB_P0_ROUTE_HC111 0x400f316f
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#define CYREG_UDB_P0_ROUTE_HC112 0x400f3170
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#define CYREG_UDB_P0_ROUTE_HC113 0x400f3171
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#define CYREG_UDB_P0_ROUTE_HC114 0x400f3172
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#define CYREG_UDB_P0_ROUTE_HC115 0x400f3173
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#define CYREG_UDB_P0_ROUTE_HC116 0x400f3174
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#define CYREG_UDB_P0_ROUTE_HC117 0x400f3175
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#define CYREG_UDB_P0_ROUTE_HC118 0x400f3176
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#define CYREG_UDB_P0_ROUTE_HC119 0x400f3177
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#define CYREG_UDB_P0_ROUTE_HC120 0x400f3178
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#define CYREG_UDB_P0_ROUTE_HC121 0x400f3179
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#define CYREG_UDB_P0_ROUTE_HC122 0x400f317a
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#define CYREG_UDB_P0_ROUTE_HC123 0x400f317b
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#define CYREG_UDB_P0_ROUTE_HC124 0x400f317c
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#define CYREG_UDB_P0_ROUTE_HC125 0x400f317d
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#define CYREG_UDB_P0_ROUTE_HC126 0x400f317e
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#define CYREG_UDB_P0_ROUTE_HC127 0x400f317f
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#define CYREG_UDB_P0_ROUTE_HV_L0 0x400f3180
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#define CYFLD_UDB_P_ROUTE_HV_BYTE__OFFSET 0x00000000
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#define CYFLD_UDB_P_ROUTE_HV_BYTE__SIZE 0x00000008
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#define CYREG_UDB_P0_ROUTE_HV_L1 0x400f3181
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#define CYREG_UDB_P0_ROUTE_HV_L2 0x400f3182
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#define CYREG_UDB_P0_ROUTE_HV_L3 0x400f3183
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#define CYREG_UDB_P0_ROUTE_HV_L4 0x400f3184
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#define CYREG_UDB_P0_ROUTE_HV_L5 0x400f3185
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#define CYREG_UDB_P0_ROUTE_HV_L6 0x400f3186
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#define CYREG_UDB_P0_ROUTE_HV_L7 0x400f3187
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#define CYREG_UDB_P0_ROUTE_HV_L8 0x400f3188
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#define CYREG_UDB_P0_ROUTE_HV_L9 0x400f3189
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#define CYREG_UDB_P0_ROUTE_HV_L10 0x400f318a
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#define CYREG_UDB_P0_ROUTE_HV_L11 0x400f318b
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#define CYREG_UDB_P0_ROUTE_HV_L12 0x400f318c
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#define CYREG_UDB_P0_ROUTE_HV_L13 0x400f318d
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#define CYREG_UDB_P0_ROUTE_HV_L14 0x400f318e
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#define CYREG_UDB_P0_ROUTE_HV_L15 0x400f318f
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#define CYREG_UDB_P0_ROUTE_HS0 0x400f3190
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#define CYFLD_UDB_P_ROUTE_HS_BYTE__OFFSET 0x00000000
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#define CYFLD_UDB_P_ROUTE_HS_BYTE__SIZE 0x00000008
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#define CYREG_UDB_P0_ROUTE_HS1 0x400f3191
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#define CYREG_UDB_P0_ROUTE_HS2 0x400f3192
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#define CYREG_UDB_P0_ROUTE_HS3 0x400f3193
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#define CYREG_UDB_P0_ROUTE_HS4 0x400f3194
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#define CYREG_UDB_P0_ROUTE_HS5 0x400f3195
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#define CYREG_UDB_P0_ROUTE_HS6 0x400f3196
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#define CYREG_UDB_P0_ROUTE_HS7 0x400f3197
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#define CYREG_UDB_P0_ROUTE_HS8 0x400f3198
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#define CYREG_UDB_P0_ROUTE_HS9 0x400f3199
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#define CYREG_UDB_P0_ROUTE_HS10 0x400f319a
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#define CYREG_UDB_P0_ROUTE_HS11 0x400f319b
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#define CYREG_UDB_P0_ROUTE_HS12 0x400f319c
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#define CYREG_UDB_P0_ROUTE_HS13 0x400f319d
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#define CYREG_UDB_P0_ROUTE_HS14 0x400f319e
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#define CYREG_UDB_P0_ROUTE_HS15 0x400f319f
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#define CYREG_UDB_P0_ROUTE_HS16 0x400f31a0
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#define CYREG_UDB_P0_ROUTE_HS17 0x400f31a1
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#define CYREG_UDB_P0_ROUTE_HS18 0x400f31a2
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#define CYREG_UDB_P0_ROUTE_HS19 0x400f31a3
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#define CYREG_UDB_P0_ROUTE_HS20 0x400f31a4
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#define CYREG_UDB_P0_ROUTE_HS21 0x400f31a5
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#define CYREG_UDB_P0_ROUTE_HS22 0x400f31a6
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#define CYREG_UDB_P0_ROUTE_HS23 0x400f31a7
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#define CYREG_UDB_P0_ROUTE_HV_R0 0x400f31a8
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#define CYREG_UDB_P0_ROUTE_HV_R1 0x400f31a9
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#define CYREG_UDB_P0_ROUTE_HV_R2 0x400f31aa
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#define CYREG_UDB_P0_ROUTE_HV_R3 0x400f31ab
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#define CYREG_UDB_P0_ROUTE_HV_R4 0x400f31ac
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#define CYREG_UDB_P0_ROUTE_HV_R5 0x400f31ad
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#define CYREG_UDB_P0_ROUTE_HV_R6 0x400f31ae
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#define CYREG_UDB_P0_ROUTE_HV_R7 0x400f31af
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#define CYREG_UDB_P0_ROUTE_HV_R8 0x400f31b0
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#define CYREG_UDB_P0_ROUTE_HV_R9 0x400f31b1
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#define CYREG_UDB_P0_ROUTE_HV_R10 0x400f31b2
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#define CYREG_UDB_P0_ROUTE_HV_R11 0x400f31b3
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#define CYREG_UDB_P0_ROUTE_HV_R12 0x400f31b4
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#define CYREG_UDB_P0_ROUTE_HV_R13 0x400f31b5
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#define CYREG_UDB_P0_ROUTE_HV_R14 0x400f31b6
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#define CYREG_UDB_P0_ROUTE_HV_R15 0x400f31b7
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#define CYREG_UDB_P0_ROUTE_PLD0IN0 0x400f31c0
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#define CYFLD_UDB_P_ROUTE_PI_TOP__OFFSET 0x00000000
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#define CYFLD_UDB_P_ROUTE_PI_TOP__SIZE 0x00000004
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#define CYFLD_UDB_P_ROUTE_PI_BOT__OFFSET 0x00000004
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#define CYFLD_UDB_P_ROUTE_PI_BOT__SIZE 0x00000004
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#define CYREG_UDB_P0_ROUTE_PLD0IN1 0x400f31c2
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#define CYREG_UDB_P0_ROUTE_PLD0IN2 0x400f31c4
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#define CYREG_UDB_P0_ROUTE_PLD1IN0 0x400f31ca
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#define CYREG_UDB_P0_ROUTE_PLD1IN1 0x400f31cc
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#define CYREG_UDB_P0_ROUTE_PLD1IN2 0x400f31ce
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#define CYREG_UDB_P0_ROUTE_DPIN0 0x400f31d0
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#define CYREG_UDB_P0_ROUTE_DPIN1 0x400f31d2
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#define CYFLD_UDB_P_ROUTE_PI_TOP2__OFFSET 0x00000002
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#define CYFLD_UDB_P_ROUTE_PI_TOP2__SIZE 0x00000002
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#define CYFLD_UDB_P_ROUTE_PI_BOT2__OFFSET 0x00000004
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#define CYFLD_UDB_P_ROUTE_PI_BOT2__SIZE 0x00000002
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#define CYREG_UDB_P0_ROUTE_SCIN 0x400f31d6
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#define CYREG_UDB_P0_ROUTE_SCIOIN 0x400f31d8
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#define CYREG_UDB_P0_ROUTE_RCIN 0x400f31de
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#define CYREG_UDB_P0_ROUTE_VS0 0x400f31e0
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#define CYFLD_UDB_P_ROUTE_VS_TOP__OFFSET 0x00000000
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#define CYFLD_UDB_P_ROUTE_VS_TOP__SIZE 0x00000004
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#define CYFLD_UDB_P_ROUTE_VS_BOT__OFFSET 0x00000004
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#define CYFLD_UDB_P_ROUTE_VS_BOT__SIZE 0x00000004
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#define CYREG_UDB_P0_ROUTE_VS1 0x400f31e2
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#define CYREG_UDB_P0_ROUTE_VS2 0x400f31e4
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#define CYREG_UDB_P0_ROUTE_VS3 0x400f31e6
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#define CYREG_UDB_P0_ROUTE_VS4 0x400f31e8
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#define CYREG_UDB_P0_ROUTE_VS5 0x400f31ea
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#define CYREG_UDB_P0_ROUTE_VS6 0x400f31ec
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#define CYREG_UDB_P0_ROUTE_VS7 0x400f31ee
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#define CYDEV_UDB_P1_BASE 0x400f3200
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#define CYDEV_UDB_P1_SIZE 0x00000200
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#define CYDEV_UDB_P1_U0_BASE 0x400f3200
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#define CYDEV_UDB_P1_U0_SIZE 0x00000080
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#define CYREG_UDB_P1_U0_PLD_IT0 0x400f3200
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#define CYREG_UDB_P1_U0_PLD_IT1 0x400f3204
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#define CYREG_UDB_P1_U0_PLD_IT2 0x400f3208
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#define CYREG_UDB_P1_U0_PLD_IT3 0x400f320c
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#define CYREG_UDB_P1_U0_PLD_IT4 0x400f3210
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#define CYREG_UDB_P1_U0_PLD_IT5 0x400f3214
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#define CYREG_UDB_P1_U0_PLD_IT6 0x400f3218
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#define CYREG_UDB_P1_U0_PLD_IT7 0x400f321c
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#define CYREG_UDB_P1_U0_PLD_IT8 0x400f3220
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#define CYREG_UDB_P1_U0_PLD_IT9 0x400f3224
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#define CYREG_UDB_P1_U0_PLD_IT10 0x400f3228
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#define CYREG_UDB_P1_U0_PLD_IT11 0x400f322c
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#define CYREG_UDB_P1_U0_PLD_ORT0 0x400f3230
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#define CYREG_UDB_P1_U0_PLD_ORT1 0x400f3232
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#define CYREG_UDB_P1_U0_PLD_ORT2 0x400f3234
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#define CYREG_UDB_P1_U0_PLD_ORT3 0x400f3236
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#define CYREG_UDB_P1_U0_PLD_MC_CFG_CEN_CONST 0x400f3238
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#define CYREG_UDB_P1_U0_PLD_MC_CFG_XORFB 0x400f323a
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#define CYREG_UDB_P1_U0_PLD_MC_SET_RESET 0x400f323c
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#define CYREG_UDB_P1_U0_PLD_MC_CFG_BYPASS 0x400f323e
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#define CYREG_UDB_P1_U0_CFG0 0x400f3240
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#define CYREG_UDB_P1_U0_CFG1 0x400f3241
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#define CYREG_UDB_P1_U0_CFG2 0x400f3242
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#define CYREG_UDB_P1_U0_CFG3 0x400f3243
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#define CYREG_UDB_P1_U0_CFG4 0x400f3244
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#define CYREG_UDB_P1_U0_CFG5 0x400f3245
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#define CYREG_UDB_P1_U0_CFG6 0x400f3246
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#define CYREG_UDB_P1_U0_CFG7 0x400f3247
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#define CYREG_UDB_P1_U0_CFG8 0x400f3248
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#define CYREG_UDB_P1_U0_CFG9 0x400f3249
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#define CYREG_UDB_P1_U0_CFG10 0x400f324a
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#define CYREG_UDB_P1_U0_CFG11 0x400f324b
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#define CYREG_UDB_P1_U0_CFG12 0x400f324c
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#define CYREG_UDB_P1_U0_CFG13 0x400f324d
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#define CYREG_UDB_P1_U0_CFG14 0x400f324e
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#define CYREG_UDB_P1_U0_CFG15 0x400f324f
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#define CYREG_UDB_P1_U0_CFG16 0x400f3250
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#define CYREG_UDB_P1_U0_CFG17 0x400f3251
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#define CYREG_UDB_P1_U0_CFG18 0x400f3252
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#define CYREG_UDB_P1_U0_CFG19 0x400f3253
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#define CYREG_UDB_P1_U0_CFG20 0x400f3254
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#define CYREG_UDB_P1_U0_CFG21 0x400f3255
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#define CYREG_UDB_P1_U0_CFG22 0x400f3256
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#define CYREG_UDB_P1_U0_CFG23 0x400f3257
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#define CYREG_UDB_P1_U0_CFG24 0x400f3258
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#define CYREG_UDB_P1_U0_CFG25 0x400f3259
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#define CYREG_UDB_P1_U0_CFG26 0x400f325a
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#define CYREG_UDB_P1_U0_CFG27 0x400f325b
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#define CYREG_UDB_P1_U0_CFG28 0x400f325c
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#define CYREG_UDB_P1_U0_CFG29 0x400f325d
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#define CYREG_UDB_P1_U0_CFG30 0x400f325e
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#define CYREG_UDB_P1_U0_CFG31 0x400f325f
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#define CYREG_UDB_P1_U0_DCFG0 0x400f3260
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#define CYREG_UDB_P1_U0_DCFG1 0x400f3262
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#define CYREG_UDB_P1_U0_DCFG2 0x400f3264
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#define CYREG_UDB_P1_U0_DCFG3 0x400f3266
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#define CYREG_UDB_P1_U0_DCFG4 0x400f3268
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#define CYREG_UDB_P1_U0_DCFG5 0x400f326a
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#define CYREG_UDB_P1_U0_DCFG6 0x400f326c
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#define CYREG_UDB_P1_U0_DCFG7 0x400f326e
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#define CYDEV_UDB_P1_U1_BASE 0x400f3280
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#define CYDEV_UDB_P1_U1_SIZE 0x00000080
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#define CYREG_UDB_P1_U1_PLD_IT0 0x400f3280
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#define CYREG_UDB_P1_U1_PLD_IT1 0x400f3284
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#define CYREG_UDB_P1_U1_PLD_IT2 0x400f3288
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#define CYREG_UDB_P1_U1_PLD_IT3 0x400f328c
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#define CYREG_UDB_P1_U1_PLD_IT4 0x400f3290
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#define CYREG_UDB_P1_U1_PLD_IT5 0x400f3294
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#define CYREG_UDB_P1_U1_PLD_IT6 0x400f3298
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#define CYREG_UDB_P1_U1_PLD_IT7 0x400f329c
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#define CYREG_UDB_P1_U1_PLD_IT8 0x400f32a0
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#define CYREG_UDB_P1_U1_PLD_IT9 0x400f32a4
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#define CYREG_UDB_P1_U1_PLD_IT10 0x400f32a8
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#define CYREG_UDB_P1_U1_PLD_IT11 0x400f32ac
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#define CYREG_UDB_P1_U1_PLD_ORT0 0x400f32b0
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#define CYREG_UDB_P1_U1_PLD_ORT1 0x400f32b2
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#define CYREG_UDB_P1_U1_PLD_ORT2 0x400f32b4
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#define CYREG_UDB_P1_U1_PLD_ORT3 0x400f32b6
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#define CYREG_UDB_P1_U1_PLD_MC_CFG_CEN_CONST 0x400f32b8
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#define CYREG_UDB_P1_U1_PLD_MC_CFG_XORFB 0x400f32ba
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#define CYREG_UDB_P1_U1_PLD_MC_SET_RESET 0x400f32bc
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#define CYREG_UDB_P1_U1_PLD_MC_CFG_BYPASS 0x400f32be
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#define CYREG_UDB_P1_U1_CFG0 0x400f32c0
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#define CYREG_UDB_P1_U1_CFG1 0x400f32c1
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#define CYREG_UDB_P1_U1_CFG2 0x400f32c2
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#define CYREG_UDB_P1_U1_CFG3 0x400f32c3
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#define CYREG_UDB_P1_U1_CFG4 0x400f32c4
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#define CYREG_UDB_P1_U1_CFG5 0x400f32c5
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#define CYREG_UDB_P1_U1_CFG6 0x400f32c6
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#define CYREG_UDB_P1_U1_CFG7 0x400f32c7
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#define CYREG_UDB_P1_U1_CFG8 0x400f32c8
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#define CYREG_UDB_P1_U1_CFG9 0x400f32c9
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#define CYREG_UDB_P1_U1_CFG10 0x400f32ca
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#define CYREG_UDB_P1_U1_CFG11 0x400f32cb
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#define CYREG_UDB_P1_U1_CFG12 0x400f32cc
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#define CYREG_UDB_P1_U1_CFG13 0x400f32cd
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#define CYREG_UDB_P1_U1_CFG14 0x400f32ce
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#define CYREG_UDB_P1_U1_CFG15 0x400f32cf
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#define CYREG_UDB_P1_U1_CFG16 0x400f32d0
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#define CYREG_UDB_P1_U1_CFG17 0x400f32d1
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#define CYREG_UDB_P1_U1_CFG18 0x400f32d2
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#define CYREG_UDB_P1_U1_CFG19 0x400f32d3
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#define CYREG_UDB_P1_U1_CFG20 0x400f32d4
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#define CYREG_UDB_P1_U1_CFG21 0x400f32d5
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#define CYREG_UDB_P1_U1_CFG22 0x400f32d6
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#define CYREG_UDB_P1_U1_CFG23 0x400f32d7
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#define CYREG_UDB_P1_U1_CFG24 0x400f32d8
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#define CYREG_UDB_P1_U1_CFG25 0x400f32d9
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#define CYREG_UDB_P1_U1_CFG26 0x400f32da
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#define CYREG_UDB_P1_U1_CFG27 0x400f32db
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#define CYREG_UDB_P1_U1_CFG28 0x400f32dc
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#define CYREG_UDB_P1_U1_CFG29 0x400f32dd
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#define CYREG_UDB_P1_U1_CFG30 0x400f32de
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#define CYREG_UDB_P1_U1_CFG31 0x400f32df
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#define CYREG_UDB_P1_U1_DCFG0 0x400f32e0
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#define CYREG_UDB_P1_U1_DCFG1 0x400f32e2
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#define CYREG_UDB_P1_U1_DCFG2 0x400f32e4
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#define CYREG_UDB_P1_U1_DCFG3 0x400f32e6
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#define CYREG_UDB_P1_U1_DCFG4 0x400f32e8
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#define CYREG_UDB_P1_U1_DCFG5 0x400f32ea
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#define CYREG_UDB_P1_U1_DCFG6 0x400f32ec
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#define CYREG_UDB_P1_U1_DCFG7 0x400f32ee
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#define CYDEV_UDB_P1_ROUTE_BASE 0x400f3300
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#define CYDEV_UDB_P1_ROUTE_SIZE 0x00000100
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#define CYREG_UDB_P1_ROUTE_HC0 0x400f3300
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#define CYREG_UDB_P1_ROUTE_HC1 0x400f3301
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#define CYREG_UDB_P1_ROUTE_HC2 0x400f3302
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#define CYREG_UDB_P1_ROUTE_HC3 0x400f3303
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#define CYREG_UDB_P1_ROUTE_HC4 0x400f3304
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#define CYREG_UDB_P1_ROUTE_HC5 0x400f3305
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#define CYREG_UDB_P1_ROUTE_HC6 0x400f3306
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#define CYREG_UDB_P1_ROUTE_HC7 0x400f3307
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#define CYREG_UDB_P1_ROUTE_HC8 0x400f3308
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#define CYREG_UDB_P1_ROUTE_HC9 0x400f3309
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#define CYREG_UDB_P1_ROUTE_HC10 0x400f330a
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#define CYREG_UDB_P1_ROUTE_HC11 0x400f330b
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#define CYREG_UDB_P1_ROUTE_HC12 0x400f330c
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#define CYREG_UDB_P1_ROUTE_HC13 0x400f330d
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#define CYREG_UDB_P1_ROUTE_HC14 0x400f330e
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#define CYREG_UDB_P1_ROUTE_HC15 0x400f330f
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#define CYREG_UDB_P1_ROUTE_HC16 0x400f3310
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#define CYREG_UDB_P1_ROUTE_HC17 0x400f3311
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#define CYREG_UDB_P1_ROUTE_HC18 0x400f3312
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#define CYREG_UDB_P1_ROUTE_HC19 0x400f3313
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#define CYREG_UDB_P1_ROUTE_HC20 0x400f3314
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#define CYREG_UDB_P1_ROUTE_HC21 0x400f3315
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#define CYREG_UDB_P1_ROUTE_HC22 0x400f3316
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#define CYREG_UDB_P1_ROUTE_HC23 0x400f3317
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#define CYREG_UDB_P1_ROUTE_HC24 0x400f3318
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#define CYREG_UDB_P1_ROUTE_HC25 0x400f3319
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#define CYREG_UDB_P1_ROUTE_HC26 0x400f331a
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#define CYREG_UDB_P1_ROUTE_HC27 0x400f331b
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#define CYREG_UDB_P1_ROUTE_HC28 0x400f331c
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#define CYREG_UDB_P1_ROUTE_HC29 0x400f331d
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#define CYREG_UDB_P1_ROUTE_HC30 0x400f331e
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#define CYREG_UDB_P1_ROUTE_HC31 0x400f331f
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#define CYREG_UDB_P1_ROUTE_HC32 0x400f3320
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#define CYREG_UDB_P1_ROUTE_HC33 0x400f3321
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#define CYREG_UDB_P1_ROUTE_HC34 0x400f3322
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#define CYREG_UDB_P1_ROUTE_HC35 0x400f3323
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#define CYREG_UDB_P1_ROUTE_HC36 0x400f3324
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#define CYREG_UDB_P1_ROUTE_HC37 0x400f3325
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#define CYREG_UDB_P1_ROUTE_HC38 0x400f3326
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#define CYREG_UDB_P1_ROUTE_HC39 0x400f3327
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#define CYREG_UDB_P1_ROUTE_HC40 0x400f3328
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#define CYREG_UDB_P1_ROUTE_HC41 0x400f3329
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#define CYREG_UDB_P1_ROUTE_HC42 0x400f332a
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#define CYREG_UDB_P1_ROUTE_HC43 0x400f332b
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#define CYREG_UDB_P1_ROUTE_HC44 0x400f332c
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#define CYREG_UDB_P1_ROUTE_HC45 0x400f332d
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#define CYREG_UDB_P1_ROUTE_HC46 0x400f332e
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#define CYREG_UDB_P1_ROUTE_HC47 0x400f332f
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#define CYREG_UDB_P1_ROUTE_HC48 0x400f3330
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#define CYREG_UDB_P1_ROUTE_HC49 0x400f3331
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#define CYREG_UDB_P1_ROUTE_HC50 0x400f3332
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#define CYREG_UDB_P1_ROUTE_HC51 0x400f3333
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#define CYREG_UDB_P1_ROUTE_HC52 0x400f3334
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#define CYREG_UDB_P1_ROUTE_HC53 0x400f3335
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#define CYREG_UDB_P1_ROUTE_HC54 0x400f3336
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#define CYREG_UDB_P1_ROUTE_HC55 0x400f3337
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#define CYREG_UDB_P1_ROUTE_HC56 0x400f3338
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#define CYREG_UDB_P1_ROUTE_HC57 0x400f3339
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#define CYREG_UDB_P1_ROUTE_HC58 0x400f333a
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#define CYREG_UDB_P1_ROUTE_HC59 0x400f333b
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#define CYREG_UDB_P1_ROUTE_HC60 0x400f333c
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#define CYREG_UDB_P1_ROUTE_HC61 0x400f333d
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#define CYREG_UDB_P1_ROUTE_HC62 0x400f333e
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#define CYREG_UDB_P1_ROUTE_HC63 0x400f333f
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#define CYREG_UDB_P1_ROUTE_HC64 0x400f3340
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#define CYREG_UDB_P1_ROUTE_HC65 0x400f3341
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#define CYREG_UDB_P1_ROUTE_HC66 0x400f3342
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#define CYREG_UDB_P1_ROUTE_HC67 0x400f3343
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#define CYREG_UDB_P1_ROUTE_HC68 0x400f3344
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#define CYREG_UDB_P1_ROUTE_HC69 0x400f3345
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#define CYREG_UDB_P1_ROUTE_HC70 0x400f3346
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#define CYREG_UDB_P1_ROUTE_HC71 0x400f3347
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#define CYREG_UDB_P1_ROUTE_HC72 0x400f3348
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#define CYREG_UDB_P1_ROUTE_HC73 0x400f3349
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#define CYREG_UDB_P1_ROUTE_HC74 0x400f334a
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#define CYREG_UDB_P1_ROUTE_HC75 0x400f334b
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#define CYREG_UDB_P1_ROUTE_HC76 0x400f334c
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#define CYREG_UDB_P1_ROUTE_HC77 0x400f334d
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#define CYREG_UDB_P1_ROUTE_HC78 0x400f334e
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#define CYREG_UDB_P1_ROUTE_HC79 0x400f334f
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#define CYREG_UDB_P1_ROUTE_HC80 0x400f3350
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#define CYREG_UDB_P1_ROUTE_HC81 0x400f3351
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#define CYREG_UDB_P1_ROUTE_HC82 0x400f3352
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#define CYREG_UDB_P1_ROUTE_HC83 0x400f3353
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#define CYREG_UDB_P1_ROUTE_HC84 0x400f3354
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#define CYREG_UDB_P1_ROUTE_HC85 0x400f3355
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#define CYREG_UDB_P1_ROUTE_HC86 0x400f3356
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#define CYREG_UDB_P1_ROUTE_HC87 0x400f3357
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#define CYREG_UDB_P1_ROUTE_HC88 0x400f3358
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#define CYREG_UDB_P1_ROUTE_HC89 0x400f3359
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#define CYREG_UDB_P1_ROUTE_HC90 0x400f335a
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#define CYREG_UDB_P1_ROUTE_HC91 0x400f335b
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#define CYREG_UDB_P1_ROUTE_HC92 0x400f335c
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#define CYREG_UDB_P1_ROUTE_HC93 0x400f335d
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#define CYREG_UDB_P1_ROUTE_HC94 0x400f335e
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#define CYREG_UDB_P1_ROUTE_HC95 0x400f335f
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#define CYREG_UDB_P1_ROUTE_HC96 0x400f3360
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#define CYREG_UDB_P1_ROUTE_HC97 0x400f3361
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#define CYREG_UDB_P1_ROUTE_HC98 0x400f3362
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#define CYREG_UDB_P1_ROUTE_HC99 0x400f3363
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#define CYREG_UDB_P1_ROUTE_HC100 0x400f3364
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#define CYREG_UDB_P1_ROUTE_HC101 0x400f3365
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#define CYREG_UDB_P1_ROUTE_HC102 0x400f3366
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#define CYREG_UDB_P1_ROUTE_HC103 0x400f3367
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#define CYREG_UDB_P1_ROUTE_HC104 0x400f3368
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#define CYREG_UDB_P1_ROUTE_HC105 0x400f3369
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#define CYREG_UDB_P1_ROUTE_HC106 0x400f336a
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#define CYREG_UDB_P1_ROUTE_HC107 0x400f336b
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#define CYREG_UDB_P1_ROUTE_HC108 0x400f336c
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#define CYREG_UDB_P1_ROUTE_HC109 0x400f336d
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#define CYREG_UDB_P1_ROUTE_HC110 0x400f336e
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#define CYREG_UDB_P1_ROUTE_HC111 0x400f336f
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#define CYREG_UDB_P1_ROUTE_HC112 0x400f3370
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#define CYREG_UDB_P1_ROUTE_HC113 0x400f3371
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#define CYREG_UDB_P1_ROUTE_HC114 0x400f3372
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#define CYREG_UDB_P1_ROUTE_HC115 0x400f3373
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#define CYREG_UDB_P1_ROUTE_HC116 0x400f3374
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#define CYREG_UDB_P1_ROUTE_HC117 0x400f3375
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#define CYREG_UDB_P1_ROUTE_HC118 0x400f3376
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#define CYREG_UDB_P1_ROUTE_HC119 0x400f3377
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#define CYREG_UDB_P1_ROUTE_HC120 0x400f3378
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#define CYREG_UDB_P1_ROUTE_HC121 0x400f3379
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#define CYREG_UDB_P1_ROUTE_HC122 0x400f337a
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#define CYREG_UDB_P1_ROUTE_HC123 0x400f337b
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#define CYREG_UDB_P1_ROUTE_HC124 0x400f337c
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#define CYREG_UDB_P1_ROUTE_HC125 0x400f337d
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#define CYREG_UDB_P1_ROUTE_HC126 0x400f337e
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#define CYREG_UDB_P1_ROUTE_HC127 0x400f337f
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#define CYREG_UDB_P1_ROUTE_HV_L0 0x400f3380
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#define CYREG_UDB_P1_ROUTE_HV_L1 0x400f3381
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#define CYREG_UDB_P1_ROUTE_HV_L2 0x400f3382
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#define CYREG_UDB_P1_ROUTE_HV_L3 0x400f3383
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#define CYREG_UDB_P1_ROUTE_HV_L4 0x400f3384
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#define CYREG_UDB_P1_ROUTE_HV_L5 0x400f3385
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#define CYREG_UDB_P1_ROUTE_HV_L6 0x400f3386
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#define CYREG_UDB_P1_ROUTE_HV_L7 0x400f3387
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#define CYREG_UDB_P1_ROUTE_HV_L8 0x400f3388
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#define CYREG_UDB_P1_ROUTE_HV_L9 0x400f3389
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#define CYREG_UDB_P1_ROUTE_HV_L10 0x400f338a
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#define CYREG_UDB_P1_ROUTE_HV_L11 0x400f338b
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#define CYREG_UDB_P1_ROUTE_HV_L12 0x400f338c
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#define CYREG_UDB_P1_ROUTE_HV_L13 0x400f338d
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#define CYREG_UDB_P1_ROUTE_HV_L14 0x400f338e
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#define CYREG_UDB_P1_ROUTE_HV_L15 0x400f338f
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#define CYREG_UDB_P1_ROUTE_HS0 0x400f3390
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#define CYREG_UDB_P1_ROUTE_HS1 0x400f3391
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#define CYREG_UDB_P1_ROUTE_HS2 0x400f3392
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#define CYREG_UDB_P1_ROUTE_HS3 0x400f3393
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#define CYREG_UDB_P1_ROUTE_HS4 0x400f3394
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#define CYREG_UDB_P1_ROUTE_HS5 0x400f3395
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#define CYREG_UDB_P1_ROUTE_HS6 0x400f3396
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#define CYREG_UDB_P1_ROUTE_HS7 0x400f3397
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#define CYREG_UDB_P1_ROUTE_HS8 0x400f3398
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#define CYREG_UDB_P1_ROUTE_HS9 0x400f3399
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#define CYREG_UDB_P1_ROUTE_HS10 0x400f339a
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#define CYREG_UDB_P1_ROUTE_HS11 0x400f339b
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#define CYREG_UDB_P1_ROUTE_HS12 0x400f339c
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#define CYREG_UDB_P1_ROUTE_HS13 0x400f339d
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#define CYREG_UDB_P1_ROUTE_HS14 0x400f339e
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#define CYREG_UDB_P1_ROUTE_HS15 0x400f339f
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#define CYREG_UDB_P1_ROUTE_HS16 0x400f33a0
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#define CYREG_UDB_P1_ROUTE_HS17 0x400f33a1
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#define CYREG_UDB_P1_ROUTE_HS18 0x400f33a2
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#define CYREG_UDB_P1_ROUTE_HS19 0x400f33a3
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#define CYREG_UDB_P1_ROUTE_HS20 0x400f33a4
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#define CYREG_UDB_P1_ROUTE_HS21 0x400f33a5
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#define CYREG_UDB_P1_ROUTE_HS22 0x400f33a6
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#define CYREG_UDB_P1_ROUTE_HS23 0x400f33a7
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#define CYREG_UDB_P1_ROUTE_HV_R0 0x400f33a8
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#define CYREG_UDB_P1_ROUTE_HV_R1 0x400f33a9
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#define CYREG_UDB_P1_ROUTE_HV_R2 0x400f33aa
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#define CYREG_UDB_P1_ROUTE_HV_R3 0x400f33ab
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#define CYREG_UDB_P1_ROUTE_HV_R4 0x400f33ac
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#define CYREG_UDB_P1_ROUTE_HV_R5 0x400f33ad
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#define CYREG_UDB_P1_ROUTE_HV_R6 0x400f33ae
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#define CYREG_UDB_P1_ROUTE_HV_R7 0x400f33af
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#define CYREG_UDB_P1_ROUTE_HV_R8 0x400f33b0
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#define CYREG_UDB_P1_ROUTE_HV_R9 0x400f33b1
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#define CYREG_UDB_P1_ROUTE_HV_R10 0x400f33b2
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#define CYREG_UDB_P1_ROUTE_HV_R11 0x400f33b3
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#define CYREG_UDB_P1_ROUTE_HV_R12 0x400f33b4
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#define CYREG_UDB_P1_ROUTE_HV_R13 0x400f33b5
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#define CYREG_UDB_P1_ROUTE_HV_R14 0x400f33b6
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#define CYREG_UDB_P1_ROUTE_HV_R15 0x400f33b7
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#define CYREG_UDB_P1_ROUTE_PLD0IN0 0x400f33c0
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#define CYREG_UDB_P1_ROUTE_PLD0IN1 0x400f33c2
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#define CYREG_UDB_P1_ROUTE_PLD0IN2 0x400f33c4
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#define CYREG_UDB_P1_ROUTE_PLD1IN0 0x400f33ca
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#define CYREG_UDB_P1_ROUTE_PLD1IN1 0x400f33cc
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#define CYREG_UDB_P1_ROUTE_PLD1IN2 0x400f33ce
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#define CYREG_UDB_P1_ROUTE_DPIN0 0x400f33d0
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#define CYREG_UDB_P1_ROUTE_DPIN1 0x400f33d2
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#define CYREG_UDB_P1_ROUTE_SCIN 0x400f33d6
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#define CYREG_UDB_P1_ROUTE_SCIOIN 0x400f33d8
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#define CYREG_UDB_P1_ROUTE_RCIN 0x400f33de
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#define CYREG_UDB_P1_ROUTE_VS0 0x400f33e0
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#define CYREG_UDB_P1_ROUTE_VS1 0x400f33e2
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#define CYREG_UDB_P1_ROUTE_VS2 0x400f33e4
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#define CYREG_UDB_P1_ROUTE_VS3 0x400f33e6
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#define CYREG_UDB_P1_ROUTE_VS4 0x400f33e8
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#define CYREG_UDB_P1_ROUTE_VS5 0x400f33ea
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#define CYREG_UDB_P1_ROUTE_VS6 0x400f33ec
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#define CYREG_UDB_P1_ROUTE_VS7 0x400f33ee
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#define CYDEV_UDB_DSI0_BASE 0x400f4000
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#define CYDEV_UDB_DSI0_SIZE 0x00000100
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#define CYREG_UDB_DSI0_HC0 0x400f4000
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#define CYFLD_UDB_DSI_HC_BYTE__OFFSET 0x00000000
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#define CYFLD_UDB_DSI_HC_BYTE__SIZE 0x00000008
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#define CYREG_UDB_DSI0_HC1 0x400f4001
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#define CYREG_UDB_DSI0_HC2 0x400f4002
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#define CYREG_UDB_DSI0_HC3 0x400f4003
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#define CYREG_UDB_DSI0_HC4 0x400f4004
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#define CYREG_UDB_DSI0_HC5 0x400f4005
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#define CYREG_UDB_DSI0_HC6 0x400f4006
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#define CYREG_UDB_DSI0_HC7 0x400f4007
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#define CYREG_UDB_DSI0_HC8 0x400f4008
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#define CYREG_UDB_DSI0_HC9 0x400f4009
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#define CYREG_UDB_DSI0_HC10 0x400f400a
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#define CYREG_UDB_DSI0_HC11 0x400f400b
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#define CYREG_UDB_DSI0_HC12 0x400f400c
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#define CYREG_UDB_DSI0_HC13 0x400f400d
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#define CYREG_UDB_DSI0_HC14 0x400f400e
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#define CYREG_UDB_DSI0_HC15 0x400f400f
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#define CYREG_UDB_DSI0_HC16 0x400f4010
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#define CYREG_UDB_DSI0_HC17 0x400f4011
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#define CYREG_UDB_DSI0_HC18 0x400f4012
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#define CYREG_UDB_DSI0_HC19 0x400f4013
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#define CYREG_UDB_DSI0_HC20 0x400f4014
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#define CYREG_UDB_DSI0_HC21 0x400f4015
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#define CYREG_UDB_DSI0_HC22 0x400f4016
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#define CYREG_UDB_DSI0_HC23 0x400f4017
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#define CYREG_UDB_DSI0_HC24 0x400f4018
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#define CYREG_UDB_DSI0_HC25 0x400f4019
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#define CYREG_UDB_DSI0_HC26 0x400f401a
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#define CYREG_UDB_DSI0_HC27 0x400f401b
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#define CYREG_UDB_DSI0_HC28 0x400f401c
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#define CYREG_UDB_DSI0_HC29 0x400f401d
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#define CYREG_UDB_DSI0_HC30 0x400f401e
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#define CYREG_UDB_DSI0_HC31 0x400f401f
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#define CYREG_UDB_DSI0_HC32 0x400f4020
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#define CYREG_UDB_DSI0_HC33 0x400f4021
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#define CYREG_UDB_DSI0_HC34 0x400f4022
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#define CYREG_UDB_DSI0_HC35 0x400f4023
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#define CYREG_UDB_DSI0_HC36 0x400f4024
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#define CYREG_UDB_DSI0_HC37 0x400f4025
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#define CYREG_UDB_DSI0_HC38 0x400f4026
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#define CYREG_UDB_DSI0_HC39 0x400f4027
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#define CYREG_UDB_DSI0_HC40 0x400f4028
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#define CYREG_UDB_DSI0_HC41 0x400f4029
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#define CYREG_UDB_DSI0_HC42 0x400f402a
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#define CYREG_UDB_DSI0_HC43 0x400f402b
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#define CYREG_UDB_DSI0_HC44 0x400f402c
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#define CYREG_UDB_DSI0_HC45 0x400f402d
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#define CYREG_UDB_DSI0_HC46 0x400f402e
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#define CYREG_UDB_DSI0_HC47 0x400f402f
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#define CYREG_UDB_DSI0_HC48 0x400f4030
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#define CYREG_UDB_DSI0_HC49 0x400f4031
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#define CYREG_UDB_DSI0_HC50 0x400f4032
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#define CYREG_UDB_DSI0_HC51 0x400f4033
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#define CYREG_UDB_DSI0_HC52 0x400f4034
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#define CYREG_UDB_DSI0_HC53 0x400f4035
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#define CYREG_UDB_DSI0_HC54 0x400f4036
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#define CYREG_UDB_DSI0_HC55 0x400f4037
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#define CYREG_UDB_DSI0_HC56 0x400f4038
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#define CYREG_UDB_DSI0_HC57 0x400f4039
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#define CYREG_UDB_DSI0_HC58 0x400f403a
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#define CYREG_UDB_DSI0_HC59 0x400f403b
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#define CYREG_UDB_DSI0_HC60 0x400f403c
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#define CYREG_UDB_DSI0_HC61 0x400f403d
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#define CYREG_UDB_DSI0_HC62 0x400f403e
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#define CYREG_UDB_DSI0_HC63 0x400f403f
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#define CYREG_UDB_DSI0_HC64 0x400f4040
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#define CYREG_UDB_DSI0_HC65 0x400f4041
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#define CYREG_UDB_DSI0_HC66 0x400f4042
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#define CYREG_UDB_DSI0_HC67 0x400f4043
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#define CYREG_UDB_DSI0_HC68 0x400f4044
|
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#define CYREG_UDB_DSI0_HC69 0x400f4045
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#define CYREG_UDB_DSI0_HC70 0x400f4046
|
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#define CYREG_UDB_DSI0_HC71 0x400f4047
|
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#define CYREG_UDB_DSI0_HC72 0x400f4048
|
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#define CYREG_UDB_DSI0_HC73 0x400f4049
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#define CYREG_UDB_DSI0_HC74 0x400f404a
|
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#define CYREG_UDB_DSI0_HC75 0x400f404b
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#define CYREG_UDB_DSI0_HC76 0x400f404c
|
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#define CYREG_UDB_DSI0_HC77 0x400f404d
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#define CYREG_UDB_DSI0_HC78 0x400f404e
|
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#define CYREG_UDB_DSI0_HC79 0x400f404f
|
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#define CYREG_UDB_DSI0_HC80 0x400f4050
|
|
#define CYREG_UDB_DSI0_HC81 0x400f4051
|
|
#define CYREG_UDB_DSI0_HC82 0x400f4052
|
|
#define CYREG_UDB_DSI0_HC83 0x400f4053
|
|
#define CYREG_UDB_DSI0_HC84 0x400f4054
|
|
#define CYREG_UDB_DSI0_HC85 0x400f4055
|
|
#define CYREG_UDB_DSI0_HC86 0x400f4056
|
|
#define CYREG_UDB_DSI0_HC87 0x400f4057
|
|
#define CYREG_UDB_DSI0_HC88 0x400f4058
|
|
#define CYREG_UDB_DSI0_HC89 0x400f4059
|
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#define CYREG_UDB_DSI0_HC90 0x400f405a
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#define CYREG_UDB_DSI0_HC91 0x400f405b
|
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#define CYREG_UDB_DSI0_HC92 0x400f405c
|
|
#define CYREG_UDB_DSI0_HC93 0x400f405d
|
|
#define CYREG_UDB_DSI0_HC94 0x400f405e
|
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#define CYREG_UDB_DSI0_HC95 0x400f405f
|
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#define CYREG_UDB_DSI0_HC96 0x400f4060
|
|
#define CYREG_UDB_DSI0_HC97 0x400f4061
|
|
#define CYREG_UDB_DSI0_HC98 0x400f4062
|
|
#define CYREG_UDB_DSI0_HC99 0x400f4063
|
|
#define CYREG_UDB_DSI0_HC100 0x400f4064
|
|
#define CYREG_UDB_DSI0_HC101 0x400f4065
|
|
#define CYREG_UDB_DSI0_HC102 0x400f4066
|
|
#define CYREG_UDB_DSI0_HC103 0x400f4067
|
|
#define CYREG_UDB_DSI0_HC104 0x400f4068
|
|
#define CYREG_UDB_DSI0_HC105 0x400f4069
|
|
#define CYREG_UDB_DSI0_HC106 0x400f406a
|
|
#define CYREG_UDB_DSI0_HC107 0x400f406b
|
|
#define CYREG_UDB_DSI0_HC108 0x400f406c
|
|
#define CYREG_UDB_DSI0_HC109 0x400f406d
|
|
#define CYREG_UDB_DSI0_HC110 0x400f406e
|
|
#define CYREG_UDB_DSI0_HC111 0x400f406f
|
|
#define CYREG_UDB_DSI0_HC112 0x400f4070
|
|
#define CYREG_UDB_DSI0_HC113 0x400f4071
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#define CYREG_UDB_DSI0_HC114 0x400f4072
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#define CYREG_UDB_DSI0_HC115 0x400f4073
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#define CYREG_UDB_DSI0_HC116 0x400f4074
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#define CYREG_UDB_DSI0_HC117 0x400f4075
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#define CYREG_UDB_DSI0_HC118 0x400f4076
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#define CYREG_UDB_DSI0_HC119 0x400f4077
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#define CYREG_UDB_DSI0_HC120 0x400f4078
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#define CYREG_UDB_DSI0_HC121 0x400f4079
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#define CYREG_UDB_DSI0_HC122 0x400f407a
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#define CYREG_UDB_DSI0_HC123 0x400f407b
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#define CYREG_UDB_DSI0_HC124 0x400f407c
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#define CYREG_UDB_DSI0_HC125 0x400f407d
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#define CYREG_UDB_DSI0_HC126 0x400f407e
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#define CYREG_UDB_DSI0_HC127 0x400f407f
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#define CYREG_UDB_DSI0_HV_L0 0x400f4080
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#define CYFLD_UDB_DSI_HV_BYTE__OFFSET 0x00000000
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#define CYFLD_UDB_DSI_HV_BYTE__SIZE 0x00000008
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#define CYREG_UDB_DSI0_HV_L1 0x400f4081
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#define CYREG_UDB_DSI0_HV_L2 0x400f4082
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#define CYREG_UDB_DSI0_HV_L3 0x400f4083
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#define CYREG_UDB_DSI0_HV_L4 0x400f4084
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#define CYREG_UDB_DSI0_HV_L5 0x400f4085
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#define CYREG_UDB_DSI0_HV_L6 0x400f4086
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#define CYREG_UDB_DSI0_HV_L7 0x400f4087
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#define CYREG_UDB_DSI0_HV_L8 0x400f4088
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#define CYREG_UDB_DSI0_HV_L9 0x400f4089
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#define CYREG_UDB_DSI0_HV_L10 0x400f408a
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#define CYREG_UDB_DSI0_HV_L11 0x400f408b
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#define CYREG_UDB_DSI0_HV_L12 0x400f408c
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#define CYREG_UDB_DSI0_HV_L13 0x400f408d
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#define CYREG_UDB_DSI0_HV_L14 0x400f408e
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#define CYREG_UDB_DSI0_HV_L15 0x400f408f
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#define CYREG_UDB_DSI0_HS0 0x400f4090
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#define CYFLD_UDB_DSI_HS_BYTE__OFFSET 0x00000000
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#define CYFLD_UDB_DSI_HS_BYTE__SIZE 0x00000008
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#define CYREG_UDB_DSI0_HS1 0x400f4091
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#define CYREG_UDB_DSI0_HS2 0x400f4092
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#define CYREG_UDB_DSI0_HS3 0x400f4093
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#define CYREG_UDB_DSI0_HS4 0x400f4094
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#define CYREG_UDB_DSI0_HS5 0x400f4095
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#define CYREG_UDB_DSI0_HS6 0x400f4096
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#define CYREG_UDB_DSI0_HS7 0x400f4097
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#define CYREG_UDB_DSI0_HS8 0x400f4098
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#define CYREG_UDB_DSI0_HS9 0x400f4099
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#define CYREG_UDB_DSI0_HS10 0x400f409a
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#define CYREG_UDB_DSI0_HS11 0x400f409b
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#define CYREG_UDB_DSI0_HS12 0x400f409c
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#define CYREG_UDB_DSI0_HS13 0x400f409d
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#define CYREG_UDB_DSI0_HS14 0x400f409e
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#define CYREG_UDB_DSI0_HS15 0x400f409f
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#define CYREG_UDB_DSI0_HS16 0x400f40a0
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#define CYREG_UDB_DSI0_HS17 0x400f40a1
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#define CYREG_UDB_DSI0_HS18 0x400f40a2
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#define CYREG_UDB_DSI0_HS19 0x400f40a3
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#define CYREG_UDB_DSI0_HS20 0x400f40a4
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#define CYREG_UDB_DSI0_HS21 0x400f40a5
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#define CYREG_UDB_DSI0_HS22 0x400f40a6
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#define CYREG_UDB_DSI0_HS23 0x400f40a7
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#define CYREG_UDB_DSI0_HV_R0 0x400f40a8
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#define CYREG_UDB_DSI0_HV_R1 0x400f40a9
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#define CYREG_UDB_DSI0_HV_R2 0x400f40aa
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#define CYREG_UDB_DSI0_HV_R3 0x400f40ab
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#define CYREG_UDB_DSI0_HV_R4 0x400f40ac
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#define CYREG_UDB_DSI0_HV_R5 0x400f40ad
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#define CYREG_UDB_DSI0_HV_R6 0x400f40ae
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#define CYREG_UDB_DSI0_HV_R7 0x400f40af
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#define CYREG_UDB_DSI0_HV_R8 0x400f40b0
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#define CYREG_UDB_DSI0_HV_R9 0x400f40b1
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#define CYREG_UDB_DSI0_HV_R10 0x400f40b2
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#define CYREG_UDB_DSI0_HV_R11 0x400f40b3
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#define CYREG_UDB_DSI0_HV_R12 0x400f40b4
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#define CYREG_UDB_DSI0_HV_R13 0x400f40b5
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#define CYREG_UDB_DSI0_HV_R14 0x400f40b6
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#define CYREG_UDB_DSI0_HV_R15 0x400f40b7
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#define CYREG_UDB_DSI0_DSIINP0 0x400f40c0
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#define CYFLD_UDB_DSI_PI_TOP__OFFSET 0x00000000
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#define CYFLD_UDB_DSI_PI_TOP__SIZE 0x00000004
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#define CYFLD_UDB_DSI_PI_BOT__OFFSET 0x00000004
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#define CYFLD_UDB_DSI_PI_BOT__SIZE 0x00000004
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#define CYREG_UDB_DSI0_DSIINP1 0x400f40c2
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#define CYREG_UDB_DSI0_DSIINP2 0x400f40c4
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#define CYREG_UDB_DSI0_DSIINP3 0x400f40c6
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#define CYREG_UDB_DSI0_DSIINP4 0x400f40c8
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#define CYREG_UDB_DSI0_DSIINP5 0x400f40ca
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#define CYREG_UDB_DSI0_DSIOUTP0 0x400f40cc
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#define CYREG_UDB_DSI0_DSIOUTP1 0x400f40ce
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#define CYREG_UDB_DSI0_DSIOUTP2 0x400f40d0
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#define CYREG_UDB_DSI0_DSIOUTP3 0x400f40d2
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#define CYREG_UDB_DSI0_DSIOUTT0 0x400f40d4
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#define CYREG_UDB_DSI0_DSIOUTT1 0x400f40d6
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#define CYREG_UDB_DSI0_DSIOUTT2 0x400f40d8
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#define CYREG_UDB_DSI0_DSIOUTT3 0x400f40da
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#define CYREG_UDB_DSI0_DSIOUTT4 0x400f40dc
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#define CYREG_UDB_DSI0_DSIOUTT5 0x400f40de
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#define CYREG_UDB_DSI0_VS0 0x400f40e0
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#define CYFLD_UDB_DSI_VS_TOP__OFFSET 0x00000000
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#define CYFLD_UDB_DSI_VS_TOP__SIZE 0x00000004
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#define CYFLD_UDB_DSI_VS_BOT__OFFSET 0x00000004
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#define CYFLD_UDB_DSI_VS_BOT__SIZE 0x00000004
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#define CYREG_UDB_DSI0_VS1 0x400f40e2
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#define CYREG_UDB_DSI0_VS2 0x400f40e4
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#define CYREG_UDB_DSI0_VS3 0x400f40e6
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#define CYREG_UDB_DSI0_VS4 0x400f40e8
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#define CYREG_UDB_DSI0_VS5 0x400f40ea
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#define CYREG_UDB_DSI0_VS6 0x400f40ec
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#define CYREG_UDB_DSI0_VS7 0x400f40ee
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#define CYDEV_UDB_DSI1_BASE 0x400f4100
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#define CYDEV_UDB_DSI1_SIZE 0x00000100
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#define CYREG_UDB_DSI1_HC0 0x400f4100
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#define CYREG_UDB_DSI1_HC1 0x400f4101
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#define CYREG_UDB_DSI1_HC2 0x400f4102
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#define CYREG_UDB_DSI1_HC3 0x400f4103
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#define CYREG_UDB_DSI1_HC4 0x400f4104
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#define CYREG_UDB_DSI1_HC5 0x400f4105
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#define CYREG_UDB_DSI1_HC6 0x400f4106
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#define CYREG_UDB_DSI1_HC7 0x400f4107
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#define CYREG_UDB_DSI1_HC8 0x400f4108
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#define CYREG_UDB_DSI1_HC9 0x400f4109
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#define CYREG_UDB_DSI1_HC10 0x400f410a
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#define CYREG_UDB_DSI1_HC11 0x400f410b
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#define CYREG_UDB_DSI1_HC12 0x400f410c
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#define CYREG_UDB_DSI1_HC13 0x400f410d
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#define CYREG_UDB_DSI1_HC14 0x400f410e
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#define CYREG_UDB_DSI1_HC15 0x400f410f
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#define CYREG_UDB_DSI1_HC16 0x400f4110
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#define CYREG_UDB_DSI1_HC17 0x400f4111
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#define CYREG_UDB_DSI1_HC18 0x400f4112
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#define CYREG_UDB_DSI1_HC19 0x400f4113
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#define CYREG_UDB_DSI1_HC20 0x400f4114
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#define CYREG_UDB_DSI1_HC21 0x400f4115
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#define CYREG_UDB_DSI1_HC22 0x400f4116
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#define CYREG_UDB_DSI1_HC23 0x400f4117
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#define CYREG_UDB_DSI1_HC24 0x400f4118
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#define CYREG_UDB_DSI1_HC25 0x400f4119
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#define CYREG_UDB_DSI1_HC26 0x400f411a
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#define CYREG_UDB_DSI1_HC27 0x400f411b
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#define CYREG_UDB_DSI1_HC28 0x400f411c
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#define CYREG_UDB_DSI1_HC29 0x400f411d
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#define CYREG_UDB_DSI1_HC30 0x400f411e
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#define CYREG_UDB_DSI1_HC31 0x400f411f
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#define CYREG_UDB_DSI1_HC32 0x400f4120
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#define CYREG_UDB_DSI1_HC33 0x400f4121
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#define CYREG_UDB_DSI1_HC34 0x400f4122
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#define CYREG_UDB_DSI1_HC35 0x400f4123
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#define CYREG_UDB_DSI1_HC36 0x400f4124
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#define CYREG_UDB_DSI1_HC37 0x400f4125
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#define CYREG_UDB_DSI1_HC38 0x400f4126
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#define CYREG_UDB_DSI1_HC39 0x400f4127
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#define CYREG_UDB_DSI1_HC40 0x400f4128
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#define CYREG_UDB_DSI1_HC41 0x400f4129
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#define CYREG_UDB_DSI1_HC42 0x400f412a
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#define CYREG_UDB_DSI1_HC43 0x400f412b
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#define CYREG_UDB_DSI1_HC44 0x400f412c
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#define CYREG_UDB_DSI1_HC45 0x400f412d
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#define CYREG_UDB_DSI1_HC46 0x400f412e
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#define CYREG_UDB_DSI1_HC47 0x400f412f
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#define CYREG_UDB_DSI1_HC48 0x400f4130
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#define CYREG_UDB_DSI1_HC49 0x400f4131
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#define CYREG_UDB_DSI1_HC50 0x400f4132
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#define CYREG_UDB_DSI1_HC51 0x400f4133
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#define CYREG_UDB_DSI1_HC52 0x400f4134
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#define CYREG_UDB_DSI1_HC53 0x400f4135
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#define CYREG_UDB_DSI1_HC54 0x400f4136
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#define CYREG_UDB_DSI1_HC55 0x400f4137
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#define CYREG_UDB_DSI1_HC56 0x400f4138
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#define CYREG_UDB_DSI1_HC57 0x400f4139
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#define CYREG_UDB_DSI1_HC58 0x400f413a
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#define CYREG_UDB_DSI1_HC59 0x400f413b
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#define CYREG_UDB_DSI1_HC60 0x400f413c
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#define CYREG_UDB_DSI1_HC61 0x400f413d
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#define CYREG_UDB_DSI1_HC62 0x400f413e
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#define CYREG_UDB_DSI1_HC63 0x400f413f
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#define CYREG_UDB_DSI1_HC64 0x400f4140
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#define CYREG_UDB_DSI1_HC65 0x400f4141
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#define CYREG_UDB_DSI1_HC66 0x400f4142
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#define CYREG_UDB_DSI1_HC67 0x400f4143
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#define CYREG_UDB_DSI1_HC68 0x400f4144
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#define CYREG_UDB_DSI1_HC69 0x400f4145
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#define CYREG_UDB_DSI1_HC70 0x400f4146
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#define CYREG_UDB_DSI1_HC71 0x400f4147
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#define CYREG_UDB_DSI1_HC72 0x400f4148
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#define CYREG_UDB_DSI1_HC73 0x400f4149
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#define CYREG_UDB_DSI1_HC74 0x400f414a
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#define CYREG_UDB_DSI1_HC75 0x400f414b
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#define CYREG_UDB_DSI1_HC76 0x400f414c
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#define CYREG_UDB_DSI1_HC77 0x400f414d
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#define CYREG_UDB_DSI1_HC78 0x400f414e
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#define CYREG_UDB_DSI1_HC79 0x400f414f
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#define CYREG_UDB_DSI1_HC80 0x400f4150
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#define CYREG_UDB_DSI1_HC81 0x400f4151
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#define CYREG_UDB_DSI1_HC82 0x400f4152
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#define CYREG_UDB_DSI1_HC83 0x400f4153
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#define CYREG_UDB_DSI1_HC84 0x400f4154
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#define CYREG_UDB_DSI1_HC85 0x400f4155
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#define CYREG_UDB_DSI1_HC86 0x400f4156
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#define CYREG_UDB_DSI1_HC87 0x400f4157
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#define CYREG_UDB_DSI1_HC88 0x400f4158
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#define CYREG_UDB_DSI1_HC89 0x400f4159
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#define CYREG_UDB_DSI1_HC90 0x400f415a
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#define CYREG_UDB_DSI1_HC91 0x400f415b
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#define CYREG_UDB_DSI1_HC92 0x400f415c
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#define CYREG_UDB_DSI1_HC93 0x400f415d
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#define CYREG_UDB_DSI1_HC94 0x400f415e
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#define CYREG_UDB_DSI1_HC95 0x400f415f
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#define CYREG_UDB_DSI1_HC96 0x400f4160
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#define CYREG_UDB_DSI1_HC97 0x400f4161
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#define CYREG_UDB_DSI1_HC98 0x400f4162
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#define CYREG_UDB_DSI1_HC99 0x400f4163
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#define CYREG_UDB_DSI1_HC100 0x400f4164
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#define CYREG_UDB_DSI1_HC101 0x400f4165
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#define CYREG_UDB_DSI1_HC102 0x400f4166
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#define CYREG_UDB_DSI1_HC103 0x400f4167
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#define CYREG_UDB_DSI1_HC104 0x400f4168
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#define CYREG_UDB_DSI1_HC105 0x400f4169
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#define CYREG_UDB_DSI1_HC106 0x400f416a
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#define CYREG_UDB_DSI1_HC107 0x400f416b
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#define CYREG_UDB_DSI1_HC108 0x400f416c
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#define CYREG_UDB_DSI1_HC109 0x400f416d
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#define CYREG_UDB_DSI1_HC110 0x400f416e
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#define CYREG_UDB_DSI1_HC111 0x400f416f
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#define CYREG_UDB_DSI1_HC112 0x400f4170
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#define CYREG_UDB_DSI1_HC113 0x400f4171
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#define CYREG_UDB_DSI1_HC114 0x400f4172
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#define CYREG_UDB_DSI1_HC115 0x400f4173
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#define CYREG_UDB_DSI1_HC116 0x400f4174
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#define CYREG_UDB_DSI1_HC117 0x400f4175
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#define CYREG_UDB_DSI1_HC118 0x400f4176
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#define CYREG_UDB_DSI1_HC119 0x400f4177
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#define CYREG_UDB_DSI1_HC120 0x400f4178
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#define CYREG_UDB_DSI1_HC121 0x400f4179
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#define CYREG_UDB_DSI1_HC122 0x400f417a
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#define CYREG_UDB_DSI1_HC123 0x400f417b
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#define CYREG_UDB_DSI1_HC124 0x400f417c
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#define CYREG_UDB_DSI1_HC125 0x400f417d
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#define CYREG_UDB_DSI1_HC126 0x400f417e
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#define CYREG_UDB_DSI1_HC127 0x400f417f
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#define CYREG_UDB_DSI1_HV_L0 0x400f4180
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#define CYREG_UDB_DSI1_HV_L1 0x400f4181
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#define CYREG_UDB_DSI1_HV_L2 0x400f4182
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#define CYREG_UDB_DSI1_HV_L3 0x400f4183
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#define CYREG_UDB_DSI1_HV_L4 0x400f4184
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#define CYREG_UDB_DSI1_HV_L5 0x400f4185
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#define CYREG_UDB_DSI1_HV_L6 0x400f4186
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#define CYREG_UDB_DSI1_HV_L7 0x400f4187
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#define CYREG_UDB_DSI1_HV_L8 0x400f4188
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#define CYREG_UDB_DSI1_HV_L9 0x400f4189
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#define CYREG_UDB_DSI1_HV_L10 0x400f418a
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#define CYREG_UDB_DSI1_HV_L11 0x400f418b
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#define CYREG_UDB_DSI1_HV_L12 0x400f418c
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#define CYREG_UDB_DSI1_HV_L13 0x400f418d
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#define CYREG_UDB_DSI1_HV_L14 0x400f418e
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#define CYREG_UDB_DSI1_HV_L15 0x400f418f
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#define CYREG_UDB_DSI1_HS0 0x400f4190
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#define CYREG_UDB_DSI1_HS1 0x400f4191
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#define CYREG_UDB_DSI1_HS2 0x400f4192
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#define CYREG_UDB_DSI1_HS3 0x400f4193
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#define CYREG_UDB_DSI1_HS4 0x400f4194
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#define CYREG_UDB_DSI1_HS5 0x400f4195
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#define CYREG_UDB_DSI1_HS6 0x400f4196
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#define CYREG_UDB_DSI1_HS7 0x400f4197
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#define CYREG_UDB_DSI1_HS8 0x400f4198
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#define CYREG_UDB_DSI1_HS9 0x400f4199
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#define CYREG_UDB_DSI1_HS10 0x400f419a
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#define CYREG_UDB_DSI1_HS11 0x400f419b
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#define CYREG_UDB_DSI1_HS12 0x400f419c
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#define CYREG_UDB_DSI1_HS13 0x400f419d
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#define CYREG_UDB_DSI1_HS14 0x400f419e
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#define CYREG_UDB_DSI1_HS15 0x400f419f
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#define CYREG_UDB_DSI1_HS16 0x400f41a0
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#define CYREG_UDB_DSI1_HS17 0x400f41a1
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#define CYREG_UDB_DSI1_HS18 0x400f41a2
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#define CYREG_UDB_DSI1_HS19 0x400f41a3
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#define CYREG_UDB_DSI1_HS20 0x400f41a4
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#define CYREG_UDB_DSI1_HS21 0x400f41a5
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#define CYREG_UDB_DSI1_HS22 0x400f41a6
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#define CYREG_UDB_DSI1_HS23 0x400f41a7
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#define CYREG_UDB_DSI1_HV_R0 0x400f41a8
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#define CYREG_UDB_DSI1_HV_R1 0x400f41a9
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#define CYREG_UDB_DSI1_HV_R2 0x400f41aa
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#define CYREG_UDB_DSI1_HV_R3 0x400f41ab
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#define CYREG_UDB_DSI1_HV_R4 0x400f41ac
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#define CYREG_UDB_DSI1_HV_R5 0x400f41ad
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#define CYREG_UDB_DSI1_HV_R6 0x400f41ae
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#define CYREG_UDB_DSI1_HV_R7 0x400f41af
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#define CYREG_UDB_DSI1_HV_R8 0x400f41b0
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#define CYREG_UDB_DSI1_HV_R9 0x400f41b1
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#define CYREG_UDB_DSI1_HV_R10 0x400f41b2
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#define CYREG_UDB_DSI1_HV_R11 0x400f41b3
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#define CYREG_UDB_DSI1_HV_R12 0x400f41b4
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#define CYREG_UDB_DSI1_HV_R13 0x400f41b5
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#define CYREG_UDB_DSI1_HV_R14 0x400f41b6
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#define CYREG_UDB_DSI1_HV_R15 0x400f41b7
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#define CYREG_UDB_DSI1_DSIINP0 0x400f41c0
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#define CYREG_UDB_DSI1_DSIINP1 0x400f41c2
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#define CYREG_UDB_DSI1_DSIINP2 0x400f41c4
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#define CYREG_UDB_DSI1_DSIINP3 0x400f41c6
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#define CYREG_UDB_DSI1_DSIINP4 0x400f41c8
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#define CYREG_UDB_DSI1_DSIINP5 0x400f41ca
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#define CYREG_UDB_DSI1_DSIOUTP0 0x400f41cc
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#define CYREG_UDB_DSI1_DSIOUTP1 0x400f41ce
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#define CYREG_UDB_DSI1_DSIOUTP2 0x400f41d0
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#define CYREG_UDB_DSI1_DSIOUTP3 0x400f41d2
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#define CYREG_UDB_DSI1_DSIOUTT0 0x400f41d4
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#define CYREG_UDB_DSI1_DSIOUTT1 0x400f41d6
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#define CYREG_UDB_DSI1_DSIOUTT2 0x400f41d8
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#define CYREG_UDB_DSI1_DSIOUTT3 0x400f41da
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#define CYREG_UDB_DSI1_DSIOUTT4 0x400f41dc
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#define CYREG_UDB_DSI1_DSIOUTT5 0x400f41de
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#define CYREG_UDB_DSI1_VS0 0x400f41e0
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#define CYREG_UDB_DSI1_VS1 0x400f41e2
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#define CYREG_UDB_DSI1_VS2 0x400f41e4
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#define CYREG_UDB_DSI1_VS3 0x400f41e6
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#define CYREG_UDB_DSI1_VS4 0x400f41e8
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#define CYREG_UDB_DSI1_VS5 0x400f41ea
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#define CYREG_UDB_DSI1_VS6 0x400f41ec
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#define CYREG_UDB_DSI1_VS7 0x400f41ee
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#define CYDEV_UDB_DSI2_BASE 0x400f4200
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#define CYDEV_UDB_DSI2_SIZE 0x00000100
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#define CYREG_UDB_DSI2_HC0 0x400f4200
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#define CYREG_UDB_DSI2_HC1 0x400f4201
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#define CYREG_UDB_DSI2_HC2 0x400f4202
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#define CYREG_UDB_DSI2_HC3 0x400f4203
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#define CYREG_UDB_DSI2_HC4 0x400f4204
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#define CYREG_UDB_DSI2_HC5 0x400f4205
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#define CYREG_UDB_DSI2_HC6 0x400f4206
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#define CYREG_UDB_DSI2_HC7 0x400f4207
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#define CYREG_UDB_DSI2_HC8 0x400f4208
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#define CYREG_UDB_DSI2_HC9 0x400f4209
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#define CYREG_UDB_DSI2_HC10 0x400f420a
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#define CYREG_UDB_DSI2_HC11 0x400f420b
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#define CYREG_UDB_DSI2_HC12 0x400f420c
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#define CYREG_UDB_DSI2_HC13 0x400f420d
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#define CYREG_UDB_DSI2_HC14 0x400f420e
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#define CYREG_UDB_DSI2_HC15 0x400f420f
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#define CYREG_UDB_DSI2_HC16 0x400f4210
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#define CYREG_UDB_DSI2_HC17 0x400f4211
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#define CYREG_UDB_DSI2_HC18 0x400f4212
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#define CYREG_UDB_DSI2_HC19 0x400f4213
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#define CYREG_UDB_DSI2_HC20 0x400f4214
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#define CYREG_UDB_DSI2_HC21 0x400f4215
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#define CYREG_UDB_DSI2_HC22 0x400f4216
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#define CYREG_UDB_DSI2_HC23 0x400f4217
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#define CYREG_UDB_DSI2_HC24 0x400f4218
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#define CYREG_UDB_DSI2_HC25 0x400f4219
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#define CYREG_UDB_DSI2_HC26 0x400f421a
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#define CYREG_UDB_DSI2_HC27 0x400f421b
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#define CYREG_UDB_DSI2_HC28 0x400f421c
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#define CYREG_UDB_DSI2_HC29 0x400f421d
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#define CYREG_UDB_DSI2_HC30 0x400f421e
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#define CYREG_UDB_DSI2_HC31 0x400f421f
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#define CYREG_UDB_DSI2_HC32 0x400f4220
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#define CYREG_UDB_DSI2_HC33 0x400f4221
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#define CYREG_UDB_DSI2_HC34 0x400f4222
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#define CYREG_UDB_DSI2_HC35 0x400f4223
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#define CYREG_UDB_DSI2_HC36 0x400f4224
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#define CYREG_UDB_DSI2_HC37 0x400f4225
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#define CYREG_UDB_DSI2_HC38 0x400f4226
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#define CYREG_UDB_DSI2_HC39 0x400f4227
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#define CYREG_UDB_DSI2_HC40 0x400f4228
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#define CYREG_UDB_DSI2_HC41 0x400f4229
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#define CYREG_UDB_DSI2_HC42 0x400f422a
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#define CYREG_UDB_DSI2_HC43 0x400f422b
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#define CYREG_UDB_DSI2_HC44 0x400f422c
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#define CYREG_UDB_DSI2_HC45 0x400f422d
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#define CYREG_UDB_DSI2_HC46 0x400f422e
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#define CYREG_UDB_DSI2_HC47 0x400f422f
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#define CYREG_UDB_DSI2_HC48 0x400f4230
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#define CYREG_UDB_DSI2_HC49 0x400f4231
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#define CYREG_UDB_DSI2_HC50 0x400f4232
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#define CYREG_UDB_DSI2_HC51 0x400f4233
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#define CYREG_UDB_DSI2_HC52 0x400f4234
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#define CYREG_UDB_DSI2_HC53 0x400f4235
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#define CYREG_UDB_DSI2_HC54 0x400f4236
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#define CYREG_UDB_DSI2_HC55 0x400f4237
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#define CYREG_UDB_DSI2_HC56 0x400f4238
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#define CYREG_UDB_DSI2_HC57 0x400f4239
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#define CYREG_UDB_DSI2_HC58 0x400f423a
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#define CYREG_UDB_DSI2_HC59 0x400f423b
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#define CYREG_UDB_DSI2_HC60 0x400f423c
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#define CYREG_UDB_DSI2_HC61 0x400f423d
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#define CYREG_UDB_DSI2_HC62 0x400f423e
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#define CYREG_UDB_DSI2_HC63 0x400f423f
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#define CYREG_UDB_DSI2_HC64 0x400f4240
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#define CYREG_UDB_DSI2_HC65 0x400f4241
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#define CYREG_UDB_DSI2_HC66 0x400f4242
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#define CYREG_UDB_DSI2_HC67 0x400f4243
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#define CYREG_UDB_DSI2_HC68 0x400f4244
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#define CYREG_UDB_DSI2_HC69 0x400f4245
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#define CYREG_UDB_DSI2_HC70 0x400f4246
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#define CYREG_UDB_DSI2_HC71 0x400f4247
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#define CYREG_UDB_DSI2_HC72 0x400f4248
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#define CYREG_UDB_DSI2_HC73 0x400f4249
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#define CYREG_UDB_DSI2_HC74 0x400f424a
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#define CYREG_UDB_DSI2_HC75 0x400f424b
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#define CYREG_UDB_DSI2_HC76 0x400f424c
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#define CYREG_UDB_DSI2_HC77 0x400f424d
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#define CYREG_UDB_DSI2_HC78 0x400f424e
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#define CYREG_UDB_DSI2_HC79 0x400f424f
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#define CYREG_UDB_DSI2_HC80 0x400f4250
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#define CYREG_UDB_DSI2_HC81 0x400f4251
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#define CYREG_UDB_DSI2_HC82 0x400f4252
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#define CYREG_UDB_DSI2_HC83 0x400f4253
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#define CYREG_UDB_DSI2_HC84 0x400f4254
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#define CYREG_UDB_DSI2_HC85 0x400f4255
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#define CYREG_UDB_DSI2_HC86 0x400f4256
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#define CYREG_UDB_DSI2_HC87 0x400f4257
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#define CYREG_UDB_DSI2_HC88 0x400f4258
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#define CYREG_UDB_DSI2_HC89 0x400f4259
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#define CYREG_UDB_DSI2_HC90 0x400f425a
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#define CYREG_UDB_DSI2_HC91 0x400f425b
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#define CYREG_UDB_DSI2_HC92 0x400f425c
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#define CYREG_UDB_DSI2_HC93 0x400f425d
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#define CYREG_UDB_DSI2_HC94 0x400f425e
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#define CYREG_UDB_DSI2_HC95 0x400f425f
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#define CYREG_UDB_DSI2_HC96 0x400f4260
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#define CYREG_UDB_DSI2_HC97 0x400f4261
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#define CYREG_UDB_DSI2_HC98 0x400f4262
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#define CYREG_UDB_DSI2_HC99 0x400f4263
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#define CYREG_UDB_DSI2_HC100 0x400f4264
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#define CYREG_UDB_DSI2_HC101 0x400f4265
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#define CYREG_UDB_DSI2_HC102 0x400f4266
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#define CYREG_UDB_DSI2_HC103 0x400f4267
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#define CYREG_UDB_DSI2_HC104 0x400f4268
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#define CYREG_UDB_DSI2_HC105 0x400f4269
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#define CYREG_UDB_DSI2_HC106 0x400f426a
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#define CYREG_UDB_DSI2_HC107 0x400f426b
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#define CYREG_UDB_DSI2_HC108 0x400f426c
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#define CYREG_UDB_DSI2_HC109 0x400f426d
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#define CYREG_UDB_DSI2_HC110 0x400f426e
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#define CYREG_UDB_DSI2_HC111 0x400f426f
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#define CYREG_UDB_DSI2_HC112 0x400f4270
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#define CYREG_UDB_DSI2_HC113 0x400f4271
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#define CYREG_UDB_DSI2_HC114 0x400f4272
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#define CYREG_UDB_DSI2_HC115 0x400f4273
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#define CYREG_UDB_DSI2_HC116 0x400f4274
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#define CYREG_UDB_DSI2_HC117 0x400f4275
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#define CYREG_UDB_DSI2_HC118 0x400f4276
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#define CYREG_UDB_DSI2_HC119 0x400f4277
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#define CYREG_UDB_DSI2_HC120 0x400f4278
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#define CYREG_UDB_DSI2_HC121 0x400f4279
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#define CYREG_UDB_DSI2_HC122 0x400f427a
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#define CYREG_UDB_DSI2_HC123 0x400f427b
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#define CYREG_UDB_DSI2_HC124 0x400f427c
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#define CYREG_UDB_DSI2_HC125 0x400f427d
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#define CYREG_UDB_DSI2_HC126 0x400f427e
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#define CYREG_UDB_DSI2_HC127 0x400f427f
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#define CYREG_UDB_DSI2_HV_L0 0x400f4280
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#define CYREG_UDB_DSI2_HV_L1 0x400f4281
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#define CYREG_UDB_DSI2_HV_L2 0x400f4282
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#define CYREG_UDB_DSI2_HV_L3 0x400f4283
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#define CYREG_UDB_DSI2_HV_L4 0x400f4284
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#define CYREG_UDB_DSI2_HV_L5 0x400f4285
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#define CYREG_UDB_DSI2_HV_L6 0x400f4286
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#define CYREG_UDB_DSI2_HV_L7 0x400f4287
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#define CYREG_UDB_DSI2_HV_L8 0x400f4288
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#define CYREG_UDB_DSI2_HV_L9 0x400f4289
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#define CYREG_UDB_DSI2_HV_L10 0x400f428a
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#define CYREG_UDB_DSI2_HV_L11 0x400f428b
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#define CYREG_UDB_DSI2_HV_L12 0x400f428c
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#define CYREG_UDB_DSI2_HV_L13 0x400f428d
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#define CYREG_UDB_DSI2_HV_L14 0x400f428e
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#define CYREG_UDB_DSI2_HV_L15 0x400f428f
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#define CYREG_UDB_DSI2_HS0 0x400f4290
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#define CYREG_UDB_DSI2_HS1 0x400f4291
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#define CYREG_UDB_DSI2_HS2 0x400f4292
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#define CYREG_UDB_DSI2_HS3 0x400f4293
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#define CYREG_UDB_DSI2_HS4 0x400f4294
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#define CYREG_UDB_DSI2_HS5 0x400f4295
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#define CYREG_UDB_DSI2_HS6 0x400f4296
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#define CYREG_UDB_DSI2_HS7 0x400f4297
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#define CYREG_UDB_DSI2_HS8 0x400f4298
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#define CYREG_UDB_DSI2_HS9 0x400f4299
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#define CYREG_UDB_DSI2_HS10 0x400f429a
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#define CYREG_UDB_DSI2_HS11 0x400f429b
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#define CYREG_UDB_DSI2_HS12 0x400f429c
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#define CYREG_UDB_DSI2_HS13 0x400f429d
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#define CYREG_UDB_DSI2_HS14 0x400f429e
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#define CYREG_UDB_DSI2_HS15 0x400f429f
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#define CYREG_UDB_DSI2_HS16 0x400f42a0
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#define CYREG_UDB_DSI2_HS17 0x400f42a1
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#define CYREG_UDB_DSI2_HS18 0x400f42a2
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#define CYREG_UDB_DSI2_HS19 0x400f42a3
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#define CYREG_UDB_DSI2_HS20 0x400f42a4
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#define CYREG_UDB_DSI2_HS21 0x400f42a5
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#define CYREG_UDB_DSI2_HS22 0x400f42a6
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#define CYREG_UDB_DSI2_HS23 0x400f42a7
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#define CYREG_UDB_DSI2_HV_R0 0x400f42a8
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#define CYREG_UDB_DSI2_HV_R1 0x400f42a9
|
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#define CYREG_UDB_DSI2_HV_R2 0x400f42aa
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#define CYREG_UDB_DSI2_HV_R3 0x400f42ab
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#define CYREG_UDB_DSI2_HV_R4 0x400f42ac
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#define CYREG_UDB_DSI2_HV_R5 0x400f42ad
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#define CYREG_UDB_DSI2_HV_R6 0x400f42ae
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#define CYREG_UDB_DSI2_HV_R7 0x400f42af
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#define CYREG_UDB_DSI2_HV_R8 0x400f42b0
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#define CYREG_UDB_DSI2_HV_R9 0x400f42b1
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#define CYREG_UDB_DSI2_HV_R10 0x400f42b2
|
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#define CYREG_UDB_DSI2_HV_R11 0x400f42b3
|
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#define CYREG_UDB_DSI2_HV_R12 0x400f42b4
|
|
#define CYREG_UDB_DSI2_HV_R13 0x400f42b5
|
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#define CYREG_UDB_DSI2_HV_R14 0x400f42b6
|
|
#define CYREG_UDB_DSI2_HV_R15 0x400f42b7
|
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#define CYREG_UDB_DSI2_DSIINP0 0x400f42c0
|
|
#define CYREG_UDB_DSI2_DSIINP1 0x400f42c2
|
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#define CYREG_UDB_DSI2_DSIINP2 0x400f42c4
|
|
#define CYREG_UDB_DSI2_DSIINP3 0x400f42c6
|
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#define CYREG_UDB_DSI2_DSIINP4 0x400f42c8
|
|
#define CYREG_UDB_DSI2_DSIINP5 0x400f42ca
|
|
#define CYREG_UDB_DSI2_DSIOUTP0 0x400f42cc
|
|
#define CYREG_UDB_DSI2_DSIOUTP1 0x400f42ce
|
|
#define CYREG_UDB_DSI2_DSIOUTP2 0x400f42d0
|
|
#define CYREG_UDB_DSI2_DSIOUTP3 0x400f42d2
|
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#define CYREG_UDB_DSI2_DSIOUTT0 0x400f42d4
|
|
#define CYREG_UDB_DSI2_DSIOUTT1 0x400f42d6
|
|
#define CYREG_UDB_DSI2_DSIOUTT2 0x400f42d8
|
|
#define CYREG_UDB_DSI2_DSIOUTT3 0x400f42da
|
|
#define CYREG_UDB_DSI2_DSIOUTT4 0x400f42dc
|
|
#define CYREG_UDB_DSI2_DSIOUTT5 0x400f42de
|
|
#define CYREG_UDB_DSI2_VS0 0x400f42e0
|
|
#define CYREG_UDB_DSI2_VS1 0x400f42e2
|
|
#define CYREG_UDB_DSI2_VS2 0x400f42e4
|
|
#define CYREG_UDB_DSI2_VS3 0x400f42e6
|
|
#define CYREG_UDB_DSI2_VS4 0x400f42e8
|
|
#define CYREG_UDB_DSI2_VS5 0x400f42ea
|
|
#define CYREG_UDB_DSI2_VS6 0x400f42ec
|
|
#define CYREG_UDB_DSI2_VS7 0x400f42ee
|
|
#define CYDEV_UDB_DSI3_BASE 0x400f4300
|
|
#define CYDEV_UDB_DSI3_SIZE 0x00000100
|
|
#define CYREG_UDB_DSI3_HC0 0x400f4300
|
|
#define CYREG_UDB_DSI3_HC1 0x400f4301
|
|
#define CYREG_UDB_DSI3_HC2 0x400f4302
|
|
#define CYREG_UDB_DSI3_HC3 0x400f4303
|
|
#define CYREG_UDB_DSI3_HC4 0x400f4304
|
|
#define CYREG_UDB_DSI3_HC5 0x400f4305
|
|
#define CYREG_UDB_DSI3_HC6 0x400f4306
|
|
#define CYREG_UDB_DSI3_HC7 0x400f4307
|
|
#define CYREG_UDB_DSI3_HC8 0x400f4308
|
|
#define CYREG_UDB_DSI3_HC9 0x400f4309
|
|
#define CYREG_UDB_DSI3_HC10 0x400f430a
|
|
#define CYREG_UDB_DSI3_HC11 0x400f430b
|
|
#define CYREG_UDB_DSI3_HC12 0x400f430c
|
|
#define CYREG_UDB_DSI3_HC13 0x400f430d
|
|
#define CYREG_UDB_DSI3_HC14 0x400f430e
|
|
#define CYREG_UDB_DSI3_HC15 0x400f430f
|
|
#define CYREG_UDB_DSI3_HC16 0x400f4310
|
|
#define CYREG_UDB_DSI3_HC17 0x400f4311
|
|
#define CYREG_UDB_DSI3_HC18 0x400f4312
|
|
#define CYREG_UDB_DSI3_HC19 0x400f4313
|
|
#define CYREG_UDB_DSI3_HC20 0x400f4314
|
|
#define CYREG_UDB_DSI3_HC21 0x400f4315
|
|
#define CYREG_UDB_DSI3_HC22 0x400f4316
|
|
#define CYREG_UDB_DSI3_HC23 0x400f4317
|
|
#define CYREG_UDB_DSI3_HC24 0x400f4318
|
|
#define CYREG_UDB_DSI3_HC25 0x400f4319
|
|
#define CYREG_UDB_DSI3_HC26 0x400f431a
|
|
#define CYREG_UDB_DSI3_HC27 0x400f431b
|
|
#define CYREG_UDB_DSI3_HC28 0x400f431c
|
|
#define CYREG_UDB_DSI3_HC29 0x400f431d
|
|
#define CYREG_UDB_DSI3_HC30 0x400f431e
|
|
#define CYREG_UDB_DSI3_HC31 0x400f431f
|
|
#define CYREG_UDB_DSI3_HC32 0x400f4320
|
|
#define CYREG_UDB_DSI3_HC33 0x400f4321
|
|
#define CYREG_UDB_DSI3_HC34 0x400f4322
|
|
#define CYREG_UDB_DSI3_HC35 0x400f4323
|
|
#define CYREG_UDB_DSI3_HC36 0x400f4324
|
|
#define CYREG_UDB_DSI3_HC37 0x400f4325
|
|
#define CYREG_UDB_DSI3_HC38 0x400f4326
|
|
#define CYREG_UDB_DSI3_HC39 0x400f4327
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#define CYREG_UDB_DSI3_HC40 0x400f4328
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#define CYREG_UDB_DSI3_HC41 0x400f4329
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#define CYREG_UDB_DSI3_HC42 0x400f432a
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#define CYREG_UDB_DSI3_HC43 0x400f432b
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#define CYREG_UDB_DSI3_HC44 0x400f432c
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#define CYREG_UDB_DSI3_HC45 0x400f432d
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#define CYREG_UDB_DSI3_HC46 0x400f432e
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#define CYREG_UDB_DSI3_HC47 0x400f432f
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#define CYREG_UDB_DSI3_HC48 0x400f4330
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#define CYREG_UDB_DSI3_HC49 0x400f4331
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#define CYREG_UDB_DSI3_HC50 0x400f4332
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#define CYREG_UDB_DSI3_HC51 0x400f4333
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#define CYREG_UDB_DSI3_HC52 0x400f4334
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#define CYREG_UDB_DSI3_HC53 0x400f4335
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#define CYREG_UDB_DSI3_HC54 0x400f4336
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#define CYREG_UDB_DSI3_HC55 0x400f4337
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#define CYREG_UDB_DSI3_HC56 0x400f4338
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#define CYREG_UDB_DSI3_HC57 0x400f4339
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#define CYREG_UDB_DSI3_HC58 0x400f433a
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#define CYREG_UDB_DSI3_HC59 0x400f433b
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#define CYREG_UDB_DSI3_HC60 0x400f433c
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#define CYREG_UDB_DSI3_HC61 0x400f433d
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#define CYREG_UDB_DSI3_HC62 0x400f433e
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#define CYREG_UDB_DSI3_HC63 0x400f433f
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#define CYREG_UDB_DSI3_HC64 0x400f4340
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#define CYREG_UDB_DSI3_HC65 0x400f4341
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#define CYREG_UDB_DSI3_HC66 0x400f4342
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#define CYREG_UDB_DSI3_HC67 0x400f4343
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#define CYREG_UDB_DSI3_HC68 0x400f4344
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#define CYREG_UDB_DSI3_HC69 0x400f4345
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#define CYREG_UDB_DSI3_HC70 0x400f4346
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#define CYREG_UDB_DSI3_HC71 0x400f4347
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#define CYREG_UDB_DSI3_HC72 0x400f4348
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#define CYREG_UDB_DSI3_HC73 0x400f4349
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#define CYREG_UDB_DSI3_HC74 0x400f434a
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#define CYREG_UDB_DSI3_HC75 0x400f434b
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#define CYREG_UDB_DSI3_HC76 0x400f434c
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#define CYREG_UDB_DSI3_HC77 0x400f434d
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#define CYREG_UDB_DSI3_HC78 0x400f434e
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#define CYREG_UDB_DSI3_HC79 0x400f434f
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#define CYREG_UDB_DSI3_HC80 0x400f4350
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#define CYREG_UDB_DSI3_HC81 0x400f4351
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#define CYREG_UDB_DSI3_HC82 0x400f4352
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#define CYREG_UDB_DSI3_HC83 0x400f4353
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#define CYREG_UDB_DSI3_HC84 0x400f4354
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#define CYREG_UDB_DSI3_HC85 0x400f4355
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#define CYREG_UDB_DSI3_HC86 0x400f4356
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#define CYREG_UDB_DSI3_HC87 0x400f4357
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#define CYREG_UDB_DSI3_HC88 0x400f4358
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#define CYREG_UDB_DSI3_HC89 0x400f4359
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#define CYREG_UDB_DSI3_HC90 0x400f435a
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#define CYREG_UDB_DSI3_HC91 0x400f435b
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#define CYREG_UDB_DSI3_HC92 0x400f435c
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#define CYREG_UDB_DSI3_HC93 0x400f435d
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#define CYREG_UDB_DSI3_HC94 0x400f435e
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#define CYREG_UDB_DSI3_HC95 0x400f435f
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#define CYREG_UDB_DSI3_HC96 0x400f4360
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#define CYREG_UDB_DSI3_HC97 0x400f4361
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#define CYREG_UDB_DSI3_HC98 0x400f4362
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#define CYREG_UDB_DSI3_HC99 0x400f4363
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#define CYREG_UDB_DSI3_HC100 0x400f4364
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#define CYREG_UDB_DSI3_HC101 0x400f4365
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#define CYREG_UDB_DSI3_HC102 0x400f4366
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#define CYREG_UDB_DSI3_HC103 0x400f4367
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#define CYREG_UDB_DSI3_HC104 0x400f4368
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#define CYREG_UDB_DSI3_HC105 0x400f4369
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#define CYREG_UDB_DSI3_HC106 0x400f436a
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#define CYREG_UDB_DSI3_HC107 0x400f436b
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#define CYREG_UDB_DSI3_HC108 0x400f436c
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#define CYREG_UDB_DSI3_HC109 0x400f436d
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#define CYREG_UDB_DSI3_HC110 0x400f436e
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#define CYREG_UDB_DSI3_HC111 0x400f436f
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#define CYREG_UDB_DSI3_HC112 0x400f4370
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#define CYREG_UDB_DSI3_HC113 0x400f4371
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#define CYREG_UDB_DSI3_HC114 0x400f4372
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#define CYREG_UDB_DSI3_HC115 0x400f4373
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#define CYREG_UDB_DSI3_HC116 0x400f4374
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#define CYREG_UDB_DSI3_HC117 0x400f4375
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#define CYREG_UDB_DSI3_HC118 0x400f4376
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#define CYREG_UDB_DSI3_HC119 0x400f4377
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#define CYREG_UDB_DSI3_HC120 0x400f4378
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#define CYREG_UDB_DSI3_HC121 0x400f4379
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#define CYREG_UDB_DSI3_HC122 0x400f437a
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#define CYREG_UDB_DSI3_HC123 0x400f437b
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#define CYREG_UDB_DSI3_HC124 0x400f437c
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#define CYREG_UDB_DSI3_HC125 0x400f437d
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#define CYREG_UDB_DSI3_HC126 0x400f437e
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#define CYREG_UDB_DSI3_HC127 0x400f437f
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#define CYREG_UDB_DSI3_HV_L0 0x400f4380
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#define CYREG_UDB_DSI3_HV_L1 0x400f4381
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#define CYREG_UDB_DSI3_HV_L2 0x400f4382
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#define CYREG_UDB_DSI3_HV_L3 0x400f4383
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#define CYREG_UDB_DSI3_HV_L4 0x400f4384
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#define CYREG_UDB_DSI3_HV_L5 0x400f4385
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#define CYREG_UDB_DSI3_HV_L6 0x400f4386
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#define CYREG_UDB_DSI3_HV_L7 0x400f4387
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#define CYREG_UDB_DSI3_HV_L8 0x400f4388
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#define CYREG_UDB_DSI3_HV_L9 0x400f4389
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#define CYREG_UDB_DSI3_HV_L10 0x400f438a
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#define CYREG_UDB_DSI3_HV_L11 0x400f438b
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#define CYREG_UDB_DSI3_HV_L12 0x400f438c
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#define CYREG_UDB_DSI3_HV_L13 0x400f438d
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#define CYREG_UDB_DSI3_HV_L14 0x400f438e
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#define CYREG_UDB_DSI3_HV_L15 0x400f438f
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#define CYREG_UDB_DSI3_HS0 0x400f4390
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#define CYREG_UDB_DSI3_HS1 0x400f4391
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#define CYREG_UDB_DSI3_HS2 0x400f4392
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#define CYREG_UDB_DSI3_HS3 0x400f4393
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#define CYREG_UDB_DSI3_HS4 0x400f4394
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#define CYREG_UDB_DSI3_HS5 0x400f4395
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#define CYREG_UDB_DSI3_HS6 0x400f4396
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#define CYREG_UDB_DSI3_HS7 0x400f4397
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#define CYREG_UDB_DSI3_HS8 0x400f4398
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#define CYREG_UDB_DSI3_HS9 0x400f4399
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#define CYREG_UDB_DSI3_HS10 0x400f439a
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#define CYREG_UDB_DSI3_HS11 0x400f439b
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#define CYREG_UDB_DSI3_HS12 0x400f439c
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#define CYREG_UDB_DSI3_HS13 0x400f439d
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#define CYREG_UDB_DSI3_HS14 0x400f439e
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#define CYREG_UDB_DSI3_HS15 0x400f439f
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#define CYREG_UDB_DSI3_HS16 0x400f43a0
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#define CYREG_UDB_DSI3_HS17 0x400f43a1
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#define CYREG_UDB_DSI3_HS18 0x400f43a2
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#define CYREG_UDB_DSI3_HS19 0x400f43a3
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#define CYREG_UDB_DSI3_HS20 0x400f43a4
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#define CYREG_UDB_DSI3_HS21 0x400f43a5
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#define CYREG_UDB_DSI3_HS22 0x400f43a6
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#define CYREG_UDB_DSI3_HS23 0x400f43a7
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#define CYREG_UDB_DSI3_HV_R0 0x400f43a8
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#define CYREG_UDB_DSI3_HV_R1 0x400f43a9
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#define CYREG_UDB_DSI3_HV_R2 0x400f43aa
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#define CYREG_UDB_DSI3_HV_R3 0x400f43ab
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#define CYREG_UDB_DSI3_HV_R4 0x400f43ac
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#define CYREG_UDB_DSI3_HV_R5 0x400f43ad
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#define CYREG_UDB_DSI3_HV_R6 0x400f43ae
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#define CYREG_UDB_DSI3_HV_R7 0x400f43af
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#define CYREG_UDB_DSI3_HV_R8 0x400f43b0
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#define CYREG_UDB_DSI3_HV_R9 0x400f43b1
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#define CYREG_UDB_DSI3_HV_R10 0x400f43b2
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#define CYREG_UDB_DSI3_HV_R11 0x400f43b3
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#define CYREG_UDB_DSI3_HV_R12 0x400f43b4
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#define CYREG_UDB_DSI3_HV_R13 0x400f43b5
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#define CYREG_UDB_DSI3_HV_R14 0x400f43b6
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#define CYREG_UDB_DSI3_HV_R15 0x400f43b7
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#define CYREG_UDB_DSI3_DSIINP0 0x400f43c0
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#define CYREG_UDB_DSI3_DSIINP1 0x400f43c2
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#define CYREG_UDB_DSI3_DSIINP2 0x400f43c4
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#define CYREG_UDB_DSI3_DSIINP3 0x400f43c6
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#define CYREG_UDB_DSI3_DSIINP4 0x400f43c8
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#define CYREG_UDB_DSI3_DSIINP5 0x400f43ca
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#define CYREG_UDB_DSI3_DSIOUTP0 0x400f43cc
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#define CYREG_UDB_DSI3_DSIOUTP1 0x400f43ce
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#define CYREG_UDB_DSI3_DSIOUTP2 0x400f43d0
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#define CYREG_UDB_DSI3_DSIOUTP3 0x400f43d2
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#define CYREG_UDB_DSI3_DSIOUTT0 0x400f43d4
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#define CYREG_UDB_DSI3_DSIOUTT1 0x400f43d6
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#define CYREG_UDB_DSI3_DSIOUTT2 0x400f43d8
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#define CYREG_UDB_DSI3_DSIOUTT3 0x400f43da
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#define CYREG_UDB_DSI3_DSIOUTT4 0x400f43dc
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#define CYREG_UDB_DSI3_DSIOUTT5 0x400f43de
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#define CYREG_UDB_DSI3_VS0 0x400f43e0
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#define CYREG_UDB_DSI3_VS1 0x400f43e2
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#define CYREG_UDB_DSI3_VS2 0x400f43e4
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#define CYREG_UDB_DSI3_VS3 0x400f43e6
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#define CYREG_UDB_DSI3_VS4 0x400f43e8
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#define CYREG_UDB_DSI3_VS5 0x400f43ea
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#define CYREG_UDB_DSI3_VS6 0x400f43ec
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#define CYREG_UDB_DSI3_VS7 0x400f43ee
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#define CYDEV_UDB_PA0_BASE 0x400f5000
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#define CYDEV_UDB_PA0_SIZE 0x00000010
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#define CYREG_UDB_PA0_CFG0 0x400f5000
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#define CYFLD_UDB_PA_CLKIN_EN_SEL__OFFSET 0x00000000
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#define CYFLD_UDB_PA_CLKIN_EN_SEL__SIZE 0x00000002
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#define CYVAL_UDB_PA_CLKIN_EN_SEL_PIN_RC 0x00000000
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#define CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_0 0x00000001
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#define CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_1 0x00000002
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#define CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_2 0x00000003
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#define CYFLD_UDB_PA_CLKIN_EN_MODE__OFFSET 0x00000002
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#define CYFLD_UDB_PA_CLKIN_EN_MODE__SIZE 0x00000002
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#define CYVAL_UDB_PA_CLKIN_EN_MODE_OFF 0x00000000
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#define CYVAL_UDB_PA_CLKIN_EN_MODE_ON 0x00000001
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#define CYVAL_UDB_PA_CLKIN_EN_MODE_POSEDGE 0x00000002
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#define CYVAL_UDB_PA_CLKIN_EN_MODE_LEVEL 0x00000003
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#define CYFLD_UDB_PA_CLKIN_EN_INV__OFFSET 0x00000004
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#define CYFLD_UDB_PA_CLKIN_EN_INV__SIZE 0x00000001
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#define CYVAL_UDB_PA_CLKIN_EN_INV_NOINV 0x00000000
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#define CYVAL_UDB_PA_CLKIN_EN_INV_INV 0x00000001
|
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#define CYFLD_UDB_PA_CLKIN_INV__OFFSET 0x00000005
|
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#define CYFLD_UDB_PA_CLKIN_INV__SIZE 0x00000001
|
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#define CYVAL_UDB_PA_CLKIN_INV_NOINV 0x00000000
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#define CYVAL_UDB_PA_CLKIN_INV_INV 0x00000001
|
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#define CYFLD_UDB_PA_NC__OFFSET 0x00000006
|
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#define CYFLD_UDB_PA_NC__SIZE 0x00000002
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#define CYREG_UDB_PA0_CFG1 0x400f5001
|
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#define CYFLD_UDB_PA_CLKOUT_EN_SEL__OFFSET 0x00000000
|
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#define CYFLD_UDB_PA_CLKOUT_EN_SEL__SIZE 0x00000002
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#define CYVAL_UDB_PA_CLKOUT_EN_SEL_PIN_RC 0x00000000
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#define CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_0 0x00000001
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#define CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_1 0x00000002
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#define CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_2 0x00000003
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#define CYFLD_UDB_PA_CLKOUT_EN_MODE__OFFSET 0x00000002
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#define CYFLD_UDB_PA_CLKOUT_EN_MODE__SIZE 0x00000002
|
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#define CYVAL_UDB_PA_CLKOUT_EN_MODE_OFF 0x00000000
|
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#define CYVAL_UDB_PA_CLKOUT_EN_MODE_ON 0x00000001
|
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#define CYVAL_UDB_PA_CLKOUT_EN_MODE_POSEDGE 0x00000002
|
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#define CYVAL_UDB_PA_CLKOUT_EN_MODE_LEVEL 0x00000003
|
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#define CYFLD_UDB_PA_CLKOUT_EN_INV__OFFSET 0x00000004
|
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#define CYFLD_UDB_PA_CLKOUT_EN_INV__SIZE 0x00000001
|
|
#define CYVAL_UDB_PA_CLKOUT_EN_INV_NOINV 0x00000000
|
|
#define CYVAL_UDB_PA_CLKOUT_EN_INV_INV 0x00000001
|
|
#define CYFLD_UDB_PA_CLKOUT_INV__OFFSET 0x00000005
|
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#define CYFLD_UDB_PA_CLKOUT_INV__SIZE 0x00000001
|
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#define CYVAL_UDB_PA_CLKOUT_INV_NOINV 0x00000000
|
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#define CYVAL_UDB_PA_CLKOUT_INV_INV 0x00000001
|
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#define CYREG_UDB_PA0_CFG2 0x400f5002
|
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#define CYFLD_UDB_PA_CLKIN_SEL__OFFSET 0x00000000
|
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#define CYFLD_UDB_PA_CLKIN_SEL__SIZE 0x00000004
|
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#define CYVAL_UDB_PA_CLKIN_SEL_GCLK0 0x00000000
|
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#define CYVAL_UDB_PA_CLKIN_SEL_GCLK1 0x00000001
|
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#define CYVAL_UDB_PA_CLKIN_SEL_GCLK2 0x00000002
|
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#define CYVAL_UDB_PA_CLKIN_SEL_GCLK3 0x00000003
|
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#define CYVAL_UDB_PA_CLKIN_SEL_GCLK4 0x00000004
|
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#define CYVAL_UDB_PA_CLKIN_SEL_GCLK5 0x00000005
|
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#define CYVAL_UDB_PA_CLKIN_SEL_GCLK6 0x00000006
|
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#define CYVAL_UDB_PA_CLKIN_SEL_GCLK7 0x00000007
|
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#define CYVAL_UDB_PA_CLKIN_SEL_BUS_CLK_APP 0x00000009
|
|
#define CYVAL_UDB_PA_CLKIN_SEL_PIN_RC 0x0000000c
|
|
#define CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_0 0x0000000d
|
|
#define CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_1 0x0000000e
|
|
#define CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_2 0x0000000f
|
|
#define CYFLD_UDB_PA_CLKOUT_SEL__OFFSET 0x00000004
|
|
#define CYFLD_UDB_PA_CLKOUT_SEL__SIZE 0x00000004
|
|
#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK0 0x00000000
|
|
#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK1 0x00000001
|
|
#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK2 0x00000002
|
|
#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK3 0x00000003
|
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#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK4 0x00000004
|
|
#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK5 0x00000005
|
|
#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK6 0x00000006
|
|
#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK7 0x00000007
|
|
#define CYVAL_UDB_PA_CLKOUT_SEL_BUS_CLK_APP 0x00000009
|
|
#define CYVAL_UDB_PA_CLKOUT_SEL_PIN_RC 0x0000000c
|
|
#define CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_0 0x0000000d
|
|
#define CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_1 0x0000000e
|
|
#define CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_2 0x0000000f
|
|
#define CYREG_UDB_PA0_CFG3 0x400f5003
|
|
#define CYFLD_UDB_PA_RES_IN_SEL__OFFSET 0x00000000
|
|
#define CYFLD_UDB_PA_RES_IN_SEL__SIZE 0x00000002
|
|
#define CYVAL_UDB_PA_RES_IN_SEL_PIN_RC 0x00000000
|
|
#define CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_0 0x00000001
|
|
#define CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_1 0x00000002
|
|
#define CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_2 0x00000003
|
|
#define CYFLD_UDB_PA_RES_IN_INV__OFFSET 0x00000002
|
|
#define CYFLD_UDB_PA_RES_IN_INV__SIZE 0x00000001
|
|
#define CYVAL_UDB_PA_RES_IN_INV_NOINV 0x00000000
|
|
#define CYVAL_UDB_PA_RES_IN_INV_INV 0x00000001
|
|
#define CYFLD_UDB_PA_NC0__OFFSET 0x00000003
|
|
#define CYFLD_UDB_PA_NC0__SIZE 0x00000001
|
|
#define CYFLD_UDB_PA_RES_OUT_SEL__OFFSET 0x00000004
|
|
#define CYFLD_UDB_PA_RES_OUT_SEL__SIZE 0x00000002
|
|
#define CYVAL_UDB_PA_RES_OUT_SEL_PIN_RC 0x00000000
|
|
#define CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_0 0x00000001
|
|
#define CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_1 0x00000002
|
|
#define CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_2 0x00000003
|
|
#define CYFLD_UDB_PA_RES_OUT_INV__OFFSET 0x00000006
|
|
#define CYFLD_UDB_PA_RES_OUT_INV__SIZE 0x00000001
|
|
#define CYVAL_UDB_PA_RES_OUT_INV_NOINV 0x00000000
|
|
#define CYVAL_UDB_PA_RES_OUT_INV_INV 0x00000001
|
|
#define CYFLD_UDB_PA_NC7__OFFSET 0x00000007
|
|
#define CYFLD_UDB_PA_NC7__SIZE 0x00000001
|
|
#define CYREG_UDB_PA0_CFG4 0x400f5004
|
|
#define CYFLD_UDB_PA_RES_IN_EN__OFFSET 0x00000000
|
|
#define CYFLD_UDB_PA_RES_IN_EN__SIZE 0x00000001
|
|
#define CYVAL_UDB_PA_RES_IN_EN_DISABLE 0x00000000
|
|
#define CYVAL_UDB_PA_RES_IN_EN_ENABLE 0x00000001
|
|
#define CYFLD_UDB_PA_RES_OUT_EN__OFFSET 0x00000001
|
|
#define CYFLD_UDB_PA_RES_OUT_EN__SIZE 0x00000001
|
|
#define CYVAL_UDB_PA_RES_OUT_EN_DISABLE 0x00000000
|
|
#define CYVAL_UDB_PA_RES_OUT_EN_ENABLE 0x00000001
|
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#define CYFLD_UDB_PA_RES_OE_EN__OFFSET 0x00000002
|
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#define CYFLD_UDB_PA_RES_OE_EN__SIZE 0x00000001
|
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#define CYVAL_UDB_PA_RES_OE_EN_DISABLE 0x00000000
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#define CYVAL_UDB_PA_RES_OE_EN_ENABLE 0x00000001
|
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#define CYFLD_UDB_PA_NC7654__OFFSET 0x00000003
|
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#define CYFLD_UDB_PA_NC7654__SIZE 0x00000005
|
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#define CYREG_UDB_PA0_CFG5 0x400f5005
|
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#define CYFLD_UDB_PA_PIN_SEL__OFFSET 0x00000000
|
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#define CYFLD_UDB_PA_PIN_SEL__SIZE 0x00000001
|
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#define CYVAL_UDB_PA_PIN_SEL_PIN0 0x00000000
|
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#define CYVAL_UDB_PA_PIN_SEL_PIN1 0x00000001
|
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#define CYVAL_UDB_PA_PIN_SEL_PIN2 0x00000002
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#define CYVAL_UDB_PA_PIN_SEL_PIN3 0x00000003
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#define CYVAL_UDB_PA_PIN_SEL_PIN4 0x00000004
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#define CYVAL_UDB_PA_PIN_SEL_PIN5 0x00000005
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#define CYVAL_UDB_PA_PIN_SEL_PIN6 0x00000006
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#define CYVAL_UDB_PA_PIN_SEL_PIN7 0x00000007
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#define CYREG_UDB_PA0_CFG6 0x400f5006
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#define CYFLD_UDB_PA_IN_SYNC0__OFFSET 0x00000000
|
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#define CYFLD_UDB_PA_IN_SYNC0__SIZE 0x00000002
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#define CYVAL_UDB_PA_IN_SYNC0_TRANSPARENT 0x00000000
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#define CYVAL_UDB_PA_IN_SYNC0_SINGLESYNC 0x00000001
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#define CYVAL_UDB_PA_IN_SYNC0_DOUBLESYNC 0x00000002
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#define CYVAL_UDB_PA_IN_SYNC0_RSVD 0x00000003
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#define CYFLD_UDB_PA_IN_SYNC1__OFFSET 0x00000002
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#define CYFLD_UDB_PA_IN_SYNC1__SIZE 0x00000002
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#define CYVAL_UDB_PA_IN_SYNC1_TRANSPARENT 0x00000000
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#define CYVAL_UDB_PA_IN_SYNC1_SINGLESYNC 0x00000001
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#define CYVAL_UDB_PA_IN_SYNC1_DOUBLESYNC 0x00000002
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#define CYVAL_UDB_PA_IN_SYNC1_RSVD 0x00000003
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#define CYFLD_UDB_PA_IN_SYNC2__OFFSET 0x00000004
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#define CYFLD_UDB_PA_IN_SYNC2__SIZE 0x00000002
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#define CYVAL_UDB_PA_IN_SYNC2_TRANSPARENT 0x00000000
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#define CYVAL_UDB_PA_IN_SYNC2_SINGLESYNC 0x00000001
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#define CYVAL_UDB_PA_IN_SYNC2_DOUBLESYNC 0x00000002
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#define CYVAL_UDB_PA_IN_SYNC2_RSVD 0x00000003
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#define CYFLD_UDB_PA_IN_SYNC3__OFFSET 0x00000006
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#define CYFLD_UDB_PA_IN_SYNC3__SIZE 0x00000002
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#define CYVAL_UDB_PA_IN_SYNC3_TRANSPARENT 0x00000000
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#define CYVAL_UDB_PA_IN_SYNC3_SINGLESYNC 0x00000001
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#define CYVAL_UDB_PA_IN_SYNC3_DOUBLESYNC 0x00000002
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#define CYVAL_UDB_PA_IN_SYNC3_RSVD 0x00000003
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#define CYREG_UDB_PA0_CFG7 0x400f5007
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#define CYFLD_UDB_PA_IN_SYNC4__OFFSET 0x00000000
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#define CYFLD_UDB_PA_IN_SYNC4__SIZE 0x00000002
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#define CYVAL_UDB_PA_IN_SYNC4_TRANSPARENT 0x00000000
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#define CYVAL_UDB_PA_IN_SYNC4_SINGLESYNC 0x00000001
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#define CYVAL_UDB_PA_IN_SYNC4_DOUBLESYNC 0x00000002
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#define CYVAL_UDB_PA_IN_SYNC4_RSVD 0x00000003
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#define CYFLD_UDB_PA_IN_SYNC5__OFFSET 0x00000002
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#define CYFLD_UDB_PA_IN_SYNC5__SIZE 0x00000002
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#define CYVAL_UDB_PA_IN_SYNC5_TRANSPARENT 0x00000000
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#define CYVAL_UDB_PA_IN_SYNC5_SINGLESYNC 0x00000001
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#define CYVAL_UDB_PA_IN_SYNC5_DOUBLESYNC 0x00000002
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#define CYVAL_UDB_PA_IN_SYNC5_RSVD 0x00000003
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#define CYFLD_UDB_PA_IN_SYNC6__OFFSET 0x00000004
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#define CYFLD_UDB_PA_IN_SYNC6__SIZE 0x00000002
|
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#define CYVAL_UDB_PA_IN_SYNC6_TRANSPARENT 0x00000000
|
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#define CYVAL_UDB_PA_IN_SYNC6_SINGLESYNC 0x00000001
|
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#define CYVAL_UDB_PA_IN_SYNC6_DOUBLESYNC 0x00000002
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#define CYVAL_UDB_PA_IN_SYNC6_RSVD 0x00000003
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#define CYFLD_UDB_PA_IN_SYNC7__OFFSET 0x00000006
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#define CYFLD_UDB_PA_IN_SYNC7__SIZE 0x00000002
|
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#define CYVAL_UDB_PA_IN_SYNC7_TRANSPARENT 0x00000000
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#define CYVAL_UDB_PA_IN_SYNC7_SINGLESYNC 0x00000001
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#define CYVAL_UDB_PA_IN_SYNC7_DOUBLESYNC 0x00000002
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#define CYVAL_UDB_PA_IN_SYNC7_RSVD 0x00000003
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#define CYREG_UDB_PA0_CFG8 0x400f5008
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#define CYFLD_UDB_PA_OUT_SYNC0__OFFSET 0x00000000
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#define CYFLD_UDB_PA_OUT_SYNC0__SIZE 0x00000002
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#define CYVAL_UDB_PA_OUT_SYNC0_TRANSPARENT 0x00000000
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#define CYVAL_UDB_PA_OUT_SYNC0_SINGLESYNC 0x00000001
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#define CYVAL_UDB_PA_OUT_SYNC0_CLOCK 0x00000002
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#define CYVAL_UDB_PA_OUT_SYNC0_CLOCKINV 0x00000003
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#define CYFLD_UDB_PA_OUT_SYNC1__OFFSET 0x00000002
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#define CYFLD_UDB_PA_OUT_SYNC1__SIZE 0x00000002
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#define CYVAL_UDB_PA_OUT_SYNC1_TRANSPARENT 0x00000000
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#define CYVAL_UDB_PA_OUT_SYNC1_SINGLESYNC 0x00000001
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#define CYVAL_UDB_PA_OUT_SYNC1_CLOCK 0x00000002
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#define CYVAL_UDB_PA_OUT_SYNC1_CLOCKINV 0x00000003
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#define CYFLD_UDB_PA_OUT_SYNC2__OFFSET 0x00000004
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#define CYFLD_UDB_PA_OUT_SYNC2__SIZE 0x00000002
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#define CYVAL_UDB_PA_OUT_SYNC2_TRANSPARENT 0x00000000
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#define CYVAL_UDB_PA_OUT_SYNC2_SINGLESYNC 0x00000001
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#define CYVAL_UDB_PA_OUT_SYNC2_CLOCK 0x00000002
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#define CYVAL_UDB_PA_OUT_SYNC2_CLOCKINV 0x00000003
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#define CYFLD_UDB_PA_OUT_SYNC3__OFFSET 0x00000006
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#define CYFLD_UDB_PA_OUT_SYNC3__SIZE 0x00000002
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#define CYVAL_UDB_PA_OUT_SYNC3_TRANSPARENT 0x00000000
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#define CYVAL_UDB_PA_OUT_SYNC3_SINGLESYNC 0x00000001
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#define CYVAL_UDB_PA_OUT_SYNC3_CLOCK 0x00000002
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#define CYVAL_UDB_PA_OUT_SYNC3_CLOCKINV 0x00000003
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#define CYREG_UDB_PA0_CFG9 0x400f5009
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#define CYFLD_UDB_PA_OUT_SYNC4__OFFSET 0x00000000
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#define CYFLD_UDB_PA_OUT_SYNC4__SIZE 0x00000002
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#define CYVAL_UDB_PA_OUT_SYNC4_TRANSPARENT 0x00000000
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#define CYVAL_UDB_PA_OUT_SYNC4_SINGLESYNC 0x00000001
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#define CYVAL_UDB_PA_OUT_SYNC4_CLOCK 0x00000002
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#define CYVAL_UDB_PA_OUT_SYNC4_CLOCKINV 0x00000003
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#define CYFLD_UDB_PA_OUT_SYNC5__OFFSET 0x00000002
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#define CYFLD_UDB_PA_OUT_SYNC5__SIZE 0x00000002
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#define CYVAL_UDB_PA_OUT_SYNC5_TRANSPARENT 0x00000000
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#define CYVAL_UDB_PA_OUT_SYNC5_SINGLESYNC 0x00000001
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#define CYVAL_UDB_PA_OUT_SYNC5_CLOCK 0x00000002
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#define CYVAL_UDB_PA_OUT_SYNC5_CLOCKINV 0x00000003
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#define CYFLD_UDB_PA_OUT_SYNC6__OFFSET 0x00000004
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#define CYFLD_UDB_PA_OUT_SYNC6__SIZE 0x00000002
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#define CYVAL_UDB_PA_OUT_SYNC6_TRANSPARENT 0x00000000
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#define CYVAL_UDB_PA_OUT_SYNC6_SINGLESYNC 0x00000001
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#define CYVAL_UDB_PA_OUT_SYNC6_CLOCK 0x00000002
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#define CYVAL_UDB_PA_OUT_SYNC6_CLOCKINV 0x00000003
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#define CYFLD_UDB_PA_OUT_SYNC7__OFFSET 0x00000006
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#define CYFLD_UDB_PA_OUT_SYNC7__SIZE 0x00000002
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|
#define CYVAL_UDB_PA_OUT_SYNC7_TRANSPARENT 0x00000000
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#define CYVAL_UDB_PA_OUT_SYNC7_SINGLESYNC 0x00000001
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#define CYVAL_UDB_PA_OUT_SYNC7_CLOCK 0x00000002
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#define CYVAL_UDB_PA_OUT_SYNC7_CLOCKINV 0x00000003
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#define CYREG_UDB_PA0_CFG10 0x400f500a
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#define CYFLD_UDB_PA_DATA_SEL0__OFFSET 0x00000000
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#define CYFLD_UDB_PA_DATA_SEL0__SIZE 0x00000002
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#define CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT0 0x00000000
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#define CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT1 0x00000001
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#define CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT2 0x00000002
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#define CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT3 0x00000003
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#define CYFLD_UDB_PA_DATA_SEL1__OFFSET 0x00000002
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#define CYFLD_UDB_PA_DATA_SEL1__SIZE 0x00000002
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#define CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT0 0x00000000
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#define CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT1 0x00000001
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#define CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT2 0x00000002
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#define CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT3 0x00000003
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#define CYFLD_UDB_PA_DATA_SEL2__OFFSET 0x00000004
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#define CYFLD_UDB_PA_DATA_SEL2__SIZE 0x00000002
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#define CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT0 0x00000000
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#define CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT1 0x00000001
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#define CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT2 0x00000002
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#define CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT3 0x00000003
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#define CYFLD_UDB_PA_DATA_SEL3__OFFSET 0x00000006
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#define CYFLD_UDB_PA_DATA_SEL3__SIZE 0x00000002
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#define CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT0 0x00000000
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#define CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT1 0x00000001
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#define CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT2 0x00000002
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#define CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT3 0x00000003
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#define CYREG_UDB_PA0_CFG11 0x400f500b
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#define CYFLD_UDB_PA_DATA_SEL4__OFFSET 0x00000000
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#define CYFLD_UDB_PA_DATA_SEL4__SIZE 0x00000002
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#define CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT0 0x00000000
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#define CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT1 0x00000001
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#define CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT2 0x00000002
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#define CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT3 0x00000003
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#define CYFLD_UDB_PA_DATA_SEL5__OFFSET 0x00000002
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#define CYFLD_UDB_PA_DATA_SEL5__SIZE 0x00000002
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#define CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT0 0x00000000
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#define CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT1 0x00000001
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#define CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT2 0x00000002
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#define CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT3 0x00000003
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#define CYFLD_UDB_PA_DATA_SEL6__OFFSET 0x00000004
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#define CYFLD_UDB_PA_DATA_SEL6__SIZE 0x00000002
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#define CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT0 0x00000000
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|
#define CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT1 0x00000001
|
|
#define CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT2 0x00000002
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|
#define CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT3 0x00000003
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|
#define CYFLD_UDB_PA_DATA_SEL7__OFFSET 0x00000006
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#define CYFLD_UDB_PA_DATA_SEL7__SIZE 0x00000002
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|
#define CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT0 0x00000000
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#define CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT1 0x00000001
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|
#define CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT2 0x00000002
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|
#define CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT3 0x00000003
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|
#define CYREG_UDB_PA0_CFG12 0x400f500c
|
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#define CYFLD_UDB_PA_OE_SEL0__OFFSET 0x00000000
|
|
#define CYFLD_UDB_PA_OE_SEL0__SIZE 0x00000002
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|
#define CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT0 0x00000000
|
|
#define CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT1 0x00000001
|
|
#define CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT2 0x00000002
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#define CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT3 0x00000003
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#define CYFLD_UDB_PA_OE_SEL1__OFFSET 0x00000002
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#define CYFLD_UDB_PA_OE_SEL1__SIZE 0x00000002
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#define CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT0 0x00000000
|
|
#define CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT1 0x00000001
|
|
#define CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT2 0x00000002
|
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#define CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT3 0x00000003
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#define CYFLD_UDB_PA_OE_SEL2__OFFSET 0x00000004
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#define CYFLD_UDB_PA_OE_SEL2__SIZE 0x00000002
|
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#define CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT0 0x00000000
|
|
#define CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT1 0x00000001
|
|
#define CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT2 0x00000002
|
|
#define CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT3 0x00000003
|
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#define CYFLD_UDB_PA_OE_SEL3__OFFSET 0x00000006
|
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#define CYFLD_UDB_PA_OE_SEL3__SIZE 0x00000002
|
|
#define CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT0 0x00000000
|
|
#define CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT1 0x00000001
|
|
#define CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT2 0x00000002
|
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#define CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT3 0x00000003
|
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#define CYREG_UDB_PA0_CFG13 0x400f500d
|
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#define CYFLD_UDB_PA_OE_SEL4__OFFSET 0x00000000
|
|
#define CYFLD_UDB_PA_OE_SEL4__SIZE 0x00000002
|
|
#define CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT0 0x00000000
|
|
#define CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT1 0x00000001
|
|
#define CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT2 0x00000002
|
|
#define CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT3 0x00000003
|
|
#define CYFLD_UDB_PA_OE_SEL5__OFFSET 0x00000002
|
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#define CYFLD_UDB_PA_OE_SEL5__SIZE 0x00000002
|
|
#define CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT0 0x00000000
|
|
#define CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT1 0x00000001
|
|
#define CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT2 0x00000002
|
|
#define CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT3 0x00000003
|
|
#define CYFLD_UDB_PA_OE_SEL6__OFFSET 0x00000004
|
|
#define CYFLD_UDB_PA_OE_SEL6__SIZE 0x00000002
|
|
#define CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT0 0x00000000
|
|
#define CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT1 0x00000001
|
|
#define CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT2 0x00000002
|
|
#define CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT3 0x00000003
|
|
#define CYFLD_UDB_PA_OE_SEL7__OFFSET 0x00000006
|
|
#define CYFLD_UDB_PA_OE_SEL7__SIZE 0x00000002
|
|
#define CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT0 0x00000000
|
|
#define CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT1 0x00000001
|
|
#define CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT2 0x00000002
|
|
#define CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT3 0x00000003
|
|
#define CYREG_UDB_PA0_CFG14 0x400f500e
|
|
#define CYFLD_UDB_PA_OE_SYNC0__OFFSET 0x00000000
|
|
#define CYFLD_UDB_PA_OE_SYNC0__SIZE 0x00000002
|
|
#define CYVAL_UDB_PA_OE_SYNC0_TRANSPARENT 0x00000000
|
|
#define CYVAL_UDB_PA_OE_SYNC0_SINGLESYNC 0x00000001
|
|
#define CYVAL_UDB_PA_OE_SYNC0_CONSTANT1 0x00000002
|
|
#define CYVAL_UDB_PA_OE_SYNC0_CONSTANT0 0x00000003
|
|
#define CYFLD_UDB_PA_OE_SYNC1__OFFSET 0x00000002
|
|
#define CYFLD_UDB_PA_OE_SYNC1__SIZE 0x00000002
|
|
#define CYVAL_UDB_PA_OE_SYNC1_TRANSPARENT 0x00000000
|
|
#define CYVAL_UDB_PA_OE_SYNC1_SINGLESYNC 0x00000001
|
|
#define CYVAL_UDB_PA_OE_SYNC1_CONSTANT1 0x00000002
|
|
#define CYVAL_UDB_PA_OE_SYNC1_CONSTANT0 0x00000003
|
|
#define CYFLD_UDB_PA_OE_SYNC2__OFFSET 0x00000004
|
|
#define CYFLD_UDB_PA_OE_SYNC2__SIZE 0x00000002
|
|
#define CYVAL_UDB_PA_OE_SYNC2_TRANSPARENT 0x00000000
|
|
#define CYVAL_UDB_PA_OE_SYNC2_SINGLESYNC 0x00000001
|
|
#define CYVAL_UDB_PA_OE_SYNC2_CONSTANT1 0x00000002
|
|
#define CYVAL_UDB_PA_OE_SYNC2_CONSTANT0 0x00000003
|
|
#define CYFLD_UDB_PA_OE_SYNC3__OFFSET 0x00000006
|
|
#define CYFLD_UDB_PA_OE_SYNC3__SIZE 0x00000002
|
|
#define CYVAL_UDB_PA_OE_SYNC3_TRANSPARENT 0x00000000
|
|
#define CYVAL_UDB_PA_OE_SYNC3_SINGLESYNC 0x00000001
|
|
#define CYVAL_UDB_PA_OE_SYNC3_CONSTANT1 0x00000002
|
|
#define CYVAL_UDB_PA_OE_SYNC3_CONSTANT0 0x00000003
|
|
#define CYDEV_UDB_PA1_BASE 0x400f5010
|
|
#define CYDEV_UDB_PA1_SIZE 0x00000010
|
|
#define CYREG_UDB_PA1_CFG0 0x400f5010
|
|
#define CYREG_UDB_PA1_CFG1 0x400f5011
|
|
#define CYREG_UDB_PA1_CFG2 0x400f5012
|
|
#define CYREG_UDB_PA1_CFG3 0x400f5013
|
|
#define CYREG_UDB_PA1_CFG4 0x400f5014
|
|
#define CYREG_UDB_PA1_CFG5 0x400f5015
|
|
#define CYREG_UDB_PA1_CFG6 0x400f5016
|
|
#define CYREG_UDB_PA1_CFG7 0x400f5017
|
|
#define CYREG_UDB_PA1_CFG8 0x400f5018
|
|
#define CYREG_UDB_PA1_CFG9 0x400f5019
|
|
#define CYREG_UDB_PA1_CFG10 0x400f501a
|
|
#define CYREG_UDB_PA1_CFG11 0x400f501b
|
|
#define CYREG_UDB_PA1_CFG12 0x400f501c
|
|
#define CYREG_UDB_PA1_CFG13 0x400f501d
|
|
#define CYREG_UDB_PA1_CFG14 0x400f501e
|
|
#define CYDEV_UDB_PA2_BASE 0x400f5020
|
|
#define CYDEV_UDB_PA2_SIZE 0x00000010
|
|
#define CYREG_UDB_PA2_CFG0 0x400f5020
|
|
#define CYREG_UDB_PA2_CFG1 0x400f5021
|
|
#define CYREG_UDB_PA2_CFG2 0x400f5022
|
|
#define CYREG_UDB_PA2_CFG3 0x400f5023
|
|
#define CYREG_UDB_PA2_CFG4 0x400f5024
|
|
#define CYREG_UDB_PA2_CFG5 0x400f5025
|
|
#define CYREG_UDB_PA2_CFG6 0x400f5026
|
|
#define CYREG_UDB_PA2_CFG7 0x400f5027
|
|
#define CYREG_UDB_PA2_CFG8 0x400f5028
|
|
#define CYREG_UDB_PA2_CFG9 0x400f5029
|
|
#define CYREG_UDB_PA2_CFG10 0x400f502a
|
|
#define CYREG_UDB_PA2_CFG11 0x400f502b
|
|
#define CYREG_UDB_PA2_CFG12 0x400f502c
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#define CYREG_UDB_PA2_CFG13 0x400f502d
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#define CYREG_UDB_PA2_CFG14 0x400f502e
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#define CYDEV_UDB_PA3_BASE 0x400f5030
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#define CYDEV_UDB_PA3_SIZE 0x00000010
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#define CYREG_UDB_PA3_CFG0 0x400f5030
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#define CYREG_UDB_PA3_CFG1 0x400f5031
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#define CYREG_UDB_PA3_CFG2 0x400f5032
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#define CYREG_UDB_PA3_CFG3 0x400f5033
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#define CYREG_UDB_PA3_CFG4 0x400f5034
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#define CYREG_UDB_PA3_CFG5 0x400f5035
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#define CYREG_UDB_PA3_CFG6 0x400f5036
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#define CYREG_UDB_PA3_CFG7 0x400f5037
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#define CYREG_UDB_PA3_CFG8 0x400f5038
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#define CYREG_UDB_PA3_CFG9 0x400f5039
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#define CYREG_UDB_PA3_CFG10 0x400f503a
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#define CYREG_UDB_PA3_CFG11 0x400f503b
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#define CYREG_UDB_PA3_CFG12 0x400f503c
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#define CYREG_UDB_PA3_CFG13 0x400f503d
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#define CYREG_UDB_PA3_CFG14 0x400f503e
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#define CYDEV_UDB_BCTL0_BASE 0x400f6000
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#define CYDEV_UDB_BCTL0_SIZE 0x00001000
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#define CYREG_UDB_BCTL0_DRV 0x400f6000
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#define CYFLD_UDB_BCTL0_DRV__OFFSET 0x00000000
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#define CYFLD_UDB_BCTL0_DRV__SIZE 0x00000008
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#define CYVAL_UDB_BCTL0_DRV_DISABLE 0x00000000
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#define CYVAL_UDB_BCTL0_DRV_ENABLE 0x00000001
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#define CYREG_UDB_BCTL0_MDCLK_EN 0x400f6001
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#define CYFLD_UDB_BCTL0_DCEN__OFFSET 0x00000000
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#define CYFLD_UDB_BCTL0_DCEN__SIZE 0x00000008
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#define CYVAL_UDB_BCTL0_DCEN_DISABLE 0x00000000
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#define CYVAL_UDB_BCTL0_DCEN_ENABLE 0x00000001
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#define CYREG_UDB_BCTL0_MBCLK_EN 0x400f6002
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#define CYFLD_UDB_BCTL0_BCEN__OFFSET 0x00000000
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#define CYFLD_UDB_BCTL0_BCEN__SIZE 0x00000001
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#define CYVAL_UDB_BCTL0_BCEN_DISABLE 0x00000000
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#define CYVAL_UDB_BCTL0_BCEN_ENABLE 0x00000001
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#define CYREG_UDB_BCTL0_BOTSEL_L 0x400f6008
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#define CYFLD_UDB_BCTL0_CLK_SEL0__OFFSET 0x00000000
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#define CYFLD_UDB_BCTL0_CLK_SEL0__SIZE 0x00000002
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#define CYVAL_UDB_BCTL0_CLK_SEL0_EDGE_ENABLES 0x00000000
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#define CYVAL_UDB_BCTL0_CLK_SEL0_PORT_INPUT 0x00000001
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#define CYVAL_UDB_BCTL0_CLK_SEL0_DSI_OUTPUT 0x00000002
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#define CYVAL_UDB_BCTL0_CLK_SEL0_SYNC_DSI_OUTPUT 0x00000003
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#define CYFLD_UDB_BCTL0_CLK_SEL1__OFFSET 0x00000002
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#define CYFLD_UDB_BCTL0_CLK_SEL1__SIZE 0x00000002
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#define CYVAL_UDB_BCTL0_CLK_SEL1_EDGE_ENABLES 0x00000000
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#define CYVAL_UDB_BCTL0_CLK_SEL1_PORT_INPUT 0x00000001
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#define CYVAL_UDB_BCTL0_CLK_SEL1_DSI_OUTPUT 0x00000002
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#define CYVAL_UDB_BCTL0_CLK_SEL1_SYNC_DSI_OUTPUT 0x00000003
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#define CYFLD_UDB_BCTL0_CLK_SEL2__OFFSET 0x00000004
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#define CYFLD_UDB_BCTL0_CLK_SEL2__SIZE 0x00000002
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#define CYVAL_UDB_BCTL0_CLK_SEL2_EDGE_ENABLES 0x00000000
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#define CYVAL_UDB_BCTL0_CLK_SEL2_PORT_INPUT 0x00000001
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#define CYVAL_UDB_BCTL0_CLK_SEL2_DSI_OUTPUT 0x00000002
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#define CYVAL_UDB_BCTL0_CLK_SEL2_SYNC_DSI_OUTPUT 0x00000003
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#define CYFLD_UDB_BCTL0_CLK_SEL3__OFFSET 0x00000006
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#define CYFLD_UDB_BCTL0_CLK_SEL3__SIZE 0x00000002
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#define CYVAL_UDB_BCTL0_CLK_SEL3_EDGE_ENABLES 0x00000000
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#define CYVAL_UDB_BCTL0_CLK_SEL3_PORT_INPUT 0x00000001
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#define CYVAL_UDB_BCTL0_CLK_SEL3_DSI_OUTPUT 0x00000002
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#define CYVAL_UDB_BCTL0_CLK_SEL3_SYNC_DSI_OUTPUT 0x00000003
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#define CYREG_UDB_BCTL0_BOTSEL_U 0x400f6009
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#define CYFLD_UDB_BCTL0_CLK_SEL4__OFFSET 0x00000000
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#define CYFLD_UDB_BCTL0_CLK_SEL4__SIZE 0x00000002
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#define CYVAL_UDB_BCTL0_CLK_SEL4_EDGE_ENABLES 0x00000000
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#define CYVAL_UDB_BCTL0_CLK_SEL4_PORT_INPUT 0x00000001
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#define CYVAL_UDB_BCTL0_CLK_SEL4_DSI_OUTPUT 0x00000002
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#define CYVAL_UDB_BCTL0_CLK_SEL4_SYNC_DSI_OUTPUT 0x00000003
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#define CYFLD_UDB_BCTL0_CLK_SEL5__OFFSET 0x00000002
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#define CYFLD_UDB_BCTL0_CLK_SEL5__SIZE 0x00000002
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#define CYVAL_UDB_BCTL0_CLK_SEL5_EDGE_ENABLES 0x00000000
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#define CYVAL_UDB_BCTL0_CLK_SEL5_PORT_INPUT 0x00000001
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#define CYVAL_UDB_BCTL0_CLK_SEL5_DSI_OUTPUT 0x00000002
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#define CYVAL_UDB_BCTL0_CLK_SEL5_SYNC_DSI_OUTPUT 0x00000003
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#define CYFLD_UDB_BCTL0_CLK_SEL6__OFFSET 0x00000004
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#define CYFLD_UDB_BCTL0_CLK_SEL6__SIZE 0x00000002
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#define CYVAL_UDB_BCTL0_CLK_SEL6_EDGE_ENABLES 0x00000000
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#define CYVAL_UDB_BCTL0_CLK_SEL6_PORT_INPUT 0x00000001
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#define CYVAL_UDB_BCTL0_CLK_SEL6_DSI_OUTPUT 0x00000002
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#define CYVAL_UDB_BCTL0_CLK_SEL6_SYNC_DSI_OUTPUT 0x00000003
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#define CYFLD_UDB_BCTL0_CLK_SEL7__OFFSET 0x00000006
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#define CYFLD_UDB_BCTL0_CLK_SEL7__SIZE 0x00000002
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#define CYVAL_UDB_BCTL0_CLK_SEL7_EDGE_ENABLES 0x00000000
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#define CYVAL_UDB_BCTL0_CLK_SEL7_PORT_INPUT 0x00000001
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#define CYVAL_UDB_BCTL0_CLK_SEL7_DSI_OUTPUT 0x00000002
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#define CYVAL_UDB_BCTL0_CLK_SEL7_SYNC_DSI_OUTPUT 0x00000003
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#define CYREG_UDB_BCTL0_TOPSEL_L 0x400f600a
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#define CYREG_UDB_BCTL0_TOPSEL_U 0x400f600b
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#define CYREG_UDB_BCTL0_QCLK_EN0 0x400f6010
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#define CYFLD_UDB_BCTL0_DCEN_Q__OFFSET 0x00000000
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#define CYFLD_UDB_BCTL0_DCEN_Q__SIZE 0x00000008
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#define CYVAL_UDB_BCTL0_DCEN_Q_DISABLE 0x00000000
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#define CYVAL_UDB_BCTL0_DCEN_Q_ENABLE 0x00000001
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#define CYFLD_UDB_BCTL0_BCEN_Q__OFFSET 0x00000008
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#define CYFLD_UDB_BCTL0_BCEN_Q__SIZE 0x00000001
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#define CYVAL_UDB_BCTL0_BCEN_Q_DISABLE 0x00000000
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#define CYVAL_UDB_BCTL0_BCEN_Q_ENABLE 0x00000001
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#define CYFLD_UDB_BCTL0_GCH_WR_LO__OFFSET 0x00000009
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#define CYFLD_UDB_BCTL0_GCH_WR_LO__SIZE 0x00000001
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#define CYVAL_UDB_BCTL0_GCH_WR_LO_DISABLE 0x00000000
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#define CYVAL_UDB_BCTL0_GCH_WR_LO_ENABLE 0x00000001
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#define CYFLD_UDB_BCTL0_GCH_WR_HI__OFFSET 0x0000000a
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#define CYFLD_UDB_BCTL0_GCH_WR_HI__SIZE 0x00000001
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#define CYVAL_UDB_BCTL0_GCH_WR_HI_DISABLE 0x00000000
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#define CYVAL_UDB_BCTL0_GCH_WR_HI_ENABLE 0x00000001
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#define CYFLD_UDB_BCTL0_DISABLE_ROUTE__OFFSET 0x0000000b
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#define CYFLD_UDB_BCTL0_DISABLE_ROUTE__SIZE 0x00000001
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#define CYVAL_UDB_BCTL0_DISABLE_ROUTE_DISABLE 0x00000000
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#define CYVAL_UDB_BCTL0_DISABLE_ROUTE_ENABLE 0x00000001
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#define CYFLD_UDB_BCTL0_GLB_DSI_WR__OFFSET 0x0000000c
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#define CYFLD_UDB_BCTL0_GLB_DSI_WR__SIZE 0x00000001
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#define CYVAL_UDB_BCTL0_GLB_DSI_WR_DISABLE 0x00000000
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#define CYVAL_UDB_BCTL0_GLB_DSI_WR_ENABLE 0x00000001
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#define CYFLD_UDB_BCTL0_WR_CFG_OPT__OFFSET 0x0000000d
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#define CYFLD_UDB_BCTL0_WR_CFG_OPT__SIZE 0x00000001
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#define CYVAL_UDB_BCTL0_WR_CFG_OPT_FULL_CYCLE_STB 0x00000000
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#define CYVAL_UDB_BCTL0_WR_CFG_OPT_HALF_CYCLE_STB 0x00000001
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#define CYFLD_UDB_BCTL0_NC0__OFFSET 0x0000000e
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#define CYFLD_UDB_BCTL0_NC0__SIZE 0x00000001
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#define CYFLD_UDB_BCTL0_SLEEP_TEST__OFFSET 0x0000000f
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#define CYFLD_UDB_BCTL0_SLEEP_TEST__SIZE 0x00000001
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#define CYVAL_UDB_BCTL0_SLEEP_TEST_DISABLE 0x00000000
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#define CYVAL_UDB_BCTL0_SLEEP_TEST_ENABLE 0x00000001
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#define CYREG_UDB_BCTL0_QCLK_EN1 0x400f6012
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#define CYREG_UDB_BCTL0_QCLK_EN2 0x400f6014
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#define CYREG_UDB_BCTL0_QCLK_EN3 0x400f6016
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#define CYDEV_UDB_UDBIF_BASE 0x400f7000
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#define CYDEV_UDB_UDBIF_SIZE 0x00001000
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#define CYREG_UDB_UDBIF_BANK_CTL 0x400f7000
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#define CYFLD_UDB_UDBIF_DIS_COR__OFFSET 0x00000000
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#define CYFLD_UDB_UDBIF_DIS_COR__SIZE 0x00000001
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#define CYVAL_UDB_UDBIF_DIS_COR_NORMAL 0x00000000
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#define CYVAL_UDB_UDBIF_DIS_COR_DISABLE 0x00000001
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#define CYFLD_UDB_UDBIF_ROUTE_EN__OFFSET 0x00000001
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#define CYFLD_UDB_UDBIF_ROUTE_EN__SIZE 0x00000001
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#define CYVAL_UDB_UDBIF_ROUTE_EN_DISABLE 0x00000000
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#define CYVAL_UDB_UDBIF_ROUTE_EN_ENABLE 0x00000001
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#define CYFLD_UDB_UDBIF_BANK_EN__OFFSET 0x00000002
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#define CYFLD_UDB_UDBIF_BANK_EN__SIZE 0x00000001
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#define CYVAL_UDB_UDBIF_BANK_EN_DISABLE 0x00000000
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#define CYVAL_UDB_UDBIF_BANK_EN_ENABLE 0x00000001
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#define CYFLD_UDB_UDBIF_LOCK__OFFSET 0x00000003
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#define CYFLD_UDB_UDBIF_LOCK__SIZE 0x00000001
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#define CYVAL_UDB_UDBIF_LOCK_MUTABLE 0x00000000
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#define CYVAL_UDB_UDBIF_LOCK_LOCKED 0x00000001
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#define CYFLD_UDB_UDBIF_PIPE__OFFSET 0x00000004
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#define CYFLD_UDB_UDBIF_PIPE__SIZE 0x00000001
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#define CYVAL_UDB_UDBIF_PIPE_BYPASS 0x00000000
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#define CYVAL_UDB_UDBIF_PIPE_PIPELINED 0x00000001
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#define CYFLD_UDB_UDBIF_GLBL_WR__OFFSET 0x00000007
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#define CYFLD_UDB_UDBIF_GLBL_WR__SIZE 0x00000001
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#define CYVAL_UDB_UDBIF_GLBL_WR_DISABLE 0x00000000
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#define CYVAL_UDB_UDBIF_GLBL_WR_ENABLE 0x00000001
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#define CYREG_UDB_UDBIF_WAIT_CFG 0x400f7001
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#define CYFLD_UDB_UDBIF_RD_CFG_WAIT__OFFSET 0x00000000
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#define CYFLD_UDB_UDBIF_RD_CFG_WAIT__SIZE 0x00000002
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#define CYVAL_UDB_UDBIF_RD_CFG_WAIT_FIVE_WAITS 0x00000000
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#define CYVAL_UDB_UDBIF_RD_CFG_WAIT_FOUR_WAITS 0x00000001
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#define CYVAL_UDB_UDBIF_RD_CFG_WAIT_THREE_WAITS 0x00000002
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#define CYVAL_UDB_UDBIF_RD_CFG_WAIT_ONE_WAIT 0x00000003
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#define CYFLD_UDB_UDBIF_WR_CFG_WAIT__OFFSET 0x00000002
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#define CYFLD_UDB_UDBIF_WR_CFG_WAIT__SIZE 0x00000002
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#define CYVAL_UDB_UDBIF_WR_CFG_WAIT_ONE_WAIT 0x00000000
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#define CYVAL_UDB_UDBIF_WR_CFG_WAIT_TWO_WAITS 0x00000001
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#define CYVAL_UDB_UDBIF_WR_CFG_WAIT_THREE_WAITS 0x00000002
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#define CYVAL_UDB_UDBIF_WR_CFG_WAIT_ZERO_WAITS 0x00000003
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#define CYFLD_UDB_UDBIF_RD_WRK_WAIT__OFFSET 0x00000004
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#define CYFLD_UDB_UDBIF_RD_WRK_WAIT__SIZE 0x00000002
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#define CYVAL_UDB_UDBIF_RD_WRK_WAIT_ONE_WAIT 0x00000000
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#define CYVAL_UDB_UDBIF_RD_WRK_WAIT_TWO_WAITS 0x00000001
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#define CYVAL_UDB_UDBIF_RD_WRK_WAIT_THREE_WAITS 0x00000002
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#define CYVAL_UDB_UDBIF_RD_WRK_WAIT_ZERO_WAITS 0x00000003
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#define CYFLD_UDB_UDBIF_WR_WRK_WAIT__OFFSET 0x00000006
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#define CYFLD_UDB_UDBIF_WR_WRK_WAIT__SIZE 0x00000002
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#define CYVAL_UDB_UDBIF_WR_WRK_WAIT_ONE_WAIT 0x00000000
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#define CYVAL_UDB_UDBIF_WR_WRK_WAIT_TWO_WAITS 0x00000001
|
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#define CYVAL_UDB_UDBIF_WR_WRK_WAIT_THREE_WAITS 0x00000002
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#define CYVAL_UDB_UDBIF_WR_WRK_WAIT_ZERO_WAITS 0x00000003
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#define CYREG_UDB_UDBIF_INT_CLK_CTL 0x400f701c
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#define CYFLD_UDB_UDBIF_EN_HFCLK__OFFSET 0x00000000
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#define CYFLD_UDB_UDBIF_EN_HFCLK__SIZE 0x00000001
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#define CYREG_UDB_INT_CFG 0x400f8000
|
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#define CYFLD_UDB_INT_MODE_CFG__OFFSET 0x00000000
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#define CYFLD_UDB_INT_MODE_CFG__SIZE 0x00000008
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#define CYVAL_UDB_INT_MODE_CFG_LEVEL 0x00000000
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#define CYVAL_UDB_INT_MODE_CFG_PULSE 0x00000001
|
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#define CYDEV_CPUSS_BASE 0x40100000
|
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#define CYDEV_CPUSS_SIZE 0x00001000
|
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#define CYREG_CPUSS_CONFIG 0x40100000
|
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#define CYFLD_CPUSS_VECT_IN_RAM__OFFSET 0x00000000
|
|
#define CYFLD_CPUSS_VECT_IN_RAM__SIZE 0x00000001
|
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#define CYREG_CPUSS_SYSREQ 0x40100004
|
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#define CYFLD_CPUSS_SYSCALL_COMMAND__OFFSET 0x00000000
|
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#define CYFLD_CPUSS_SYSCALL_COMMAND__SIZE 0x00000010
|
|
#define CYFLD_CPUSS_DIS_RESET_VECT_REL__OFFSET 0x0000001b
|
|
#define CYFLD_CPUSS_DIS_RESET_VECT_REL__SIZE 0x00000001
|
|
#define CYFLD_CPUSS_PRIVILEGED__OFFSET 0x0000001c
|
|
#define CYFLD_CPUSS_PRIVILEGED__SIZE 0x00000001
|
|
#define CYFLD_CPUSS_ROM_ACCESS_EN__OFFSET 0x0000001d
|
|
#define CYFLD_CPUSS_ROM_ACCESS_EN__SIZE 0x00000001
|
|
#define CYFLD_CPUSS_HMASTER_0__OFFSET 0x0000001e
|
|
#define CYFLD_CPUSS_HMASTER_0__SIZE 0x00000001
|
|
#define CYFLD_CPUSS_SYSCALL_REQ__OFFSET 0x0000001f
|
|
#define CYFLD_CPUSS_SYSCALL_REQ__SIZE 0x00000001
|
|
#define CYREG_CPUSS_SYSARG 0x40100008
|
|
#define CYFLD_CPUSS_SYSCALL_ARG__OFFSET 0x00000000
|
|
#define CYFLD_CPUSS_SYSCALL_ARG__SIZE 0x00000020
|
|
#define CYREG_CPUSS_PROTECTION 0x4010000c
|
|
#define CYFLD_CPUSS_PROTECTION_MODE__OFFSET 0x00000000
|
|
#define CYFLD_CPUSS_PROTECTION_MODE__SIZE 0x00000004
|
|
#define CYFLD_CPUSS_FLASH_LOCK__OFFSET 0x0000001e
|
|
#define CYFLD_CPUSS_FLASH_LOCK__SIZE 0x00000001
|
|
#define CYFLD_CPUSS_PROTECTION_LOCK__OFFSET 0x0000001f
|
|
#define CYFLD_CPUSS_PROTECTION_LOCK__SIZE 0x00000001
|
|
#define CYREG_CPUSS_PRIV_ROM 0x40100010
|
|
#define CYFLD_CPUSS_BROM_PROT_LIMIT__OFFSET 0x00000000
|
|
#define CYFLD_CPUSS_BROM_PROT_LIMIT__SIZE 0x00000008
|
|
#define CYREG_CPUSS_PRIV_RAM 0x40100014
|
|
#define CYFLD_CPUSS_RAM_PROT_LIMIT__OFFSET 0x00000000
|
|
#define CYFLD_CPUSS_RAM_PROT_LIMIT__SIZE 0x00000009
|
|
#define CYREG_CPUSS_PRIV_FLASH 0x40100018
|
|
#define CYFLD_CPUSS_FLASH_PROT_LIMIT__OFFSET 0x00000000
|
|
#define CYFLD_CPUSS_FLASH_PROT_LIMIT__SIZE 0x0000000b
|
|
#define CYREG_CPUSS_WOUNDING 0x4010001c
|
|
#define CYFLD_CPUSS_RAM_WOUND__OFFSET 0x00000010
|
|
#define CYFLD_CPUSS_RAM_WOUND__SIZE 0x00000003
|
|
#define CYFLD_CPUSS_FLASH_WOUND__OFFSET 0x00000014
|
|
#define CYFLD_CPUSS_FLASH_WOUND__SIZE 0x00000003
|
|
#define CYREG_CPUSS_INT_SEL 0x40100020
|
|
#define CYFLD_CPUSS_DSI__OFFSET 0x00000000
|
|
#define CYFLD_CPUSS_DSI__SIZE 0x00000020
|
|
#define CYREG_CPUSS_INT_MODE 0x40100024
|
|
#define CYFLD_CPUSS_DSI_INT_PULSE__OFFSET 0x00000000
|
|
#define CYFLD_CPUSS_DSI_INT_PULSE__SIZE 0x00000020
|
|
#define CYREG_CPUSS_NMI_MODE 0x40100028
|
|
#define CYFLD_CPUSS_DSI_NMI_PULSE__OFFSET 0x00000000
|
|
#define CYFLD_CPUSS_DSI_NMI_PULSE__SIZE 0x00000001
|
|
#define CYREG_CPUSS_FLASH_CTL 0x40100030
|
|
#define CYFLD_CPUSS_FLASH_WS__OFFSET 0x00000000
|
|
#define CYFLD_CPUSS_FLASH_WS__SIZE 0x00000002
|
|
#define CYFLD_CPUSS_PREF_EN__OFFSET 0x00000004
|
|
#define CYFLD_CPUSS_PREF_EN__SIZE 0x00000001
|
|
#define CYFLD_CPUSS_FLASH_INVALIDATE__OFFSET 0x00000008
|
|
#define CYFLD_CPUSS_FLASH_INVALIDATE__SIZE 0x00000001
|
|
#define CYREG_CPUSS_ROM_CTL 0x40100034
|
|
#define CYFLD_CPUSS_ROM_WS__OFFSET 0x00000000
|
|
#define CYFLD_CPUSS_ROM_WS__SIZE 0x00000001
|
|
#define CYDEV_SPCIF_BASE 0x40110000
|
|
#define CYDEV_SPCIF_SIZE 0x00010000
|
|
#define CYREG_SPCIF_GEOMETRY 0x40110000
|
|
#define CYFLD_SPCIF_FLASH__OFFSET 0x00000000
|
|
#define CYFLD_SPCIF_FLASH__SIZE 0x00000010
|
|
#define CYFLD_SPCIF_SFLASH__OFFSET 0x00000010
|
|
#define CYFLD_SPCIF_SFLASH__SIZE 0x00000004
|
|
#define CYFLD_SPCIF_NUM_FLASH__OFFSET 0x00000014
|
|
#define CYFLD_SPCIF_NUM_FLASH__SIZE 0x00000002
|
|
#define CYFLD_SPCIF_FLASH_ROW__OFFSET 0x00000016
|
|
#define CYFLD_SPCIF_FLASH_ROW__SIZE 0x00000002
|
|
#define CYFLD_SPCIF_NVL__OFFSET 0x00000018
|
|
#define CYFLD_SPCIF_NVL__SIZE 0x00000007
|
|
#define CYFLD_SPCIF_DE_CPD_LP__OFFSET 0x0000001f
|
|
#define CYFLD_SPCIF_DE_CPD_LP__SIZE 0x00000001
|
|
#define CYREG_SPCIF_NVL_WR_DATA 0x4011001c
|
|
#define CYFLD_SPCIF_DATA__OFFSET 0x00000000
|
|
#define CYFLD_SPCIF_DATA__SIZE 0x00000008
|
|
#define CYREG_SPCIF_INTR 0x401107f0
|
|
#define CYFLD_SPCIF_TIMER__OFFSET 0x00000000
|
|
#define CYFLD_SPCIF_TIMER__SIZE 0x00000001
|
|
#define CYREG_SPCIF_INTR_SET 0x401107f4
|
|
#define CYREG_SPCIF_INTR_MASK 0x401107f8
|
|
#define CYREG_SPCIF_INTR_MASKED 0x401107fc
|
|
#define CYDEV_TCPWM_BASE 0x40200000
|
|
#define CYDEV_TCPWM_SIZE 0x00010000
|
|
#define CYREG_TCPWM_CTRL 0x40200000
|
|
#define CYFLD_TCPWM_COUNTER_ENABLED__OFFSET 0x00000000
|
|
#define CYFLD_TCPWM_COUNTER_ENABLED__SIZE 0x00000004
|
|
#define CYREG_TCPWM_CMD 0x40200008
|
|
#define CYFLD_TCPWM_COUNTER_CAPTURE__OFFSET 0x00000000
|
|
#define CYFLD_TCPWM_COUNTER_CAPTURE__SIZE 0x00000004
|
|
#define CYFLD_TCPWM_COUNTER_RELOAD__OFFSET 0x00000008
|
|
#define CYFLD_TCPWM_COUNTER_RELOAD__SIZE 0x00000004
|
|
#define CYFLD_TCPWM_COUNTER_STOP__OFFSET 0x00000010
|
|
#define CYFLD_TCPWM_COUNTER_STOP__SIZE 0x00000004
|
|
#define CYFLD_TCPWM_COUNTER_START__OFFSET 0x00000018
|
|
#define CYFLD_TCPWM_COUNTER_START__SIZE 0x00000004
|
|
#define CYREG_TCPWM_INTR_CAUSE 0x4020000c
|
|
#define CYFLD_TCPWM_COUNTER_INT__OFFSET 0x00000000
|
|
#define CYFLD_TCPWM_COUNTER_INT__SIZE 0x00000004
|
|
#define CYDEV_TCPWM_CNT0_BASE 0x40200100
|
|
#define CYDEV_TCPWM_CNT0_SIZE 0x00000040
|
|
#define CYREG_TCPWM_CNT0_CTRL 0x40200100
|
|
#define CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__OFFSET 0x00000000
|
|
#define CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__SIZE 0x00000001
|
|
#define CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__OFFSET 0x00000001
|
|
#define CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__SIZE 0x00000001
|
|
#define CYFLD_TCPWM_CNT_PWM_SYNC_KILL__OFFSET 0x00000002
|
|
#define CYFLD_TCPWM_CNT_PWM_SYNC_KILL__SIZE 0x00000001
|
|
#define CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__OFFSET 0x00000003
|
|
#define CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__SIZE 0x00000001
|
|
#define CYFLD_TCPWM_CNT_GENERIC__OFFSET 0x00000008
|
|
#define CYFLD_TCPWM_CNT_GENERIC__SIZE 0x00000008
|
|
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY1 0x00000000
|
|
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY2 0x00000001
|
|
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY4 0x00000002
|
|
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY8 0x00000003
|
|
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY16 0x00000004
|
|
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY32 0x00000005
|
|
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY64 0x00000006
|
|
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY128 0x00000007
|
|
#define CYFLD_TCPWM_CNT_UP_DOWN_MODE__OFFSET 0x00000010
|
|
#define CYFLD_TCPWM_CNT_UP_DOWN_MODE__SIZE 0x00000002
|
|
#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UP 0x00000000
|
|
#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_DOWN 0x00000001
|
|
#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN1 0x00000002
|
|
#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN2 0x00000003
|
|
#define CYFLD_TCPWM_CNT_ONE_SHOT__OFFSET 0x00000012
|
|
#define CYFLD_TCPWM_CNT_ONE_SHOT__SIZE 0x00000001
|
|
#define CYFLD_TCPWM_CNT_QUADRATURE_MODE__OFFSET 0x00000014
|
|
#define CYFLD_TCPWM_CNT_QUADRATURE_MODE__SIZE 0x00000002
|
|
#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_X1 0x00000000
|
|
#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_X2 0x00000001
|
|
#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_X4 0x00000002
|
|
#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_OUT 0x00000001
|
|
#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_COMPL_OUT 0x00000002
|
|
#define CYFLD_TCPWM_CNT_MODE__OFFSET 0x00000018
|
|
#define CYFLD_TCPWM_CNT_MODE__SIZE 0x00000003
|
|
#define CYVAL_TCPWM_CNT_MODE_TIMER 0x00000000
|
|
#define CYVAL_TCPWM_CNT_MODE_CAPTURE 0x00000002
|
|
#define CYVAL_TCPWM_CNT_MODE_QUAD 0x00000003
|
|
#define CYVAL_TCPWM_CNT_MODE_PWM 0x00000004
|
|
#define CYVAL_TCPWM_CNT_MODE_PWM_DT 0x00000005
|
|
#define CYVAL_TCPWM_CNT_MODE_PWM_PR 0x00000006
|
|
#define CYREG_TCPWM_CNT0_STATUS 0x40200104
|
|
#define CYFLD_TCPWM_CNT_DOWN__OFFSET 0x00000000
|
|
#define CYFLD_TCPWM_CNT_DOWN__SIZE 0x00000001
|
|
#define CYFLD_TCPWM_CNT_RUNNING__OFFSET 0x0000001f
|
|
#define CYFLD_TCPWM_CNT_RUNNING__SIZE 0x00000001
|
|
#define CYREG_TCPWM_CNT0_COUNTER 0x40200108
|
|
#define CYFLD_TCPWM_CNT_COUNTER__OFFSET 0x00000000
|
|
#define CYFLD_TCPWM_CNT_COUNTER__SIZE 0x00000010
|
|
#define CYREG_TCPWM_CNT0_CC 0x4020010c
|
|
#define CYFLD_TCPWM_CNT_CC__OFFSET 0x00000000
|
|
#define CYFLD_TCPWM_CNT_CC__SIZE 0x00000010
|
|
#define CYREG_TCPWM_CNT0_CC_BUFF 0x40200110
|
|
#define CYREG_TCPWM_CNT0_PERIOD 0x40200114
|
|
#define CYFLD_TCPWM_CNT_PERIOD__OFFSET 0x00000000
|
|
#define CYFLD_TCPWM_CNT_PERIOD__SIZE 0x00000010
|
|
#define CYREG_TCPWM_CNT0_PERIOD_BUFF 0x40200118
|
|
#define CYREG_TCPWM_CNT0_TR_CTRL0 0x40200120
|
|
#define CYFLD_TCPWM_CNT_CAPTURE_SEL__OFFSET 0x00000000
|
|
#define CYFLD_TCPWM_CNT_CAPTURE_SEL__SIZE 0x00000004
|
|
#define CYFLD_TCPWM_CNT_COUNT_SEL__OFFSET 0x00000004
|
|
#define CYFLD_TCPWM_CNT_COUNT_SEL__SIZE 0x00000004
|
|
#define CYFLD_TCPWM_CNT_RELOAD_SEL__OFFSET 0x00000008
|
|
#define CYFLD_TCPWM_CNT_RELOAD_SEL__SIZE 0x00000004
|
|
#define CYFLD_TCPWM_CNT_STOP_SEL__OFFSET 0x0000000c
|
|
#define CYFLD_TCPWM_CNT_STOP_SEL__SIZE 0x00000004
|
|
#define CYFLD_TCPWM_CNT_START_SEL__OFFSET 0x00000010
|
|
#define CYFLD_TCPWM_CNT_START_SEL__SIZE 0x00000004
|
|
#define CYREG_TCPWM_CNT0_TR_CTRL1 0x40200124
|
|
#define CYFLD_TCPWM_CNT_CAPTURE_EDGE__OFFSET 0x00000000
|
|
#define CYFLD_TCPWM_CNT_CAPTURE_EDGE__SIZE 0x00000002
|
|
#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_RISING_EDGE 0x00000000
|
|
#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_FALLING_EDGE 0x00000001
|
|
#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_BOTH_EDGES 0x00000002
|
|
#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_NO_EDGE_DET 0x00000003
|
|
#define CYFLD_TCPWM_CNT_COUNT_EDGE__OFFSET 0x00000002
|
|
#define CYFLD_TCPWM_CNT_COUNT_EDGE__SIZE 0x00000002
|
|
#define CYVAL_TCPWM_CNT_COUNT_EDGE_RISING_EDGE 0x00000000
|
|
#define CYVAL_TCPWM_CNT_COUNT_EDGE_FALLING_EDGE 0x00000001
|
|
#define CYVAL_TCPWM_CNT_COUNT_EDGE_BOTH_EDGES 0x00000002
|
|
#define CYVAL_TCPWM_CNT_COUNT_EDGE_NO_EDGE_DET 0x00000003
|
|
#define CYFLD_TCPWM_CNT_RELOAD_EDGE__OFFSET 0x00000004
|
|
#define CYFLD_TCPWM_CNT_RELOAD_EDGE__SIZE 0x00000002
|
|
#define CYVAL_TCPWM_CNT_RELOAD_EDGE_RISING_EDGE 0x00000000
|
|
#define CYVAL_TCPWM_CNT_RELOAD_EDGE_FALLING_EDGE 0x00000001
|
|
#define CYVAL_TCPWM_CNT_RELOAD_EDGE_BOTH_EDGES 0x00000002
|
|
#define CYVAL_TCPWM_CNT_RELOAD_EDGE_NO_EDGE_DET 0x00000003
|
|
#define CYFLD_TCPWM_CNT_STOP_EDGE__OFFSET 0x00000006
|
|
#define CYFLD_TCPWM_CNT_STOP_EDGE__SIZE 0x00000002
|
|
#define CYVAL_TCPWM_CNT_STOP_EDGE_RISING_EDGE 0x00000000
|
|
#define CYVAL_TCPWM_CNT_STOP_EDGE_FALLING_EDGE 0x00000001
|
|
#define CYVAL_TCPWM_CNT_STOP_EDGE_BOTH_EDGES 0x00000002
|
|
#define CYVAL_TCPWM_CNT_STOP_EDGE_NO_EDGE_DET 0x00000003
|
|
#define CYFLD_TCPWM_CNT_START_EDGE__OFFSET 0x00000008
|
|
#define CYFLD_TCPWM_CNT_START_EDGE__SIZE 0x00000002
|
|
#define CYVAL_TCPWM_CNT_START_EDGE_RISING_EDGE 0x00000000
|
|
#define CYVAL_TCPWM_CNT_START_EDGE_FALLING_EDGE 0x00000001
|
|
#define CYVAL_TCPWM_CNT_START_EDGE_BOTH_EDGES 0x00000002
|
|
#define CYVAL_TCPWM_CNT_START_EDGE_NO_EDGE_DET 0x00000003
|
|
#define CYREG_TCPWM_CNT0_TR_CTRL2 0x40200128
|
|
#define CYFLD_TCPWM_CNT_CC_MATCH_MODE__OFFSET 0x00000000
|
|
#define CYFLD_TCPWM_CNT_CC_MATCH_MODE__SIZE 0x00000002
|
|
#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_SET 0x00000000
|
|
#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_CLEAR 0x00000001
|
|
#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_INVERT 0x00000002
|
|
#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_NO_CHANGE 0x00000003
|
|
#define CYFLD_TCPWM_CNT_OVERFLOW_MODE__OFFSET 0x00000002
|
|
#define CYFLD_TCPWM_CNT_OVERFLOW_MODE__SIZE 0x00000002
|
|
#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_SET 0x00000000
|
|
#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_CLEAR 0x00000001
|
|
#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_INVERT 0x00000002
|
|
#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_NO_CHANGE 0x00000003
|
|
#define CYFLD_TCPWM_CNT_UNDERFLOW_MODE__OFFSET 0x00000004
|
|
#define CYFLD_TCPWM_CNT_UNDERFLOW_MODE__SIZE 0x00000002
|
|
#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_SET 0x00000000
|
|
#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_CLEAR 0x00000001
|
|
#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_INVERT 0x00000002
|
|
#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_NO_CHANGE 0x00000003
|
|
#define CYREG_TCPWM_CNT0_INTR 0x40200130
|
|
#define CYFLD_TCPWM_CNT_TC__OFFSET 0x00000000
|
|
#define CYFLD_TCPWM_CNT_TC__SIZE 0x00000001
|
|
#define CYFLD_TCPWM_CNT_CC_MATCH__OFFSET 0x00000001
|
|
#define CYFLD_TCPWM_CNT_CC_MATCH__SIZE 0x00000001
|
|
#define CYREG_TCPWM_CNT0_INTR_SET 0x40200134
|
|
#define CYREG_TCPWM_CNT0_INTR_MASK 0x40200138
|
|
#define CYREG_TCPWM_CNT0_INTR_MASKED 0x4020013c
|
|
#define CYDEV_TCPWM_CNT1_BASE 0x40200140
|
|
#define CYDEV_TCPWM_CNT1_SIZE 0x00000040
|
|
#define CYREG_TCPWM_CNT1_CTRL 0x40200140
|
|
#define CYREG_TCPWM_CNT1_STATUS 0x40200144
|
|
#define CYREG_TCPWM_CNT1_COUNTER 0x40200148
|
|
#define CYREG_TCPWM_CNT1_CC 0x4020014c
|
|
#define CYREG_TCPWM_CNT1_CC_BUFF 0x40200150
|
|
#define CYREG_TCPWM_CNT1_PERIOD 0x40200154
|
|
#define CYREG_TCPWM_CNT1_PERIOD_BUFF 0x40200158
|
|
#define CYREG_TCPWM_CNT1_TR_CTRL0 0x40200160
|
|
#define CYREG_TCPWM_CNT1_TR_CTRL1 0x40200164
|
|
#define CYREG_TCPWM_CNT1_TR_CTRL2 0x40200168
|
|
#define CYREG_TCPWM_CNT1_INTR 0x40200170
|
|
#define CYREG_TCPWM_CNT1_INTR_SET 0x40200174
|
|
#define CYREG_TCPWM_CNT1_INTR_MASK 0x40200178
|
|
#define CYREG_TCPWM_CNT1_INTR_MASKED 0x4020017c
|
|
#define CYDEV_TCPWM_CNT2_BASE 0x40200180
|
|
#define CYDEV_TCPWM_CNT2_SIZE 0x00000040
|
|
#define CYREG_TCPWM_CNT2_CTRL 0x40200180
|
|
#define CYREG_TCPWM_CNT2_STATUS 0x40200184
|
|
#define CYREG_TCPWM_CNT2_COUNTER 0x40200188
|
|
#define CYREG_TCPWM_CNT2_CC 0x4020018c
|
|
#define CYREG_TCPWM_CNT2_CC_BUFF 0x40200190
|
|
#define CYREG_TCPWM_CNT2_PERIOD 0x40200194
|
|
#define CYREG_TCPWM_CNT2_PERIOD_BUFF 0x40200198
|
|
#define CYREG_TCPWM_CNT2_TR_CTRL0 0x402001a0
|
|
#define CYREG_TCPWM_CNT2_TR_CTRL1 0x402001a4
|
|
#define CYREG_TCPWM_CNT2_TR_CTRL2 0x402001a8
|
|
#define CYREG_TCPWM_CNT2_INTR 0x402001b0
|
|
#define CYREG_TCPWM_CNT2_INTR_SET 0x402001b4
|
|
#define CYREG_TCPWM_CNT2_INTR_MASK 0x402001b8
|
|
#define CYREG_TCPWM_CNT2_INTR_MASKED 0x402001bc
|
|
#define CYDEV_TCPWM_CNT3_BASE 0x402001c0
|
|
#define CYDEV_TCPWM_CNT3_SIZE 0x00000040
|
|
#define CYREG_TCPWM_CNT3_CTRL 0x402001c0
|
|
#define CYREG_TCPWM_CNT3_STATUS 0x402001c4
|
|
#define CYREG_TCPWM_CNT3_COUNTER 0x402001c8
|
|
#define CYREG_TCPWM_CNT3_CC 0x402001cc
|
|
#define CYREG_TCPWM_CNT3_CC_BUFF 0x402001d0
|
|
#define CYREG_TCPWM_CNT3_PERIOD 0x402001d4
|
|
#define CYREG_TCPWM_CNT3_PERIOD_BUFF 0x402001d8
|
|
#define CYREG_TCPWM_CNT3_TR_CTRL0 0x402001e0
|
|
#define CYREG_TCPWM_CNT3_TR_CTRL1 0x402001e4
|
|
#define CYREG_TCPWM_CNT3_TR_CTRL2 0x402001e8
|
|
#define CYREG_TCPWM_CNT3_INTR 0x402001f0
|
|
#define CYREG_TCPWM_CNT3_INTR_SET 0x402001f4
|
|
#define CYREG_TCPWM_CNT3_INTR_MASK 0x402001f8
|
|
#define CYREG_TCPWM_CNT3_INTR_MASKED 0x402001fc
|
|
#define CYDEV_SCB0_BASE 0x40240000
|
|
#define CYDEV_SCB0_SIZE 0x00010000
|
|
#define CYREG_SCB0_CTRL 0x40240000
|
|
#define CYFLD_SCB_OVS__OFFSET 0x00000000
|
|
#define CYFLD_SCB_OVS__SIZE 0x00000004
|
|
#define CYFLD_SCB_EC_AM_MODE__OFFSET 0x00000008
|
|
#define CYFLD_SCB_EC_AM_MODE__SIZE 0x00000001
|
|
#define CYFLD_SCB_EC_OP_MODE__OFFSET 0x00000009
|
|
#define CYFLD_SCB_EC_OP_MODE__SIZE 0x00000001
|
|
#define CYFLD_SCB_EZ_MODE__OFFSET 0x0000000a
|
|
#define CYFLD_SCB_EZ_MODE__SIZE 0x00000001
|
|
#define CYFLD_SCB_BYTE_MODE__OFFSET 0x0000000b
|
|
#define CYFLD_SCB_BYTE_MODE__SIZE 0x00000001
|
|
#define CYFLD_SCB_ADDR_ACCEPT__OFFSET 0x00000010
|
|
#define CYFLD_SCB_ADDR_ACCEPT__SIZE 0x00000001
|
|
#define CYFLD_SCB_BLOCK__OFFSET 0x00000011
|
|
#define CYFLD_SCB_BLOCK__SIZE 0x00000001
|
|
#define CYFLD_SCB_MODE__OFFSET 0x00000018
|
|
#define CYFLD_SCB_MODE__SIZE 0x00000002
|
|
#define CYVAL_SCB_MODE_I2C 0x00000000
|
|
#define CYVAL_SCB_MODE_SPI 0x00000001
|
|
#define CYVAL_SCB_MODE_UART 0x00000002
|
|
#define CYFLD_SCB_ENABLED__OFFSET 0x0000001f
|
|
#define CYFLD_SCB_ENABLED__SIZE 0x00000001
|
|
#define CYREG_SCB0_STATUS 0x40240004
|
|
#define CYFLD_SCB_EC_BUSY__OFFSET 0x00000000
|
|
#define CYFLD_SCB_EC_BUSY__SIZE 0x00000001
|
|
#define CYREG_SCB0_SPI_CTRL 0x40240020
|
|
#define CYFLD_SCB_CONTINUOUS__OFFSET 0x00000000
|
|
#define CYFLD_SCB_CONTINUOUS__SIZE 0x00000001
|
|
#define CYFLD_SCB_SELECT_PRECEDE__OFFSET 0x00000001
|
|
#define CYFLD_SCB_SELECT_PRECEDE__SIZE 0x00000001
|
|
#define CYFLD_SCB_CPHA__OFFSET 0x00000002
|
|
#define CYFLD_SCB_CPHA__SIZE 0x00000001
|
|
#define CYFLD_SCB_CPOL__OFFSET 0x00000003
|
|
#define CYFLD_SCB_CPOL__SIZE 0x00000001
|
|
#define CYFLD_SCB_LATE_MISO_SAMPLE__OFFSET 0x00000004
|
|
#define CYFLD_SCB_LATE_MISO_SAMPLE__SIZE 0x00000001
|
|
#define CYFLD_SCB_SCLK_CONTINUOUS__OFFSET 0x00000005
|
|
#define CYFLD_SCB_SCLK_CONTINUOUS__SIZE 0x00000001
|
|
#define CYFLD_SCB_SSEL_POLARITY0__OFFSET 0x00000008
|
|
#define CYFLD_SCB_SSEL_POLARITY0__SIZE 0x00000001
|
|
#define CYFLD_SCB_SSEL_POLARITY1__OFFSET 0x00000009
|
|
#define CYFLD_SCB_SSEL_POLARITY1__SIZE 0x00000001
|
|
#define CYFLD_SCB_SSEL_POLARITY2__OFFSET 0x0000000a
|
|
#define CYFLD_SCB_SSEL_POLARITY2__SIZE 0x00000001
|
|
#define CYFLD_SCB_SSEL_POLARITY3__OFFSET 0x0000000b
|
|
#define CYFLD_SCB_SSEL_POLARITY3__SIZE 0x00000001
|
|
#define CYFLD_SCB_LOOPBACK__OFFSET 0x00000010
|
|
#define CYFLD_SCB_LOOPBACK__SIZE 0x00000001
|
|
#define CYFLD_SCB_SLAVE_SELECT__OFFSET 0x0000001a
|
|
#define CYFLD_SCB_SLAVE_SELECT__SIZE 0x00000002
|
|
#define CYFLD_SCB_MASTER_MODE__OFFSET 0x0000001f
|
|
#define CYFLD_SCB_MASTER_MODE__SIZE 0x00000001
|
|
#define CYREG_SCB0_SPI_STATUS 0x40240024
|
|
#define CYFLD_SCB_BUS_BUSY__OFFSET 0x00000000
|
|
#define CYFLD_SCB_BUS_BUSY__SIZE 0x00000001
|
|
#define CYFLD_SCB_SPI_EC_BUSY__OFFSET 0x00000001
|
|
#define CYFLD_SCB_SPI_EC_BUSY__SIZE 0x00000001
|
|
#define CYFLD_SCB_CURR_EZ_ADDR__OFFSET 0x00000008
|
|
#define CYFLD_SCB_CURR_EZ_ADDR__SIZE 0x00000008
|
|
#define CYFLD_SCB_BASE_EZ_ADDR__OFFSET 0x00000010
|
|
#define CYFLD_SCB_BASE_EZ_ADDR__SIZE 0x00000008
|
|
#define CYREG_SCB0_UART_CTRL 0x40240040
|
|
#define CYREG_SCB0_UART_TX_CTRL 0x40240044
|
|
#define CYFLD_SCB_STOP_BITS__OFFSET 0x00000000
|
|
#define CYFLD_SCB_STOP_BITS__SIZE 0x00000003
|
|
#define CYFLD_SCB_PARITY__OFFSET 0x00000004
|
|
#define CYFLD_SCB_PARITY__SIZE 0x00000001
|
|
#define CYFLD_SCB_PARITY_ENABLED__OFFSET 0x00000005
|
|
#define CYFLD_SCB_PARITY_ENABLED__SIZE 0x00000001
|
|
#define CYFLD_SCB_RETRY_ON_NACK__OFFSET 0x00000008
|
|
#define CYFLD_SCB_RETRY_ON_NACK__SIZE 0x00000001
|
|
#define CYREG_SCB0_UART_RX_CTRL 0x40240048
|
|
#define CYFLD_SCB_POLARITY__OFFSET 0x00000006
|
|
#define CYFLD_SCB_POLARITY__SIZE 0x00000001
|
|
#define CYFLD_SCB_DROP_ON_PARITY_ERROR__OFFSET 0x00000008
|
|
#define CYFLD_SCB_DROP_ON_PARITY_ERROR__SIZE 0x00000001
|
|
#define CYFLD_SCB_DROP_ON_FRAME_ERROR__OFFSET 0x00000009
|
|
#define CYFLD_SCB_DROP_ON_FRAME_ERROR__SIZE 0x00000001
|
|
#define CYFLD_SCB_MP_MODE__OFFSET 0x0000000a
|
|
#define CYFLD_SCB_MP_MODE__SIZE 0x00000001
|
|
#define CYFLD_SCB_LIN_MODE__OFFSET 0x0000000c
|
|
#define CYFLD_SCB_LIN_MODE__SIZE 0x00000001
|
|
#define CYFLD_SCB_SKIP_START__OFFSET 0x0000000d
|
|
#define CYFLD_SCB_SKIP_START__SIZE 0x00000001
|
|
#define CYFLD_SCB_BREAK_WIDTH__OFFSET 0x00000010
|
|
#define CYFLD_SCB_BREAK_WIDTH__SIZE 0x00000004
|
|
#define CYREG_SCB0_UART_RX_STATUS 0x4024004c
|
|
#define CYFLD_SCB_BR_COUNTER__OFFSET 0x00000000
|
|
#define CYFLD_SCB_BR_COUNTER__SIZE 0x0000000c
|
|
#define CYREG_SCB0_UART_FLOW_CTRL 0x40240050
|
|
#define CYFLD_SCB_TRIGGER_LEVEL__OFFSET 0x00000000
|
|
#define CYFLD_SCB_TRIGGER_LEVEL__SIZE 0x00000004
|
|
#define CYFLD_SCB_RTS_POLARITY__OFFSET 0x00000010
|
|
#define CYFLD_SCB_RTS_POLARITY__SIZE 0x00000001
|
|
#define CYFLD_SCB_CTS_POLARITY__OFFSET 0x00000018
|
|
#define CYFLD_SCB_CTS_POLARITY__SIZE 0x00000001
|
|
#define CYFLD_SCB_CTS_ENABLED__OFFSET 0x00000019
|
|
#define CYFLD_SCB_CTS_ENABLED__SIZE 0x00000001
|
|
#define CYREG_SCB0_I2C_CTRL 0x40240060
|
|
#define CYFLD_SCB_HIGH_PHASE_OVS__OFFSET 0x00000000
|
|
#define CYFLD_SCB_HIGH_PHASE_OVS__SIZE 0x00000004
|
|
#define CYFLD_SCB_LOW_PHASE_OVS__OFFSET 0x00000004
|
|
#define CYFLD_SCB_LOW_PHASE_OVS__SIZE 0x00000004
|
|
#define CYFLD_SCB_M_READY_DATA_ACK__OFFSET 0x00000008
|
|
#define CYFLD_SCB_M_READY_DATA_ACK__SIZE 0x00000001
|
|
#define CYFLD_SCB_M_NOT_READY_DATA_NACK__OFFSET 0x00000009
|
|
#define CYFLD_SCB_M_NOT_READY_DATA_NACK__SIZE 0x00000001
|
|
#define CYFLD_SCB_S_GENERAL_IGNORE__OFFSET 0x0000000b
|
|
#define CYFLD_SCB_S_GENERAL_IGNORE__SIZE 0x00000001
|
|
#define CYFLD_SCB_S_READY_ADDR_ACK__OFFSET 0x0000000c
|
|
#define CYFLD_SCB_S_READY_ADDR_ACK__SIZE 0x00000001
|
|
#define CYFLD_SCB_S_READY_DATA_ACK__OFFSET 0x0000000d
|
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#define CYFLD_SCB_S_READY_DATA_ACK__SIZE 0x00000001
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#define CYFLD_SCB_S_NOT_READY_ADDR_NACK__OFFSET 0x0000000e
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#define CYFLD_SCB_S_NOT_READY_ADDR_NACK__SIZE 0x00000001
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#define CYFLD_SCB_S_NOT_READY_DATA_NACK__OFFSET 0x0000000f
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#define CYFLD_SCB_S_NOT_READY_DATA_NACK__SIZE 0x00000001
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#define CYFLD_SCB_SLAVE_MODE__OFFSET 0x0000001e
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#define CYFLD_SCB_SLAVE_MODE__SIZE 0x00000001
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#define CYREG_SCB0_I2C_STATUS 0x40240064
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#define CYFLD_SCB_I2C_EC_BUSY__OFFSET 0x00000001
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#define CYFLD_SCB_I2C_EC_BUSY__SIZE 0x00000001
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#define CYFLD_SCB_S_READ__OFFSET 0x00000004
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#define CYFLD_SCB_S_READ__SIZE 0x00000001
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#define CYFLD_SCB_M_READ__OFFSET 0x00000005
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#define CYFLD_SCB_M_READ__SIZE 0x00000001
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#define CYREG_SCB0_I2C_M_CMD 0x40240068
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#define CYFLD_SCB_M_START__OFFSET 0x00000000
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#define CYFLD_SCB_M_START__SIZE 0x00000001
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#define CYFLD_SCB_M_START_ON_IDLE__OFFSET 0x00000001
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#define CYFLD_SCB_M_START_ON_IDLE__SIZE 0x00000001
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#define CYFLD_SCB_M_ACK__OFFSET 0x00000002
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#define CYFLD_SCB_M_ACK__SIZE 0x00000001
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#define CYFLD_SCB_M_NACK__OFFSET 0x00000003
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#define CYFLD_SCB_M_NACK__SIZE 0x00000001
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#define CYFLD_SCB_M_STOP__OFFSET 0x00000004
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#define CYFLD_SCB_M_STOP__SIZE 0x00000001
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#define CYREG_SCB0_I2C_S_CMD 0x4024006c
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#define CYFLD_SCB_S_ACK__OFFSET 0x00000000
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#define CYFLD_SCB_S_ACK__SIZE 0x00000001
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#define CYFLD_SCB_S_NACK__OFFSET 0x00000001
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#define CYFLD_SCB_S_NACK__SIZE 0x00000001
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#define CYREG_SCB0_I2C_CFG 0x40240070
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#define CYFLD_SCB_SDA_IN_FILT_TRIM__OFFSET 0x00000000
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#define CYFLD_SCB_SDA_IN_FILT_TRIM__SIZE 0x00000002
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#define CYFLD_SCB_SDA_IN_FILT_SEL__OFFSET 0x00000004
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#define CYFLD_SCB_SDA_IN_FILT_SEL__SIZE 0x00000001
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#define CYFLD_SCB_SCL_IN_FILT_TRIM__OFFSET 0x00000008
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#define CYFLD_SCB_SCL_IN_FILT_TRIM__SIZE 0x00000002
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#define CYFLD_SCB_SCL_IN_FILT_SEL__OFFSET 0x0000000c
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#define CYFLD_SCB_SCL_IN_FILT_SEL__SIZE 0x00000001
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#define CYFLD_SCB_SDA_OUT_FILT0_TRIM__OFFSET 0x00000010
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#define CYFLD_SCB_SDA_OUT_FILT0_TRIM__SIZE 0x00000002
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#define CYFLD_SCB_SDA_OUT_FILT1_TRIM__OFFSET 0x00000012
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#define CYFLD_SCB_SDA_OUT_FILT1_TRIM__SIZE 0x00000002
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#define CYFLD_SCB_SDA_OUT_FILT2_TRIM__OFFSET 0x00000014
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#define CYFLD_SCB_SDA_OUT_FILT2_TRIM__SIZE 0x00000002
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#define CYFLD_SCB_SDA_OUT_FILT_SEL__OFFSET 0x0000001c
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#define CYFLD_SCB_SDA_OUT_FILT_SEL__SIZE 0x00000002
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#define CYREG_SCB0_TX_CTRL 0x40240200
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#define CYFLD_SCB_DATA_WIDTH__OFFSET 0x00000000
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#define CYFLD_SCB_DATA_WIDTH__SIZE 0x00000004
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#define CYFLD_SCB_MSB_FIRST__OFFSET 0x00000008
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#define CYFLD_SCB_MSB_FIRST__SIZE 0x00000001
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#define CYREG_SCB0_TX_FIFO_CTRL 0x40240204
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#define CYFLD_SCB_CLEAR__OFFSET 0x00000010
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#define CYFLD_SCB_CLEAR__SIZE 0x00000001
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#define CYFLD_SCB_FREEZE__OFFSET 0x00000011
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#define CYFLD_SCB_FREEZE__SIZE 0x00000001
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#define CYREG_SCB0_TX_FIFO_STATUS 0x40240208
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#define CYFLD_SCB_USED__OFFSET 0x00000000
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#define CYFLD_SCB_USED__SIZE 0x00000005
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#define CYFLD_SCB_SR_VALID__OFFSET 0x0000000f
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#define CYFLD_SCB_SR_VALID__SIZE 0x00000001
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#define CYFLD_SCB_RD_PTR__OFFSET 0x00000010
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#define CYFLD_SCB_RD_PTR__SIZE 0x00000004
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#define CYFLD_SCB_WR_PTR__OFFSET 0x00000018
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#define CYFLD_SCB_WR_PTR__SIZE 0x00000004
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#define CYREG_SCB0_TX_FIFO_WR 0x40240240
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#define CYFLD_SCB_DATA__OFFSET 0x00000000
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#define CYFLD_SCB_DATA__SIZE 0x00000010
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#define CYREG_SCB0_RX_CTRL 0x40240300
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#define CYFLD_SCB_MEDIAN__OFFSET 0x00000009
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#define CYFLD_SCB_MEDIAN__SIZE 0x00000001
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#define CYREG_SCB0_RX_FIFO_CTRL 0x40240304
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#define CYREG_SCB0_RX_FIFO_STATUS 0x40240308
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#define CYREG_SCB0_RX_MATCH 0x40240310
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#define CYFLD_SCB_ADDR__OFFSET 0x00000000
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#define CYFLD_SCB_ADDR__SIZE 0x00000008
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#define CYFLD_SCB_MASK__OFFSET 0x00000010
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#define CYFLD_SCB_MASK__SIZE 0x00000008
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#define CYREG_SCB0_RX_FIFO_RD 0x40240340
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#define CYREG_SCB0_RX_FIFO_RD_SILENT 0x40240344
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#define CYREG_SCB0_EZ_DATA0 0x40240400
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#define CYFLD_SCB_EZ_DATA__OFFSET 0x00000000
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#define CYFLD_SCB_EZ_DATA__SIZE 0x00000008
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#define CYREG_SCB0_EZ_DATA1 0x40240404
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#define CYREG_SCB0_EZ_DATA2 0x40240408
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#define CYREG_SCB0_EZ_DATA3 0x4024040c
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#define CYREG_SCB0_EZ_DATA4 0x40240410
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#define CYREG_SCB0_EZ_DATA5 0x40240414
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#define CYREG_SCB0_EZ_DATA6 0x40240418
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#define CYREG_SCB0_EZ_DATA7 0x4024041c
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#define CYREG_SCB0_EZ_DATA8 0x40240420
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#define CYREG_SCB0_EZ_DATA9 0x40240424
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#define CYREG_SCB0_EZ_DATA10 0x40240428
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#define CYREG_SCB0_EZ_DATA11 0x4024042c
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#define CYREG_SCB0_EZ_DATA12 0x40240430
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#define CYREG_SCB0_EZ_DATA13 0x40240434
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#define CYREG_SCB0_EZ_DATA14 0x40240438
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#define CYREG_SCB0_EZ_DATA15 0x4024043c
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#define CYREG_SCB0_EZ_DATA16 0x40240440
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#define CYREG_SCB0_EZ_DATA17 0x40240444
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#define CYREG_SCB0_EZ_DATA18 0x40240448
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#define CYREG_SCB0_EZ_DATA19 0x4024044c
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#define CYREG_SCB0_EZ_DATA20 0x40240450
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#define CYREG_SCB0_EZ_DATA21 0x40240454
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#define CYREG_SCB0_EZ_DATA22 0x40240458
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#define CYREG_SCB0_EZ_DATA23 0x4024045c
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#define CYREG_SCB0_EZ_DATA24 0x40240460
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#define CYREG_SCB0_EZ_DATA25 0x40240464
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#define CYREG_SCB0_EZ_DATA26 0x40240468
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#define CYREG_SCB0_EZ_DATA27 0x4024046c
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#define CYREG_SCB0_EZ_DATA28 0x40240470
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#define CYREG_SCB0_EZ_DATA29 0x40240474
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#define CYREG_SCB0_EZ_DATA30 0x40240478
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#define CYREG_SCB0_EZ_DATA31 0x4024047c
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#define CYREG_SCB0_INTR_CAUSE 0x40240e00
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#define CYFLD_SCB_M__OFFSET 0x00000000
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#define CYFLD_SCB_M__SIZE 0x00000001
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#define CYFLD_SCB_S__OFFSET 0x00000001
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#define CYFLD_SCB_S__SIZE 0x00000001
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#define CYFLD_SCB_TX__OFFSET 0x00000002
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#define CYFLD_SCB_TX__SIZE 0x00000001
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#define CYFLD_SCB_RX__OFFSET 0x00000003
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#define CYFLD_SCB_RX__SIZE 0x00000001
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#define CYFLD_SCB_I2C_EC__OFFSET 0x00000004
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#define CYFLD_SCB_I2C_EC__SIZE 0x00000001
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#define CYFLD_SCB_SPI_EC__OFFSET 0x00000005
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#define CYFLD_SCB_SPI_EC__SIZE 0x00000001
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#define CYREG_SCB0_INTR_I2C_EC 0x40240e80
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#define CYFLD_SCB_WAKE_UP__OFFSET 0x00000000
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#define CYFLD_SCB_WAKE_UP__SIZE 0x00000001
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#define CYFLD_SCB_EZ_STOP__OFFSET 0x00000001
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#define CYFLD_SCB_EZ_STOP__SIZE 0x00000001
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#define CYFLD_SCB_EZ_WRITE_STOP__OFFSET 0x00000002
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#define CYFLD_SCB_EZ_WRITE_STOP__SIZE 0x00000001
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#define CYFLD_SCB_EZ_READ_STOP__OFFSET 0x00000003
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#define CYFLD_SCB_EZ_READ_STOP__SIZE 0x00000001
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#define CYREG_SCB0_INTR_I2C_EC_MASK 0x40240e88
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#define CYREG_SCB0_INTR_I2C_EC_MASKED 0x40240e8c
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#define CYREG_SCB0_INTR_SPI_EC 0x40240ec0
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#define CYREG_SCB0_INTR_SPI_EC_MASK 0x40240ec8
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#define CYREG_SCB0_INTR_SPI_EC_MASKED 0x40240ecc
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#define CYREG_SCB0_INTR_M 0x40240f00
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#define CYFLD_SCB_I2C_ARB_LOST__OFFSET 0x00000000
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#define CYFLD_SCB_I2C_ARB_LOST__SIZE 0x00000001
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#define CYFLD_SCB_I2C_NACK__OFFSET 0x00000001
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#define CYFLD_SCB_I2C_NACK__SIZE 0x00000001
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#define CYFLD_SCB_I2C_ACK__OFFSET 0x00000002
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#define CYFLD_SCB_I2C_ACK__SIZE 0x00000001
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#define CYFLD_SCB_I2C_STOP__OFFSET 0x00000004
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#define CYFLD_SCB_I2C_STOP__SIZE 0x00000001
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#define CYFLD_SCB_I2C_BUS_ERROR__OFFSET 0x00000008
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#define CYFLD_SCB_I2C_BUS_ERROR__SIZE 0x00000001
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#define CYFLD_SCB_SPI_DONE__OFFSET 0x00000009
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#define CYFLD_SCB_SPI_DONE__SIZE 0x00000001
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#define CYREG_SCB0_INTR_M_SET 0x40240f04
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#define CYREG_SCB0_INTR_M_MASK 0x40240f08
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#define CYREG_SCB0_INTR_M_MASKED 0x40240f0c
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#define CYREG_SCB0_INTR_S 0x40240f40
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#define CYFLD_SCB_I2C_WRITE_STOP__OFFSET 0x00000003
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#define CYFLD_SCB_I2C_WRITE_STOP__SIZE 0x00000001
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#define CYFLD_SCB_I2C_START__OFFSET 0x00000005
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#define CYFLD_SCB_I2C_START__SIZE 0x00000001
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#define CYFLD_SCB_I2C_ADDR_MATCH__OFFSET 0x00000006
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#define CYFLD_SCB_I2C_ADDR_MATCH__SIZE 0x00000001
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#define CYFLD_SCB_I2C_GENERAL__OFFSET 0x00000007
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#define CYFLD_SCB_I2C_GENERAL__SIZE 0x00000001
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#define CYFLD_SCB_SPI_EZ_WRITE_STOP__OFFSET 0x00000009
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#define CYFLD_SCB_SPI_EZ_WRITE_STOP__SIZE 0x00000001
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#define CYFLD_SCB_SPI_EZ_STOP__OFFSET 0x0000000a
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#define CYFLD_SCB_SPI_EZ_STOP__SIZE 0x00000001
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#define CYFLD_SCB_SPI_BUS_ERROR__OFFSET 0x0000000b
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#define CYFLD_SCB_SPI_BUS_ERROR__SIZE 0x00000001
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#define CYREG_SCB0_INTR_S_SET 0x40240f44
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#define CYREG_SCB0_INTR_S_MASK 0x40240f48
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#define CYREG_SCB0_INTR_S_MASKED 0x40240f4c
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#define CYREG_SCB0_INTR_TX 0x40240f80
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#define CYFLD_SCB_TRIGGER__OFFSET 0x00000000
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#define CYFLD_SCB_TRIGGER__SIZE 0x00000001
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#define CYFLD_SCB_NOT_FULL__OFFSET 0x00000001
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#define CYFLD_SCB_NOT_FULL__SIZE 0x00000001
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#define CYFLD_SCB_EMPTY__OFFSET 0x00000004
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#define CYFLD_SCB_EMPTY__SIZE 0x00000001
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#define CYFLD_SCB_OVERFLOW__OFFSET 0x00000005
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#define CYFLD_SCB_OVERFLOW__SIZE 0x00000001
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#define CYFLD_SCB_UNDERFLOW__OFFSET 0x00000006
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#define CYFLD_SCB_UNDERFLOW__SIZE 0x00000001
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#define CYFLD_SCB_BLOCKED__OFFSET 0x00000007
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#define CYFLD_SCB_BLOCKED__SIZE 0x00000001
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#define CYFLD_SCB_UART_NACK__OFFSET 0x00000008
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#define CYFLD_SCB_UART_NACK__SIZE 0x00000001
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#define CYFLD_SCB_UART_DONE__OFFSET 0x00000009
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#define CYFLD_SCB_UART_DONE__SIZE 0x00000001
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#define CYFLD_SCB_UART_ARB_LOST__OFFSET 0x0000000a
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#define CYFLD_SCB_UART_ARB_LOST__SIZE 0x00000001
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#define CYREG_SCB0_INTR_TX_SET 0x40240f84
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#define CYREG_SCB0_INTR_TX_MASK 0x40240f88
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#define CYREG_SCB0_INTR_TX_MASKED 0x40240f8c
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#define CYREG_SCB0_INTR_RX 0x40240fc0
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#define CYFLD_SCB_NOT_EMPTY__OFFSET 0x00000002
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#define CYFLD_SCB_NOT_EMPTY__SIZE 0x00000001
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#define CYFLD_SCB_FULL__OFFSET 0x00000003
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#define CYFLD_SCB_FULL__SIZE 0x00000001
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#define CYFLD_SCB_FRAME_ERROR__OFFSET 0x00000008
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#define CYFLD_SCB_FRAME_ERROR__SIZE 0x00000001
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#define CYFLD_SCB_PARITY_ERROR__OFFSET 0x00000009
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#define CYFLD_SCB_PARITY_ERROR__SIZE 0x00000001
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#define CYFLD_SCB_BAUD_DETECT__OFFSET 0x0000000a
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#define CYFLD_SCB_BAUD_DETECT__SIZE 0x00000001
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#define CYFLD_SCB_BREAK_DETECT__OFFSET 0x0000000b
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#define CYFLD_SCB_BREAK_DETECT__SIZE 0x00000001
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#define CYREG_SCB0_INTR_RX_SET 0x40240fc4
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#define CYREG_SCB0_INTR_RX_MASK 0x40240fc8
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#define CYREG_SCB0_INTR_RX_MASKED 0x40240fcc
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#define CYDEV_SCB1_BASE 0x40250000
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#define CYDEV_SCB1_SIZE 0x00010000
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#define CYREG_SCB1_CTRL 0x40250000
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#define CYREG_SCB1_STATUS 0x40250004
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#define CYREG_SCB1_SPI_CTRL 0x40250020
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#define CYREG_SCB1_SPI_STATUS 0x40250024
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#define CYREG_SCB1_UART_CTRL 0x40250040
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#define CYREG_SCB1_UART_TX_CTRL 0x40250044
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#define CYREG_SCB1_UART_RX_CTRL 0x40250048
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#define CYREG_SCB1_UART_RX_STATUS 0x4025004c
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#define CYREG_SCB1_UART_FLOW_CTRL 0x40250050
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#define CYREG_SCB1_I2C_CTRL 0x40250060
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#define CYREG_SCB1_I2C_STATUS 0x40250064
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#define CYREG_SCB1_I2C_M_CMD 0x40250068
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#define CYREG_SCB1_I2C_S_CMD 0x4025006c
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#define CYREG_SCB1_I2C_CFG 0x40250070
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#define CYREG_SCB1_TX_CTRL 0x40250200
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#define CYREG_SCB1_TX_FIFO_CTRL 0x40250204
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#define CYREG_SCB1_TX_FIFO_STATUS 0x40250208
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#define CYREG_SCB1_TX_FIFO_WR 0x40250240
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#define CYREG_SCB1_RX_CTRL 0x40250300
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#define CYREG_SCB1_RX_FIFO_CTRL 0x40250304
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#define CYREG_SCB1_RX_FIFO_STATUS 0x40250308
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#define CYREG_SCB1_RX_MATCH 0x40250310
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#define CYREG_SCB1_RX_FIFO_RD 0x40250340
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#define CYREG_SCB1_RX_FIFO_RD_SILENT 0x40250344
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#define CYREG_SCB1_EZ_DATA0 0x40250400
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#define CYREG_SCB1_EZ_DATA1 0x40250404
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#define CYREG_SCB1_EZ_DATA2 0x40250408
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#define CYREG_SCB1_EZ_DATA3 0x4025040c
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#define CYREG_SCB1_EZ_DATA4 0x40250410
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#define CYREG_SCB1_EZ_DATA5 0x40250414
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#define CYREG_SCB1_EZ_DATA6 0x40250418
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#define CYREG_SCB1_EZ_DATA7 0x4025041c
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#define CYREG_SCB1_EZ_DATA8 0x40250420
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#define CYREG_SCB1_EZ_DATA9 0x40250424
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#define CYREG_SCB1_EZ_DATA10 0x40250428
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#define CYREG_SCB1_EZ_DATA11 0x4025042c
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#define CYREG_SCB1_EZ_DATA12 0x40250430
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#define CYREG_SCB1_EZ_DATA13 0x40250434
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#define CYREG_SCB1_EZ_DATA14 0x40250438
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#define CYREG_SCB1_EZ_DATA15 0x4025043c
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#define CYREG_SCB1_EZ_DATA16 0x40250440
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#define CYREG_SCB1_EZ_DATA17 0x40250444
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#define CYREG_SCB1_EZ_DATA18 0x40250448
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#define CYREG_SCB1_EZ_DATA19 0x4025044c
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#define CYREG_SCB1_EZ_DATA20 0x40250450
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#define CYREG_SCB1_EZ_DATA21 0x40250454
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#define CYREG_SCB1_EZ_DATA22 0x40250458
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|
#define CYREG_SCB1_EZ_DATA23 0x4025045c
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#define CYREG_SCB1_EZ_DATA24 0x40250460
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|
#define CYREG_SCB1_EZ_DATA25 0x40250464
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|
#define CYREG_SCB1_EZ_DATA26 0x40250468
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|
#define CYREG_SCB1_EZ_DATA27 0x4025046c
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|
#define CYREG_SCB1_EZ_DATA28 0x40250470
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#define CYREG_SCB1_EZ_DATA29 0x40250474
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|
#define CYREG_SCB1_EZ_DATA30 0x40250478
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|
#define CYREG_SCB1_EZ_DATA31 0x4025047c
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|
#define CYREG_SCB1_INTR_CAUSE 0x40250e00
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#define CYREG_SCB1_INTR_I2C_EC 0x40250e80
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|
#define CYREG_SCB1_INTR_I2C_EC_MASK 0x40250e88
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|
#define CYREG_SCB1_INTR_I2C_EC_MASKED 0x40250e8c
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|
#define CYREG_SCB1_INTR_SPI_EC 0x40250ec0
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#define CYREG_SCB1_INTR_SPI_EC_MASK 0x40250ec8
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#define CYREG_SCB1_INTR_SPI_EC_MASKED 0x40250ecc
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#define CYREG_SCB1_INTR_M 0x40250f00
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#define CYREG_SCB1_INTR_M_SET 0x40250f04
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#define CYREG_SCB1_INTR_M_MASK 0x40250f08
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|
#define CYREG_SCB1_INTR_M_MASKED 0x40250f0c
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|
#define CYREG_SCB1_INTR_S 0x40250f40
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|
#define CYREG_SCB1_INTR_S_SET 0x40250f44
|
|
#define CYREG_SCB1_INTR_S_MASK 0x40250f48
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|
#define CYREG_SCB1_INTR_S_MASKED 0x40250f4c
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|
#define CYREG_SCB1_INTR_TX 0x40250f80
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|
#define CYREG_SCB1_INTR_TX_SET 0x40250f84
|
|
#define CYREG_SCB1_INTR_TX_MASK 0x40250f88
|
|
#define CYREG_SCB1_INTR_TX_MASKED 0x40250f8c
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|
#define CYREG_SCB1_INTR_RX 0x40250fc0
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|
#define CYREG_SCB1_INTR_RX_SET 0x40250fc4
|
|
#define CYREG_SCB1_INTR_RX_MASK 0x40250fc8
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|
#define CYREG_SCB1_INTR_RX_MASKED 0x40250fcc
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|
#define CYDEV_CSD_BASE 0x40280000
|
|
#define CYDEV_CSD_SIZE 0x00010000
|
|
#define CYREG_CSD_ID 0x40280000
|
|
#define CYFLD_CSD_ID__OFFSET 0x00000000
|
|
#define CYFLD_CSD_ID__SIZE 0x00000010
|
|
#define CYFLD_CSD_REVISION__OFFSET 0x00000010
|
|
#define CYFLD_CSD_REVISION__SIZE 0x00000010
|
|
#define CYREG_CSD_CONFIG 0x40280004
|
|
#define CYFLD_CSD_DSI_SAMPLE_EN__OFFSET 0x00000000
|
|
#define CYFLD_CSD_DSI_SAMPLE_EN__SIZE 0x00000001
|
|
#define CYFLD_CSD_SAMPLE_SYNC__OFFSET 0x00000001
|
|
#define CYFLD_CSD_SAMPLE_SYNC__SIZE 0x00000001
|
|
#define CYFLD_CSD_BYPASS_SEL__OFFSET 0x00000002
|
|
#define CYFLD_CSD_BYPASS_SEL__SIZE 0x00000001
|
|
#define CYVAL_CSD_BYPASS_SEL_PRS_OR_DIV2 0x00000000
|
|
#define CYVAL_CSD_BYPASS_SEL_DIRECT_CLOCK 0x00000001
|
|
#define CYFLD_CSD_FILTER_ENABLE__OFFSET 0x00000003
|
|
#define CYFLD_CSD_FILTER_ENABLE__SIZE 0x00000001
|
|
#define CYVAL_CSD_FILTER_ENABLE_FILTER_OFF 0x00000000
|
|
#define CYVAL_CSD_FILTER_ENABLE_FILTER_ON 0x00000001
|
|
#define CYFLD_CSD_DUAL_CAP_EN__OFFSET 0x00000004
|
|
#define CYFLD_CSD_DUAL_CAP_EN__SIZE 0x00000001
|
|
#define CYVAL_CSD_DUAL_CAP_EN_DISABLE 0x00000000
|
|
#define CYVAL_CSD_DUAL_CAP_EN_ENABLE 0x00000001
|
|
#define CYFLD_CSD_PRS_CLEAR__OFFSET 0x00000005
|
|
#define CYFLD_CSD_PRS_CLEAR__SIZE 0x00000001
|
|
#define CYFLD_CSD_PRS_SELECT__OFFSET 0x00000006
|
|
#define CYFLD_CSD_PRS_SELECT__SIZE 0x00000001
|
|
#define CYVAL_CSD_PRS_SELECT_DIV2 0x00000000
|
|
#define CYVAL_CSD_PRS_SELECT_PRS 0x00000001
|
|
#define CYFLD_CSD_PRS_12_8__OFFSET 0x00000007
|
|
#define CYFLD_CSD_PRS_12_8__SIZE 0x00000001
|
|
#define CYVAL_CSD_PRS_12_8_8B 0x00000000
|
|
#define CYVAL_CSD_PRS_12_8_12B 0x00000001
|
|
#define CYFLD_CSD_DSI_SENSE_EN__OFFSET 0x00000008
|
|
#define CYFLD_CSD_DSI_SENSE_EN__SIZE 0x00000001
|
|
#define CYFLD_CSD_SHIELD_DELAY__OFFSET 0x00000009
|
|
#define CYFLD_CSD_SHIELD_DELAY__SIZE 0x00000002
|
|
#define CYVAL_CSD_SHIELD_DELAY_OFF 0x00000000
|
|
#define CYVAL_CSD_SHIELD_DELAY_50NS 0x00000002
|
|
#define CYVAL_CSD_SHIELD_DELAY_10NS 0x00000003
|
|
#define CYFLD_CSD_SENSE_COMP_BW__OFFSET 0x0000000b
|
|
#define CYFLD_CSD_SENSE_COMP_BW__SIZE 0x00000001
|
|
#define CYVAL_CSD_SENSE_COMP_BW_LOW 0x00000000
|
|
#define CYVAL_CSD_SENSE_COMP_BW_HIGH 0x00000001
|
|
#define CYFLD_CSD_SENSE_EN__OFFSET 0x0000000c
|
|
#define CYFLD_CSD_SENSE_EN__SIZE 0x00000001
|
|
#define CYFLD_CSD_REFBUF_EN__OFFSET 0x0000000d
|
|
#define CYFLD_CSD_REFBUF_EN__SIZE 0x00000001
|
|
#define CYFLD_CSD_COMP_MODE__OFFSET 0x0000000e
|
|
#define CYFLD_CSD_COMP_MODE__SIZE 0x00000001
|
|
#define CYVAL_CSD_COMP_MODE_CHARGE_BUF 0x00000000
|
|
#define CYVAL_CSD_COMP_MODE_CHARGE_IO 0x00000001
|
|
#define CYFLD_CSD_COMP_PIN__OFFSET 0x0000000f
|
|
#define CYFLD_CSD_COMP_PIN__SIZE 0x00000001
|
|
#define CYVAL_CSD_COMP_PIN_CHANNEL1 0x00000000
|
|
#define CYVAL_CSD_COMP_PIN_CHANNEL2 0x00000001
|
|
#define CYFLD_CSD_POLARITY__OFFSET 0x00000010
|
|
#define CYFLD_CSD_POLARITY__SIZE 0x00000001
|
|
#define CYVAL_CSD_POLARITY_VSSIO 0x00000000
|
|
#define CYVAL_CSD_POLARITY_VDDIO 0x00000001
|
|
#define CYFLD_CSD_POLARITY2__OFFSET 0x00000011
|
|
#define CYFLD_CSD_POLARITY2__SIZE 0x00000001
|
|
#define CYVAL_CSD_POLARITY2_VSSIO 0x00000000
|
|
#define CYVAL_CSD_POLARITY2_VDDIO 0x00000001
|
|
#define CYFLD_CSD_MUTUAL_CAP__OFFSET 0x00000012
|
|
#define CYFLD_CSD_MUTUAL_CAP__SIZE 0x00000001
|
|
#define CYVAL_CSD_MUTUAL_CAP_SELFCAP 0x00000000
|
|
#define CYVAL_CSD_MUTUAL_CAP_MUTUALCAP 0x00000001
|
|
#define CYFLD_CSD_SENSE_COMP_EN__OFFSET 0x00000013
|
|
#define CYFLD_CSD_SENSE_COMP_EN__SIZE 0x00000001
|
|
#define CYFLD_CSD_REBUF_OUTSEL__OFFSET 0x00000015
|
|
#define CYFLD_CSD_REBUF_OUTSEL__SIZE 0x00000001
|
|
#define CYVAL_CSD_REBUF_OUTSEL_AMUXA 0x00000000
|
|
#define CYVAL_CSD_REBUF_OUTSEL_AMUXB 0x00000001
|
|
#define CYFLD_CSD_SENSE_INSEL__OFFSET 0x00000016
|
|
#define CYFLD_CSD_SENSE_INSEL__SIZE 0x00000001
|
|
#define CYVAL_CSD_SENSE_INSEL_SENSE_CHANNEL1 0x00000000
|
|
#define CYVAL_CSD_SENSE_INSEL_SENSE_AMUXA 0x00000001
|
|
#define CYFLD_CSD_REFBUF_DRV__OFFSET 0x00000017
|
|
#define CYFLD_CSD_REFBUF_DRV__SIZE 0x00000002
|
|
#define CYVAL_CSD_REFBUF_DRV_OFF 0x00000000
|
|
#define CYVAL_CSD_REFBUF_DRV_DRV_1 0x00000001
|
|
#define CYVAL_CSD_REFBUF_DRV_DRV_2 0x00000002
|
|
#define CYVAL_CSD_REFBUF_DRV_DRV_3 0x00000003
|
|
#define CYFLD_CSD_DDFTSEL__OFFSET 0x0000001a
|
|
#define CYFLD_CSD_DDFTSEL__SIZE 0x00000003
|
|
#define CYVAL_CSD_DDFTSEL_NORMAL 0x00000000
|
|
#define CYVAL_CSD_DDFTSEL_CSD_SENSE 0x00000001
|
|
#define CYVAL_CSD_DDFTSEL_CSD_SHIELD 0x00000002
|
|
#define CYVAL_CSD_DDFTSEL_CLK_SAMPLE 0x00000003
|
|
#define CYVAL_CSD_DDFTSEL_COMP_OUT 0x00000004
|
|
#define CYFLD_CSD_ADFTEN__OFFSET 0x0000001d
|
|
#define CYFLD_CSD_ADFTEN__SIZE 0x00000001
|
|
#define CYFLD_CSD_DDFTCOMP__OFFSET 0x0000001e
|
|
#define CYFLD_CSD_DDFTCOMP__SIZE 0x00000001
|
|
#define CYVAL_CSD_DDFTCOMP_REFBUFCOMP 0x00000000
|
|
#define CYVAL_CSD_DDFTCOMP_SENSECOMP 0x00000001
|
|
#define CYFLD_CSD_ENABLE__OFFSET 0x0000001f
|
|
#define CYFLD_CSD_ENABLE__SIZE 0x00000001
|
|
#define CYREG_CSD_IDAC 0x40280008
|
|
#define CYFLD_CSD_IDAC1__OFFSET 0x00000000
|
|
#define CYFLD_CSD_IDAC1__SIZE 0x00000008
|
|
#define CYFLD_CSD_IDAC1_MODE__OFFSET 0x00000008
|
|
#define CYFLD_CSD_IDAC1_MODE__SIZE 0x00000002
|
|
#define CYVAL_CSD_IDAC1_MODE_OFF 0x00000000
|
|
#define CYVAL_CSD_IDAC1_MODE_FIXED 0x00000001
|
|
#define CYVAL_CSD_IDAC1_MODE_VARIABLE 0x00000002
|
|
#define CYVAL_CSD_IDAC1_MODE_DSI 0x00000003
|
|
#define CYFLD_CSD_IDAC1_RANGE__OFFSET 0x0000000a
|
|
#define CYFLD_CSD_IDAC1_RANGE__SIZE 0x00000001
|
|
#define CYVAL_CSD_IDAC1_RANGE_4X 0x00000000
|
|
#define CYVAL_CSD_IDAC1_RANGE_8X 0x00000001
|
|
#define CYFLD_CSD_POLARITY1_MIR__OFFSET 0x0000000c
|
|
#define CYFLD_CSD_POLARITY1_MIR__SIZE 0x00000001
|
|
#define CYFLD_CSD_IDAC2__OFFSET 0x00000010
|
|
#define CYFLD_CSD_IDAC2__SIZE 0x00000007
|
|
#define CYFLD_CSD_IDAC2_MODE__OFFSET 0x00000018
|
|
#define CYFLD_CSD_IDAC2_MODE__SIZE 0x00000002
|
|
#define CYVAL_CSD_IDAC2_MODE_OFF 0x00000000
|
|
#define CYVAL_CSD_IDAC2_MODE_FIXED 0x00000001
|
|
#define CYVAL_CSD_IDAC2_MODE_VARIABLE 0x00000002
|
|
#define CYVAL_CSD_IDAC2_MODE_DSI 0x00000003
|
|
#define CYFLD_CSD_IDAC2_RANGE__OFFSET 0x0000001a
|
|
#define CYFLD_CSD_IDAC2_RANGE__SIZE 0x00000001
|
|
#define CYVAL_CSD_IDAC2_RANGE_4X 0x00000000
|
|
#define CYVAL_CSD_IDAC2_RANGE_8X 0x00000001
|
|
#define CYFLD_CSD_POLARITY2_MIR__OFFSET 0x0000001c
|
|
#define CYFLD_CSD_POLARITY2_MIR__SIZE 0x00000001
|
|
#define CYFLD_CSD_FEEDBACK_MODE__OFFSET 0x0000001e
|
|
#define CYFLD_CSD_FEEDBACK_MODE__SIZE 0x00000001
|
|
#define CYVAL_CSD_FEEDBACK_MODE_FLOP 0x00000000
|
|
#define CYVAL_CSD_FEEDBACK_MODE_COMP 0x00000001
|
|
#define CYREG_CSD_COUNTER 0x4028000c
|
|
#define CYFLD_CSD_COUNTER__OFFSET 0x00000000
|
|
#define CYFLD_CSD_COUNTER__SIZE 0x00000010
|
|
#define CYFLD_CSD_PERIOD__OFFSET 0x00000010
|
|
#define CYFLD_CSD_PERIOD__SIZE 0x00000010
|
|
#define CYREG_CSD_STATUS 0x40280010
|
|
#define CYFLD_CSD_CSD_CHARGE__OFFSET 0x00000000
|
|
#define CYFLD_CSD_CSD_CHARGE__SIZE 0x00000001
|
|
#define CYFLD_CSD_CSD_SENSE__OFFSET 0x00000001
|
|
#define CYFLD_CSD_CSD_SENSE__SIZE 0x00000001
|
|
#define CYFLD_CSD_COMP_OUT__OFFSET 0x00000002
|
|
#define CYFLD_CSD_COMP_OUT__SIZE 0x00000001
|
|
#define CYVAL_CSD_COMP_OUT_C_LT_VREF 0x00000000
|
|
#define CYVAL_CSD_COMP_OUT_C_GT_VREF 0x00000001
|
|
#define CYFLD_CSD_SAMPLE__OFFSET 0x00000003
|
|
#define CYFLD_CSD_SAMPLE__SIZE 0x00000001
|
|
#define CYREG_CSD_INTR 0x40280014
|
|
#define CYFLD_CSD_CSD__OFFSET 0x00000000
|
|
#define CYFLD_CSD_CSD__SIZE 0x00000001
|
|
#define CYREG_CSD_INTR_SET 0x40280018
|
|
#define CYREG_CSD_PWM 0x4028001c
|
|
#define CYFLD_CSD_PWM_COUNT__OFFSET 0x00000000
|
|
#define CYFLD_CSD_PWM_COUNT__SIZE 0x00000004
|
|
#define CYFLD_CSD_PWM_SEL__OFFSET 0x00000004
|
|
#define CYFLD_CSD_PWM_SEL__SIZE 0x00000002
|
|
#define CYVAL_CSD_PWM_SEL_OFF 0x00000000
|
|
#define CYVAL_CSD_PWM_SEL_FIXED_HIGH 0x00000002
|
|
#define CYVAL_CSD_PWM_SEL_FIXED_LOW 0x00000003
|
|
#define CYREG_CSD_TRIM1 0x4028ff00
|
|
#define CYFLD_CSD_IDAC1_SRC_TRIM__OFFSET 0x00000000
|
|
#define CYFLD_CSD_IDAC1_SRC_TRIM__SIZE 0x00000004
|
|
#define CYFLD_CSD_IDAC2_SRC_TRIM__OFFSET 0x00000004
|
|
#define CYFLD_CSD_IDAC2_SRC_TRIM__SIZE 0x00000004
|
|
#define CYREG_CSD_TRIM2 0x4028ff04
|
|
#define CYFLD_CSD_IDAC1_SNK_TRIM__OFFSET 0x00000000
|
|
#define CYFLD_CSD_IDAC1_SNK_TRIM__SIZE 0x00000004
|
|
#define CYFLD_CSD_IDAC2_SNK_TRIM__OFFSET 0x00000004
|
|
#define CYFLD_CSD_IDAC2_SNK_TRIM__SIZE 0x00000004
|
|
#define CYDEV_LCD_BASE 0x402a0000
|
|
#define CYDEV_LCD_SIZE 0x00010000
|
|
#define CYREG_LCD_ID 0x402a0000
|
|
#define CYFLD_LCD_ID__OFFSET 0x00000000
|
|
#define CYFLD_LCD_ID__SIZE 0x00000010
|
|
#define CYFLD_LCD_REVISION__OFFSET 0x00000010
|
|
#define CYFLD_LCD_REVISION__SIZE 0x00000010
|
|
#define CYREG_LCD_DIVIDER 0x402a0004
|
|
#define CYFLD_LCD_SUBFR_DIV__OFFSET 0x00000000
|
|
#define CYFLD_LCD_SUBFR_DIV__SIZE 0x00000010
|
|
#define CYFLD_LCD_DEAD_DIV__OFFSET 0x00000010
|
|
#define CYFLD_LCD_DEAD_DIV__SIZE 0x00000010
|
|
#define CYREG_LCD_CONTROL 0x402a0008
|
|
#define CYFLD_LCD_LS_EN__OFFSET 0x00000000
|
|
#define CYFLD_LCD_LS_EN__SIZE 0x00000001
|
|
#define CYFLD_LCD_HS_EN__OFFSET 0x00000001
|
|
#define CYFLD_LCD_HS_EN__SIZE 0x00000001
|
|
#define CYFLD_LCD_LCD_MODE__OFFSET 0x00000002
|
|
#define CYFLD_LCD_LCD_MODE__SIZE 0x00000001
|
|
#define CYVAL_LCD_LCD_MODE_LS 0x00000000
|
|
#define CYVAL_LCD_LCD_MODE_HS 0x00000001
|
|
#define CYFLD_LCD_TYPE__OFFSET 0x00000003
|
|
#define CYFLD_LCD_TYPE__SIZE 0x00000001
|
|
#define CYVAL_LCD_TYPE_TYPE_A 0x00000000
|
|
#define CYVAL_LCD_TYPE_TYPE_B 0x00000001
|
|
#define CYFLD_LCD_OP_MODE__OFFSET 0x00000004
|
|
#define CYFLD_LCD_OP_MODE__SIZE 0x00000001
|
|
#define CYVAL_LCD_OP_MODE_PWM 0x00000000
|
|
#define CYVAL_LCD_OP_MODE_CORRELATION 0x00000001
|
|
#define CYFLD_LCD_BIAS__OFFSET 0x00000005
|
|
#define CYFLD_LCD_BIAS__SIZE 0x00000002
|
|
#define CYVAL_LCD_BIAS_HALF 0x00000000
|
|
#define CYVAL_LCD_BIAS_THIRD 0x00000001
|
|
#define CYVAL_LCD_BIAS_FOURTH 0x00000002
|
|
#define CYVAL_LCD_BIAS_FIFTH 0x00000003
|
|
#define CYFLD_LCD_COM_NUM__OFFSET 0x00000008
|
|
#define CYFLD_LCD_COM_NUM__SIZE 0x00000004
|
|
#define CYFLD_LCD_LS_EN_STAT__OFFSET 0x0000001f
|
|
#define CYFLD_LCD_LS_EN_STAT__SIZE 0x00000001
|
|
#define CYREG_LCD_DATA00 0x402a0100
|
|
#define CYFLD_LCD_DATA__OFFSET 0x00000000
|
|
#define CYFLD_LCD_DATA__SIZE 0x00000020
|
|
#define CYREG_LCD_DATA01 0x402a0104
|
|
#define CYREG_LCD_DATA02 0x402a0108
|
|
#define CYREG_LCD_DATA03 0x402a010c
|
|
#define CYREG_LCD_DATA04 0x402a0110
|
|
#define CYREG_LCD_DATA05 0x402a0114
|
|
#define CYREG_LCD_DATA06 0x402a0118
|
|
#define CYREG_LCD_DATA07 0x402a011c
|
|
#define CYDEV_LPCOMP_BASE 0x402b0000
|
|
#define CYDEV_LPCOMP_SIZE 0x00010000
|
|
#define CYREG_LPCOMP_ID 0x402b0000
|
|
#define CYFLD_LPCOMP_ID__OFFSET 0x00000000
|
|
#define CYFLD_LPCOMP_ID__SIZE 0x00000010
|
|
#define CYFLD_LPCOMP_REVISION__OFFSET 0x00000010
|
|
#define CYFLD_LPCOMP_REVISION__SIZE 0x00000010
|
|
#define CYREG_LPCOMP_CONFIG 0x402b0004
|
|
#define CYFLD_LPCOMP_MODE1__OFFSET 0x00000000
|
|
#define CYFLD_LPCOMP_MODE1__SIZE 0x00000002
|
|
#define CYVAL_LPCOMP_MODE1_SLOW 0x00000000
|
|
#define CYVAL_LPCOMP_MODE1_FAST 0x00000001
|
|
#define CYVAL_LPCOMP_MODE1_ULP 0x00000002
|
|
#define CYFLD_LPCOMP_HYST1__OFFSET 0x00000002
|
|
#define CYFLD_LPCOMP_HYST1__SIZE 0x00000001
|
|
#define CYFLD_LPCOMP_FILTER1__OFFSET 0x00000003
|
|
#define CYFLD_LPCOMP_FILTER1__SIZE 0x00000001
|
|
#define CYFLD_LPCOMP_INTTYPE1__OFFSET 0x00000004
|
|
#define CYFLD_LPCOMP_INTTYPE1__SIZE 0x00000002
|
|
#define CYVAL_LPCOMP_INTTYPE1_DISABLE 0x00000000
|
|
#define CYVAL_LPCOMP_INTTYPE1_RISING 0x00000001
|
|
#define CYVAL_LPCOMP_INTTYPE1_FALLING 0x00000002
|
|
#define CYVAL_LPCOMP_INTTYPE1_BOTH 0x00000003
|
|
#define CYFLD_LPCOMP_OUT1__OFFSET 0x00000006
|
|
#define CYFLD_LPCOMP_OUT1__SIZE 0x00000001
|
|
#define CYFLD_LPCOMP_ENABLE1__OFFSET 0x00000007
|
|
#define CYFLD_LPCOMP_ENABLE1__SIZE 0x00000001
|
|
#define CYFLD_LPCOMP_MODE2__OFFSET 0x00000008
|
|
#define CYFLD_LPCOMP_MODE2__SIZE 0x00000002
|
|
#define CYVAL_LPCOMP_MODE2_SLOW 0x00000000
|
|
#define CYVAL_LPCOMP_MODE2_FAST 0x00000001
|
|
#define CYVAL_LPCOMP_MODE2_ULP 0x00000002
|
|
#define CYFLD_LPCOMP_HYST2__OFFSET 0x0000000a
|
|
#define CYFLD_LPCOMP_HYST2__SIZE 0x00000001
|
|
#define CYFLD_LPCOMP_FILTER2__OFFSET 0x0000000b
|
|
#define CYFLD_LPCOMP_FILTER2__SIZE 0x00000001
|
|
#define CYFLD_LPCOMP_INTTYPE2__OFFSET 0x0000000c
|
|
#define CYFLD_LPCOMP_INTTYPE2__SIZE 0x00000002
|
|
#define CYVAL_LPCOMP_INTTYPE2_DISABLE 0x00000000
|
|
#define CYVAL_LPCOMP_INTTYPE2_RISING 0x00000001
|
|
#define CYVAL_LPCOMP_INTTYPE2_FALLING 0x00000002
|
|
#define CYVAL_LPCOMP_INTTYPE2_BOTH 0x00000003
|
|
#define CYFLD_LPCOMP_OUT2__OFFSET 0x0000000e
|
|
#define CYFLD_LPCOMP_OUT2__SIZE 0x00000001
|
|
#define CYFLD_LPCOMP_ENABLE2__OFFSET 0x0000000f
|
|
#define CYFLD_LPCOMP_ENABLE2__SIZE 0x00000001
|
|
#define CYFLD_LPCOMP_DSI_BYPASS1__OFFSET 0x00000010
|
|
#define CYFLD_LPCOMP_DSI_BYPASS1__SIZE 0x00000001
|
|
#define CYFLD_LPCOMP_DSI_LEVEL1__OFFSET 0x00000011
|
|
#define CYFLD_LPCOMP_DSI_LEVEL1__SIZE 0x00000001
|
|
#define CYFLD_LPCOMP_DSI_BYPASS2__OFFSET 0x00000014
|
|
#define CYFLD_LPCOMP_DSI_BYPASS2__SIZE 0x00000001
|
|
#define CYFLD_LPCOMP_DSI_LEVEL2__OFFSET 0x00000015
|
|
#define CYFLD_LPCOMP_DSI_LEVEL2__SIZE 0x00000001
|
|
#define CYREG_LPCOMP_DFT 0x402b0008
|
|
#define CYFLD_LPCOMP_CAL_EN__OFFSET 0x00000000
|
|
#define CYFLD_LPCOMP_CAL_EN__SIZE 0x00000001
|
|
#define CYFLD_LPCOMP_BYPASS__OFFSET 0x00000001
|
|
#define CYFLD_LPCOMP_BYPASS__SIZE 0x00000001
|
|
#define CYREG_LPCOMP_INTR 0x402b0010
|
|
#define CYFLD_LPCOMP_COMP1__OFFSET 0x00000000
|
|
#define CYFLD_LPCOMP_COMP1__SIZE 0x00000001
|
|
#define CYFLD_LPCOMP_COMP2__OFFSET 0x00000001
|
|
#define CYFLD_LPCOMP_COMP2__SIZE 0x00000001
|
|
#define CYREG_LPCOMP_INTR_SET 0x402b0014
|
|
#define CYREG_LPCOMP_INTR_MASK 0x402b0018
|
|
#define CYFLD_LPCOMP_COMP1_MASK__OFFSET 0x00000000
|
|
#define CYFLD_LPCOMP_COMP1_MASK__SIZE 0x00000001
|
|
#define CYFLD_LPCOMP_COMP2_MASK__OFFSET 0x00000001
|
|
#define CYFLD_LPCOMP_COMP2_MASK__SIZE 0x00000001
|
|
#define CYREG_LPCOMP_INTR_MASKED 0x402b001c
|
|
#define CYFLD_LPCOMP_COMP1_MASKED__OFFSET 0x00000000
|
|
#define CYFLD_LPCOMP_COMP1_MASKED__SIZE 0x00000001
|
|
#define CYFLD_LPCOMP_COMP2_MASKED__OFFSET 0x00000001
|
|
#define CYFLD_LPCOMP_COMP2_MASKED__SIZE 0x00000001
|
|
#define CYREG_LPCOMP_TRIM1 0x402bff00
|
|
#define CYFLD_LPCOMP_COMP1_TRIMA__OFFSET 0x00000000
|
|
#define CYFLD_LPCOMP_COMP1_TRIMA__SIZE 0x00000005
|
|
#define CYREG_LPCOMP_TRIM2 0x402bff04
|
|
#define CYFLD_LPCOMP_COMP1_TRIMB__OFFSET 0x00000000
|
|
#define CYFLD_LPCOMP_COMP1_TRIMB__SIZE 0x00000005
|
|
#define CYREG_LPCOMP_TRIM3 0x402bff08
|
|
#define CYFLD_LPCOMP_COMP2_TRIMA__OFFSET 0x00000000
|
|
#define CYFLD_LPCOMP_COMP2_TRIMA__SIZE 0x00000005
|
|
#define CYREG_LPCOMP_TRIM4 0x402bff0c
|
|
#define CYFLD_LPCOMP_COMP2_TRIMB__OFFSET 0x00000000
|
|
#define CYFLD_LPCOMP_COMP2_TRIMB__SIZE 0x00000005
|
|
#define CYDEV_BLE_BASE 0x402e0000
|
|
#define CYDEV_BLE_SIZE 0x00010000
|
|
#define CYDEV_BLE_BLERD_BASE 0x402e0000
|
|
#define CYDEV_BLE_BLERD_SIZE 0x00000200
|
|
#define CYREG_BLE_BLERD_CFG1 0x402e0000
|
|
#define CYFLD_BLE_BLERD_RX_DATA_INVERSE__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_RX_DATA_INVERSE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_TX_DATA_INVERSE__OFFSET 0x00000001
|
|
#define CYFLD_BLE_BLERD_TX_DATA_INVERSE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_AGC_DISABLE__OFFSET 0x00000002
|
|
#define CYFLD_BLE_BLERD_AGC_DISABLE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_RF_PLL_DIRECT__OFFSET 0x00000003
|
|
#define CYFLD_BLE_BLERD_RF_PLL_DIRECT__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_CLKGATING_DISABLE__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLERD_CLKGATING_DISABLE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_EN_BR_CLK__OFFSET 0x00000005
|
|
#define CYFLD_BLE_BLERD_EN_BR_CLK__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_ADC_IQ_INVERSE__OFFSET 0x00000006
|
|
#define CYFLD_BLE_BLERD_ADC_IQ_INVERSE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_TX_PA_RAMP_MODE__OFFSET 0x00000007
|
|
#define CYFLD_BLE_BLERD_TX_PA_RAMP_MODE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_RADIO_STANDALONE__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLERD_RADIO_STANDALONE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_ADC_DC_CAPTURE_EN__OFFSET 0x00000009
|
|
#define CYFLD_BLE_BLERD_ADC_DC_CAPTURE_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_BURNIN_CLK_EN__OFFSET 0x0000000a
|
|
#define CYFLD_BLE_BLERD_BURNIN_CLK_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_CBPF_GAIN__OFFSET 0x0000000b
|
|
#define CYFLD_BLE_BLERD_CBPF_GAIN__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_LNA_GAIN__OFFSET 0x0000000d
|
|
#define CYFLD_BLE_BLERD_LNA_GAIN__SIZE 0x00000003
|
|
#define CYREG_BLE_BLERD_CFG2 0x402e0004
|
|
#define CYFLD_BLE_BLERD_DAC_REG_DATA__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_DAC_REG_DATA__SIZE 0x0000000a
|
|
#define CYFLD_BLE_BLERD_DAC_DFT_MODE__OFFSET 0x0000000a
|
|
#define CYFLD_BLE_BLERD_DAC_DFT_MODE__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_DAC_DFT_EN__OFFSET 0x0000000c
|
|
#define CYFLD_BLE_BLERD_DAC_DFT_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_ADC_DFT_MODE__OFFSET 0x0000000d
|
|
#define CYFLD_BLE_BLERD_ADC_DFT_MODE__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_ADC_DFT_EN__OFFSET 0x0000000f
|
|
#define CYFLD_BLE_BLERD_ADC_DFT_EN__SIZE 0x00000001
|
|
#define CYREG_BLE_BLERD_MODEM 0x402e0008
|
|
#define CYFLD_BLE_BLERD_NARROW_SPD__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_NARROW_SPD__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_WIDE_SPD__OFFSET 0x00000002
|
|
#define CYFLD_BLE_BLERD_WIDE_SPD__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_RST_CNT2_SEL__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLERD_RST_CNT2_SEL__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_RESET2_EN__OFFSET 0x00000005
|
|
#define CYFLD_BLE_BLERD_RESET2_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_DC_PARAM__OFFSET 0x00000006
|
|
#define CYFLD_BLE_BLERD_DC_PARAM__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_IMREJ_BYPASS__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLERD_IMREJ_BYPASS__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_ADC_FULL_SWING_DETECT_EN__OFFSET 0x00000009
|
|
#define CYFLD_BLE_BLERD_ADC_FULL_SWING_DETECT_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_DC_SCALING_EN__OFFSET 0x0000000a
|
|
#define CYFLD_BLE_BLERD_DC_SCALING_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_ADC_PWR_EST_EN__OFFSET 0x0000000b
|
|
#define CYFLD_BLE_BLERD_ADC_PWR_EST_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_LOAD_PREV_GAIN_EN__OFFSET 0x0000000c
|
|
#define CYFLD_BLE_BLERD_LOAD_PREV_GAIN_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_READ_DC_OFFSET_SEL__OFFSET 0x0000000d
|
|
#define CYFLD_BLE_BLERD_READ_DC_OFFSET_SEL__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_ADCDFT_SEL__OFFSET 0x0000000e
|
|
#define CYFLD_BLE_BLERD_ADCDFT_SEL__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_CW_MODE__OFFSET 0x0000000f
|
|
#define CYFLD_BLE_BLERD_CW_MODE__SIZE 0x00000001
|
|
#define CYREG_BLE_BLERD_FSM 0x402e000c
|
|
#define CYFLD_BLE_BLERD_XO_AMP_DETECT__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_XO_AMP_DETECT__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_LSLDO_OK__OFFSET 0x00000001
|
|
#define CYFLD_BLE_BLERD_LSLDO_OK__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_LFLDO_OK__OFFSET 0x00000002
|
|
#define CYFLD_BLE_BLERD_LFLDO_OK__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_FCAL_PASS_DETECT__OFFSET 0x00000003
|
|
#define CYFLD_BLE_BLERD_FCAL_PASS_DETECT__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_ISO_ENABLE__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLERD_ISO_ENABLE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_RX_STATE__OFFSET 0x00000005
|
|
#define CYFLD_BLE_BLERD_RX_STATE__SIZE 0x00000003
|
|
#define CYFLD_BLE_BLERD_TX_STATE__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLERD_TX_STATE__SIZE 0x00000003
|
|
#define CYFLD_BLE_BLERD_SY_STATE__OFFSET 0x0000000b
|
|
#define CYFLD_BLE_BLERD_SY_STATE__SIZE 0x00000003
|
|
#define CYFLD_BLE_BLERD_STATE__OFFSET 0x0000000e
|
|
#define CYFLD_BLE_BLERD_STATE__SIZE 0x00000002
|
|
#define CYREG_BLE_BLERD_DBUS 0x402e0010
|
|
#define CYFLD_BLE_BLERD_RF_FREQ__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_RF_FREQ__SIZE 0x0000000c
|
|
#define CYFLD_BLE_BLERD_DIRECT_RXEN__OFFSET 0x0000000c
|
|
#define CYFLD_BLE_BLERD_DIRECT_RXEN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_DIRECT_TXEN__OFFSET 0x0000000d
|
|
#define CYFLD_BLE_BLERD_DIRECT_TXEN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_ISOLATE_N__OFFSET 0x0000000e
|
|
#define CYFLD_BLE_BLERD_ISOLATE_N__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_XTAL_ENABLE__OFFSET 0x0000000f
|
|
#define CYFLD_BLE_BLERD_XTAL_ENABLE__SIZE 0x00000001
|
|
#define CYREG_BLE_BLERD_CFGCTRL 0x402e0014
|
|
#define CYFLD_BLE_BLERD_DSM_MODE__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_DSM_MODE__SIZE 0x00000005
|
|
#define CYFLD_BLE_BLERD_IGNORE_FRAC__OFFSET 0x00000005
|
|
#define CYFLD_BLE_BLERD_IGNORE_FRAC__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_DCCAL_RERUN__OFFSET 0x00000006
|
|
#define CYFLD_BLE_BLERD_DCCAL_RERUN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_DCCAL_MODE__OFFSET 0x00000007
|
|
#define CYFLD_BLE_BLERD_DCCAL_MODE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_RCCAL_RERUN__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLERD_RCCAL_RERUN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_RCCAL_MODE__OFFSET 0x00000009
|
|
#define CYFLD_BLE_BLERD_RCCAL_MODE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_KVCAL_RERUN__OFFSET 0x0000000a
|
|
#define CYFLD_BLE_BLERD_KVCAL_RERUN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_FCAL_RERUN__OFFSET 0x0000000b
|
|
#define CYFLD_BLE_BLERD_FCAL_RERUN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_TESTMODE_EN__OFFSET 0x0000000f
|
|
#define CYFLD_BLE_BLERD_TESTMODE_EN__SIZE 0x00000001
|
|
#define CYREG_BLE_BLERD_RSSI 0x402e0018
|
|
#define CYFLD_BLE_BLERD_PREFILT__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_PREFILT__SIZE 0x00000007
|
|
#define CYFLD_BLE_BLERD_POSTFILT__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLERD_POSTFILT__SIZE 0x00000007
|
|
#define CYREG_BLE_BLERD_RMAP 0x402e0024
|
|
#define CYFLD_BLE_BLERD_BB_BYPASS__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_BB_BYPASS__SIZE 0x00000010
|
|
#define CYREG_BLE_BLERD_KVCAL 0x402e0028
|
|
#define CYFLD_BLE_BLERD_DAC_STEP__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_DAC_STEP__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_RUN_DURATION__OFFSET 0x00000002
|
|
#define CYFLD_BLE_BLERD_RUN_DURATION__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_EXP_FREQ_DIFF__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLERD_EXP_FREQ_DIFF__SIZE 0x00000008
|
|
#define CYREG_BLE_BLERD_CFG_1_FCAL 0x402e002c
|
|
#define CYFLD_BLE_BLERD_COARSE_FRAMES_6__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_COARSE_FRAMES_6__SIZE 0x00000007
|
|
#define CYFLD_BLE_BLERD_COARSE_FRAMES_7__OFFSET 0x00000007
|
|
#define CYFLD_BLE_BLERD_COARSE_FRAMES_7__SIZE 0x00000007
|
|
#define CYREG_BLE_BLERD_CFG_2_FCAL 0x402e0030
|
|
#define CYFLD_BLE_BLERD_COARSE_FRAMES_4__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_COARSE_FRAMES_4__SIZE 0x00000007
|
|
#define CYFLD_BLE_BLERD_COARSE_FRAMES_5__OFFSET 0x00000007
|
|
#define CYFLD_BLE_BLERD_COARSE_FRAMES_5__SIZE 0x00000007
|
|
#define CYREG_BLE_BLERD_CFG_3_FCAL 0x402e0034
|
|
#define CYFLD_BLE_BLERD_COARSE_FRAMES_2__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_COARSE_FRAMES_2__SIZE 0x00000007
|
|
#define CYFLD_BLE_BLERD_COARSE_FRAMES_3__OFFSET 0x00000007
|
|
#define CYFLD_BLE_BLERD_COARSE_FRAMES_3__SIZE 0x00000007
|
|
#define CYREG_BLE_BLERD_CFG_4_FCAL 0x402e0038
|
|
#define CYFLD_BLE_BLERD_COARSE_FRAMES_0__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_COARSE_FRAMES_0__SIZE 0x00000007
|
|
#define CYFLD_BLE_BLERD_COARSE_FRAMES_1__OFFSET 0x00000007
|
|
#define CYFLD_BLE_BLERD_COARSE_FRAMES_1__SIZE 0x00000007
|
|
#define CYREG_BLE_BLERD_CFG_5_FCAL 0x402e003c
|
|
#define CYFLD_BLE_BLERD_FINE_FRAMES__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_FINE_FRAMES__SIZE 0x00000007
|
|
#define CYFLD_BLE_BLERD_CNT_SEL__OFFSET 0x00000007
|
|
#define CYFLD_BLE_BLERD_CNT_SEL__SIZE 0x00000004
|
|
#define CYREG_BLE_BLERD_CFG_6_FCAL 0x402e0040
|
|
#define CYFLD_BLE_BLERD_FRAMES_VCO_OL__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_FRAMES_VCO_OL__SIZE 0x0000000b
|
|
#define CYFLD_BLE_BLERD_VCO_OL_ENBL__OFFSET 0x0000000b
|
|
#define CYFLD_BLE_BLERD_VCO_OL_ENBL__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_DRIFT_CHECK_EN__OFFSET 0x0000000c
|
|
#define CYFLD_BLE_BLERD_DRIFT_CHECK_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_DRIFT_CHECK__OFFSET 0x0000000d
|
|
#define CYFLD_BLE_BLERD_DRIFT_CHECK__SIZE 0x00000002
|
|
#define CYREG_BLE_BLERD_FCAL_TEST 0x402e0044
|
|
#define CYFLD_BLE_BLERD_FINE__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_FINE__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLERD_COARSE__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLERD_COARSE__SIZE 0x00000008
|
|
#define CYFLD_BLE_BLERD_MODE__OFFSET 0x0000000c
|
|
#define CYFLD_BLE_BLERD_MODE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_CNT_POLARITY__OFFSET 0x0000000d
|
|
#define CYFLD_BLE_BLERD_CNT_POLARITY__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_LOOP_POLARITY__OFFSET 0x0000000e
|
|
#define CYFLD_BLE_BLERD_LOOP_POLARITY__SIZE 0x00000001
|
|
#define CYREG_BLE_BLERD_TEST 0x402e0048
|
|
#define CYFLD_BLE_BLERD_KVCAL_GAIN__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_KVCAL_GAIN__SIZE 0x00000007
|
|
#define CYFLD_BLE_BLERD_KVCAL_MODE__OFFSET 0x00000007
|
|
#define CYFLD_BLE_BLERD_KVCAL_MODE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_FRCCAL_CODE__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLERD_FRCCAL_CODE__SIZE 0x00000005
|
|
#define CYFLD_BLE_BLERD_FRCCAL_MODE__OFFSET 0x0000000d
|
|
#define CYFLD_BLE_BLERD_FRCCAL_MODE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_FRCCAL_POLARITY__OFFSET 0x0000000e
|
|
#define CYFLD_BLE_BLERD_FRCCAL_POLARITY__SIZE 0x00000001
|
|
#define CYREG_BLE_BLERD_FPD_TEST 0x402e004c
|
|
#define CYFLD_BLE_BLERD_BB_FPUP_XO_BUF_ALL__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_BB_FPUP_XO_BUF_ALL__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_BB_XO_BUF_ADC__OFFSET 0x00000002
|
|
#define CYFLD_BLE_BLERD_BB_XO_BUF_ADC__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_BB_XO_BUF_SY__OFFSET 0x00000003
|
|
#define CYFLD_BLE_BLERD_BB_XO_BUF_SY__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_BB_RCCAL_BLOCK__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLERD_BB_RCCAL_BLOCK__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_FAST_CHARGE__OFFSET 0x00000007
|
|
#define CYFLD_BLE_BLERD_FAST_CHARGE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_SY_LDOVCO__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLERD_SY_LDOVCO__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_SY_LDOLOPATH__OFFSET 0x00000009
|
|
#define CYFLD_BLE_BLERD_SY_LDOLOPATH__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_SY_LDOFFFB__OFFSET 0x0000000a
|
|
#define CYFLD_BLE_BLERD_SY_LDOFFFB__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_BALUN_HFLDO__OFFSET 0x0000000b
|
|
#define CYFLD_BLE_BLERD_BALUN_HFLDO__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_BALUN_CTUNE__OFFSET 0x0000000c
|
|
#define CYFLD_BLE_BLERD_BALUN_CTUNE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_FPUP_ALL__OFFSET 0x0000000d
|
|
#define CYFLD_BLE_BLERD_FPUP_ALL__SIZE 0x00000001
|
|
#define CYREG_BLE_BLERD_SY 0x402e0050
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_IBIAS__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_IBIAS__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_VCO__OFFSET 0x00000001
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_VCO__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_DIV2__OFFSET 0x00000002
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_DIV2__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_LOPATHDIVN__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_LOPATHDIVN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_DIV2_BUF__OFFSET 0x00000005
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_DIV2_BUF__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_DIVN__OFFSET 0x00000006
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_DIVN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_FCAL__OFFSET 0x00000007
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_FCAL__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_CPLPF__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_CPLPF__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_LOPATHTX__OFFSET 0x00000009
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_LOPATHTX__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_DIV2_DRV__OFFSET 0x0000000a
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_DIV2_DRV__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_TX_POWERSAVE__OFFSET 0x0000000b
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_TX_POWERSAVE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_FCAL_AMP__OFFSET 0x0000000c
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_FCAL_AMP__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_OPENLOOP__OFFSET 0x0000000d
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_OPENLOOP__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_LOOP_FREEZE__OFFSET 0x0000000e
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_LOOP_FREEZE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_TEST_FPUP_ALL__OFFSET 0x0000000f
|
|
#define CYFLD_BLE_BLERD_TEST_FPUP_ALL__SIZE 0x00000001
|
|
#define CYREG_BLE_BLERD_TEST2_SY 0x402e0054
|
|
#define CYFLD_BLE_BLERD_ICP_CODE__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_ICP_CODE__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLERD_FPD_DSM_RUN__OFFSET 0x00000005
|
|
#define CYFLD_BLE_BLERD_FPD_DSM_RUN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_FORCE_DSM_RUN__OFFSET 0x00000006
|
|
#define CYFLD_BLE_BLERD_FORCE_DSM_RUN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_FORCE_DSM_FRAC__OFFSET 0x00000007
|
|
#define CYFLD_BLE_BLERD_FORCE_DSM_FRAC__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_DSM_FRAC__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLERD_DSM_FRAC__SIZE 0x00000008
|
|
#define CYREG_BLE_BLERD_TX 0x402e0058
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_DAC__OFFSET 0x00000001
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_DAC__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_LPF__OFFSET 0x00000002
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_LPF__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_DRIVER__OFFSET 0x00000003
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_DRIVER__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_PREDRIVER__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_PREDRIVER__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_FN_TXEN__OFFSET 0x00000005
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_FN_TXEN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_KVM_NFDEV__OFFSET 0x00000006
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_KVM_NFDEV__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_KVM_PFDEV__OFFSET 0x00000007
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_KVM_PFDEV__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_TEST_FPUP_TX_ALL__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLERD_TEST_FPUP_TX_ALL__SIZE 0x00000001
|
|
#define CYREG_BLE_BLERD_RX 0x402e005c
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_ADC_ICORE__OFFSET 0x00000001
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_ADC_ICORE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_ADC_IREFGEN__OFFSET 0x00000002
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_ADC_IREFGEN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_ADC_QCORE__OFFSET 0x00000003
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_ADC_QCORE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_ADC_QREFGEN__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_ADC_QREFGEN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_BPF__OFFSET 0x00000005
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_BPF__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_TIA__OFFSET 0x00000006
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_TIA__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_MIXER_LO__OFFSET 0x00000007
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_MIXER_LO__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_MIXER_RF__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_MIXER_RF__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_LNA__OFFSET 0x00000009
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_LNA__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_LNA_HIZ__OFFSET 0x0000000a
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_LNA_HIZ__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_FN_RXEN__OFFSET 0x0000000b
|
|
#define CYFLD_BLE_BLERD_TEST_FPD_FN_RXEN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_TEST_FPUP_RX_ALL__OFFSET 0x0000000c
|
|
#define CYFLD_BLE_BLERD_TEST_FPUP_RX_ALL__SIZE 0x00000001
|
|
#define CYREG_BLE_BLERD_DIAG1 0x402e0060
|
|
#define CYFLD_BLE_BLERD_DISABLE__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_DISABLE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_CODE__OFFSET 0x00000001
|
|
#define CYFLD_BLE_BLERD_CODE__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLERD_SEL__OFFSET 0x00000005
|
|
#define CYFLD_BLE_BLERD_SEL__SIZE 0x00000005
|
|
#define CYREG_BLE_BLERD_IM 0x402e0064
|
|
#define CYFLD_BLE_BLERD_DIAG_MON_DISABLE__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_DIAG_MON_DISABLE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_DIAG_MONI_CODE__OFFSET 0x00000001
|
|
#define CYFLD_BLE_BLERD_DIAG_MONI_CODE__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLERD_DIAG_INJ_DISABLE__OFFSET 0x00000005
|
|
#define CYFLD_BLE_BLERD_DIAG_INJ_DISABLE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_DIAG_INJ_CODE__OFFSET 0x00000006
|
|
#define CYFLD_BLE_BLERD_DIAG_INJ_CODE__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLERD_DIAG_LOOPBACK__OFFSET 0x0000000a
|
|
#define CYFLD_BLE_BLERD_DIAG_LOOPBACK__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_DIAG_BUMP__OFFSET 0x0000000b
|
|
#define CYFLD_BLE_BLERD_DIAG_BUMP__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLERD_DIAG_RESV__OFFSET 0x0000000f
|
|
#define CYFLD_BLE_BLERD_DIAG_RESV__SIZE 0x00000001
|
|
#define CYREG_BLE_BLERD_LDO_BYPASS 0x402e0068
|
|
#define CYFLD_BLE_BLERD_SYLDOVCO__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_SYLDOVCO__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_SYLDOLOPATH__OFFSET 0x00000001
|
|
#define CYFLD_BLE_BLERD_SYLDOLOPATH__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_SYLDOFFFB__OFFSET 0x00000002
|
|
#define CYFLD_BLE_BLERD_SYLDOFFFB__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_HFLDO__OFFSET 0x00000003
|
|
#define CYFLD_BLE_BLERD_HFLDO__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_RESV_LDOBP__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLERD_RESV_LDOBP__SIZE 0x0000000c
|
|
#define CYREG_BLE_BLERD_LDO 0x402e006c
|
|
#define CYFLD_BLE_BLERD_BUMP_BALUM_HF__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_BUMP_BALUM_HF__SIZE 0x00000003
|
|
#define CYFLD_BLE_BLERD_BUMP_SY_VCO__OFFSET 0x00000003
|
|
#define CYFLD_BLE_BLERD_BUMP_SY_VCO__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_BUMP_SY_LOPATH__OFFSET 0x00000005
|
|
#define CYFLD_BLE_BLERD_BUMP_SY_LOPATH__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_BUMP_SY_LHV__OFFSET 0x00000007
|
|
#define CYFLD_BLE_BLERD_BUMP_SY_LHV__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_BUMP_SY_FFFB__OFFSET 0x00000009
|
|
#define CYFLD_BLE_BLERD_BUMP_SY_FFFB__SIZE 0x00000003
|
|
#define CYFLD_BLE_BLERD_REV_LDO__OFFSET 0x0000000c
|
|
#define CYFLD_BLE_BLERD_REV_LDO__SIZE 0x00000004
|
|
#define CYREG_BLE_BLERD_BB_BUMP1 0x402e0070
|
|
#define CYFLD_BLE_BLERD_REFCORE_VDD__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_REFCORE_VDD__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_V2I_REG__OFFSET 0x00000002
|
|
#define CYFLD_BLE_BLERD_V2I_REG__SIZE 0x00000003
|
|
#define CYFLD_BLE_BLERD_LFLDO__OFFSET 0x00000005
|
|
#define CYFLD_BLE_BLERD_LFLDO__SIZE 0x00000003
|
|
#define CYFLD_BLE_BLERD_LSLDO__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLERD_LSLDO__SIZE 0x00000003
|
|
#define CYFLD_BLE_BLERD_REV_BBBUMP__OFFSET 0x0000000b
|
|
#define CYFLD_BLE_BLERD_REV_BBBUMP__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_FORCE_BGSTARTUP__OFFSET 0x0000000e
|
|
#define CYFLD_BLE_BLERD_FORCE_BGSTARTUP__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_FPD_REFORCE__OFFSET 0x0000000f
|
|
#define CYFLD_BLE_BLERD_FPD_REFORCE__SIZE 0x00000001
|
|
#define CYREG_BLE_BLERD_BB_BUMP2 0x402e0074
|
|
#define CYFLD_BLE_BLERD_V2I_RCAL__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_V2I_RCAL__SIZE 0x00000005
|
|
#define CYFLD_BLE_BLERD_V2I__OFFSET 0x00000005
|
|
#define CYFLD_BLE_BLERD_V2I__SIZE 0x00000005
|
|
#define CYFLD_BLE_BLERD_VBG_TRIM__OFFSET 0x0000000a
|
|
#define CYFLD_BLE_BLERD_VBG_TRIM__SIZE 0x00000003
|
|
#define CYFLD_BLE_BLERD_SY_IBIAS__OFFSET 0x0000000d
|
|
#define CYFLD_BLE_BLERD_SY_IBIAS__SIZE 0x00000003
|
|
#define CYREG_BLE_BLERD_BB_XO 0x402e0078
|
|
#define CYFLD_BLE_BLERD_DIS_XOCORE_SUPFILT__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_DIS_XOCORE_SUPFILT__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_EN_RE_FASTSTART__OFFSET 0x00000001
|
|
#define CYFLD_BLE_BLERD_EN_RE_FASTSTART__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_EN_CURMEAS__OFFSET 0x00000002
|
|
#define CYFLD_BLE_BLERD_EN_CURMEAS__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_EN_AMPDET_CURMEAS__OFFSET 0x00000003
|
|
#define CYFLD_BLE_BLERD_EN_AMPDET_CURMEAS__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_EN_AMPDET_FASTSTART__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLERD_EN_AMPDET_FASTSTART__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_CTRL_RC_FASTSTART_RES__OFFSET 0x00000005
|
|
#define CYFLD_BLE_BLERD_CTRL_RC_FASTSTART_RES__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_CTRL_VDDL_XO__OFFSET 0x00000007
|
|
#define CYFLD_BLE_BLERD_CTRL_VDDL_XO__SIZE 0x00000003
|
|
#define CYFLD_BLE_BLERD_CTRL_VDDL_XB__OFFSET 0x0000000a
|
|
#define CYFLD_BLE_BLERD_CTRL_VDDL_XB__SIZE 0x00000003
|
|
#define CYFLD_BLE_BLERD_CTRL_RPREF__OFFSET 0x0000000d
|
|
#define CYFLD_BLE_BLERD_CTRL_RPREF__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_rev_bb_xo__OFFSET 0x0000000f
|
|
#define CYFLD_BLE_BLERD_rev_bb_xo__SIZE 0x00000001
|
|
#define CYREG_BLE_BLERD_BB_XO_CAPTRIM 0x402e007c
|
|
#define CYFLD_BLE_BLERD_X2__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_X2__SIZE 0x00000008
|
|
#define CYFLD_BLE_BLERD_X1__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLERD_X1__SIZE 0x00000008
|
|
#define CYREG_BLE_BLERD_SY_BUMP1 0x402e0080
|
|
#define CYFLD_BLE_BLERD_VCO__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_VCO__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLERD_LOFB_POWERSAVE__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLERD_LOFB_POWERSAVE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_IBIAS_LOPATH__OFFSET 0x00000005
|
|
#define CYFLD_BLE_BLERD_IBIAS_LOPATH__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_LDOLO_FORCE_STARTUP__OFFSET 0x00000007
|
|
#define CYFLD_BLE_BLERD_LDOLO_FORCE_STARTUP__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_LOPATH__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLERD_LOPATH__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLERD_PDCPLPF__OFFSET 0x0000000c
|
|
#define CYFLD_BLE_BLERD_PDCPLPF__SIZE 0x00000004
|
|
#define CYREG_BLE_BLERD_SY_BUMP2 0x402e0084
|
|
#define CYFLD_BLE_BLERD_FCAL_BIAS_SEL__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_FCAL_BIAS_SEL__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_ACAP_BIAS_SEL__OFFSET 0x00000002
|
|
#define CYFLD_BLE_BLERD_ACAP_BIAS_SEL__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_ICP_XFACTOR__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLERD_ICP_XFACTOR__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_ICP_OFFSET__OFFSET 0x00000006
|
|
#define CYFLD_BLE_BLERD_ICP_OFFSET__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_CLKNC_MODE__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLERD_CLKNC_MODE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_PUP_MON__OFFSET 0x00000009
|
|
#define CYFLD_BLE_BLERD_PUP_MON__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_VCTRL_PULLDN__OFFSET 0x0000000a
|
|
#define CYFLD_BLE_BLERD_VCTRL_PULLDN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_VMOD_PULLDN__OFFSET 0x0000000b
|
|
#define CYFLD_BLE_BLERD_VMOD_PULLDN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_RST_DLY__OFFSET 0x0000000c
|
|
#define CYFLD_BLE_BLERD_RST_DLY__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_PDCP_OFFSET__OFFSET 0x0000000e
|
|
#define CYFLD_BLE_BLERD_PDCP_OFFSET__SIZE 0x00000002
|
|
#define CYREG_BLE_BLERD_TX_BUMP1 0x402e0088
|
|
#define CYFLD_BLE_BLERD_TX_DRIVER__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_TX_DRIVER__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLERD_SY_RST_DLY_TX__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLERD_SY_RST_DLY_TX__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_TX_LPF__OFFSET 0x00000006
|
|
#define CYFLD_BLE_BLERD_TX_LPF__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLERD_TX_VTXREF_PROG__OFFSET 0x0000000a
|
|
#define CYFLD_BLE_BLERD_TX_VTXREF_PROG__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLERD_SY_DIVN_TXPOWERSAVE__OFFSET 0x0000000e
|
|
#define CYFLD_BLE_BLERD_SY_DIVN_TXPOWERSAVE__SIZE 0x00000002
|
|
#define CYREG_BLE_BLERD_TX_BUMP2 0x402e008c
|
|
#define CYFLD_BLE_BLERD_DRV_AB_VBIAS__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_DRV_AB_VBIAS__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLERD_DRV_VCASCH__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLERD_DRV_VCASCH__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_SY_LDOBGREF_EN__OFFSET 0x00000006
|
|
#define CYFLD_BLE_BLERD_SY_LDOBGREF_EN__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_SY_ICP_OFFSET_TX__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLERD_SY_ICP_OFFSET_TX__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_DAC_RES__OFFSET 0x0000000a
|
|
#define CYFLD_BLE_BLERD_DAC_RES__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLERD_SY_CP_TXPOWERSAVE__OFFSET 0x0000000e
|
|
#define CYFLD_BLE_BLERD_SY_CP_TXPOWERSAVE__SIZE 0x00000002
|
|
#define CYREG_BLE_BLERD_RX_BUMP1 0x402e0090
|
|
#define CYFLD_BLE_BLERD_TIA__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_TIA__SIZE 0x00000003
|
|
#define CYFLD_BLE_BLERD_CBPF__OFFSET 0x00000003
|
|
#define CYFLD_BLE_BLERD_CBPF__SIZE 0x00000003
|
|
#define CYFLD_BLE_BLERD_IF_OFFSET_CALDAC__OFFSET 0x00000006
|
|
#define CYFLD_BLE_BLERD_IF_OFFSET_CALDAC__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_MIXER_VBIAS_SW__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLERD_MIXER_VBIAS_SW__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_MIXER__OFFSET 0x0000000a
|
|
#define CYFLD_BLE_BLERD_MIXER__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_LNA__OFFSET 0x0000000c
|
|
#define CYFLD_BLE_BLERD_LNA__SIZE 0x00000004
|
|
#define CYREG_BLE_BLERD_RX_BUMP2 0x402e0094
|
|
#define CYFLD_BLE_BLERD_LNA_IBIAS__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_LNA_IBIAS__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_TIA_IBIAS__OFFSET 0x00000002
|
|
#define CYFLD_BLE_BLERD_TIA_IBIAS__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_CBPF_IBIAS__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLERD_CBPF_IBIAS__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_IF_CM_IBIAS__OFFSET 0x00000006
|
|
#define CYFLD_BLE_BLERD_IF_CM_IBIAS__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_CBPF_HIZ_ENABLE__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLERD_CBPF_HIZ_ENABLE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_COMPLEX_DISABLE__OFFSET 0x00000009
|
|
#define CYFLD_BLE_BLERD_COMPLEX_DISABLE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_SY_R2HIGHMODE__OFFSET 0x0000000a
|
|
#define CYFLD_BLE_BLERD_SY_R2HIGHMODE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_SY_HILINEARITYR2_MODE__OFFSET 0x0000000b
|
|
#define CYFLD_BLE_BLERD_SY_HILINEARITYR2_MODE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_SY_LOWKVAMODE__OFFSET 0x0000000c
|
|
#define CYFLD_BLE_BLERD_SY_LOWKVAMODE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_SY_LOWKVMMODE__OFFSET 0x0000000d
|
|
#define CYFLD_BLE_BLERD_SY_LOWKVMMODE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_REV_RX_BUMP2__OFFSET 0x0000000e
|
|
#define CYFLD_BLE_BLERD_REV_RX_BUMP2__SIZE 0x00000002
|
|
#define CYREG_BLE_BLERD_ADC_BUMP1 0x402e0098
|
|
#define CYFLD_BLE_BLERD_I_REF__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_I_REF__SIZE 0x00000003
|
|
#define CYFLD_BLE_BLERD_Q_REF__OFFSET 0x00000003
|
|
#define CYFLD_BLE_BLERD_Q_REF__SIZE 0x00000003
|
|
#define CYFLD_BLE_BLERD_IBG_CAL__OFFSET 0x00000006
|
|
#define CYFLD_BLE_BLERD_IBG_CAL__SIZE 0x00000003
|
|
#define CYFLD_BLE_BLERD_LOOPDLY__OFFSET 0x00000009
|
|
#define CYFLD_BLE_BLERD_LOOPDLY__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_LOOPDLY4X_EN__OFFSET 0x0000000b
|
|
#define CYFLD_BLE_BLERD_LOOPDLY4X_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_LOWPOWER__OFFSET 0x0000000c
|
|
#define CYFLD_BLE_BLERD_LOWPOWER__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_OPAMP_BYPASS__OFFSET 0x0000000d
|
|
#define CYFLD_BLE_BLERD_OPAMP_BYPASS__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_BWCTRL__OFFSET 0x0000000e
|
|
#define CYFLD_BLE_BLERD_BWCTRL__SIZE 0x00000002
|
|
#define CYREG_BLE_BLERD_ADC_BUMP2 0x402e009c
|
|
#define CYFLD_BLE_BLERD_CYCLE_B2_DELAY__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_CYCLE_B2_DELAY__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_CYCLE_B5_DELAY__OFFSET 0x00000001
|
|
#define CYFLD_BLE_BLERD_CYCLE_B5_DELAY__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_DUTCYCLE_25__OFFSET 0x00000002
|
|
#define CYFLD_BLE_BLERD_DUTCYCLE_25__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_METADET_EN__OFFSET 0x00000003
|
|
#define CYFLD_BLE_BLERD_METADET_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_IBUMP__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLERD_IBUMP__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_PREAMP_SOURCECTRL_N__OFFSET 0x00000005
|
|
#define CYFLD_BLE_BLERD_PREAMP_SOURCECTRL_N__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_PREAMP_GAINCTRL_N__OFFSET 0x00000006
|
|
#define CYFLD_BLE_BLERD_PREAMP_GAINCTRL_N__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_SHORT_INPUT__OFFSET 0x00000007
|
|
#define CYFLD_BLE_BLERD_SHORT_INPUT__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_RETURN_SKEW__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLERD_RETURN_SKEW__SIZE 0x00000003
|
|
#define CYFLD_BLE_BLERD_IQSWAP__OFFSET 0x0000000b
|
|
#define CYFLD_BLE_BLERD_IQSWAP__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_PREAMP_BWCTRL__OFFSET 0x0000000c
|
|
#define CYFLD_BLE_BLERD_PREAMP_BWCTRL__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_REV_ADC_BUMP2__OFFSET 0x0000000e
|
|
#define CYFLD_BLE_BLERD_REV_ADC_BUMP2__SIZE 0x00000002
|
|
#define CYREG_BLE_BLERD_BALUN 0x402e00a0
|
|
#define CYFLD_BLE_BLERD_BUMP_RX_CTUNE__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_BUMP_RX_CTUNE__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLERD_BUMP_TX_CTUNE__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLERD_BUMP_TX_CTUNE__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLERD_BUMP_VTUNE__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLERD_BUMP_VTUNE__SIZE 0x00000003
|
|
#define CYFLD_BLE_BLERD_BUMP_RTUNE__OFFSET 0x0000000b
|
|
#define CYFLD_BLE_BLERD_BUMP_RTUNE__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_REV_BALUN__OFFSET 0x0000000d
|
|
#define CYFLD_BLE_BLERD_REV_BALUN__SIZE 0x00000003
|
|
#define CYREG_BLE_BLERD_CTR1 0x402e00a4
|
|
#define CYFLD_BLE_BLERD_VCO_WARMUP_TIME__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_VCO_WARMUP_TIME__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_PLL_SETTLING_TIME__OFFSET 0x00000001
|
|
#define CYFLD_BLE_BLERD_PLL_SETTLING_TIME__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_TX_FREEZE_TIME__OFFSET 0x00000003
|
|
#define CYFLD_BLE_BLERD_TX_FREEZE_TIME__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_TX_PREDRV_TIME__OFFSET 0x00000005
|
|
#define CYFLD_BLE_BLERD_TX_PREDRV_TIME__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_TX_MODSTART_TIME__OFFSET 0x00000006
|
|
#define CYFLD_BLE_BLERD_TX_MODSTART_TIME__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_TX_DF2_SEL__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLERD_TX_DF2_SEL__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_ADC_FULL_SWING_MONI_EN__OFFSET 0x00000009
|
|
#define CYFLD_BLE_BLERD_ADC_FULL_SWING_MONI_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_DBG_SELECT__OFFSET 0x0000000a
|
|
#define CYFLD_BLE_BLERD_DBG_SELECT__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_RX_DC_FREEZE_EN__OFFSET 0x0000000c
|
|
#define CYFLD_BLE_BLERD_RX_DC_FREEZE_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_RX_ENV_FREEZE_EN__OFFSET 0x0000000d
|
|
#define CYFLD_BLE_BLERD_RX_ENV_FREEZE_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_AGC_RST_DLY__OFFSET 0x0000000e
|
|
#define CYFLD_BLE_BLERD_AGC_RST_DLY__SIZE 0x00000002
|
|
#define CYREG_BLE_BLERD_AGC 0x402e00a8
|
|
#define CYFLD_BLE_BLERD_RST_EN__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_RST_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_CHECK_SAT_EN__OFFSET 0x00000001
|
|
#define CYFLD_BLE_BLERD_CHECK_SAT_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_SAT_CHK_TIM__OFFSET 0x00000002
|
|
#define CYFLD_BLE_BLERD_SAT_CHK_TIM__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_GAIN_MAPPING_MODE__OFFSET 0x00000003
|
|
#define CYFLD_BLE_BLERD_GAIN_MAPPING_MODE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_GAIN_SAT_THRES__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLERD_GAIN_SAT_THRES__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_PWR_MEAS_TIM__OFFSET 0x00000006
|
|
#define CYFLD_BLE_BLERD_PWR_MEAS_TIM__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_GAIN_STABLE_TIM__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLERD_GAIN_STABLE_TIM__SIZE 0x00000005
|
|
#define CYFLD_BLE_BLERD_START_WAIT_TIM__OFFSET 0x0000000d
|
|
#define CYFLD_BLE_BLERD_START_WAIT_TIM__SIZE 0x00000003
|
|
#define CYREG_BLE_BLERD_THRSHD1 0x402e00ac
|
|
#define CYFLD_BLE_BLERD_AGC60_66__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_AGC60_66__SIZE 0x00000006
|
|
#define CYFLD_BLE_BLERD_AGC66_60__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLERD_AGC66_60__SIZE 0x00000006
|
|
#define CYREG_BLE_BLERD_THRSHD2 0x402e00b0
|
|
#define CYFLD_BLE_BLERD_AGC48_60__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_AGC48_60__SIZE 0x00000006
|
|
#define CYFLD_BLE_BLERD_AGC60_48__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLERD_AGC60_48__SIZE 0x00000006
|
|
#define CYREG_BLE_BLERD_THRSHD3 0x402e00b4
|
|
#define CYFLD_BLE_BLERD_AGC36_48__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_AGC36_48__SIZE 0x00000006
|
|
#define CYFLD_BLE_BLERD_AGC48_36__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLERD_AGC48_36__SIZE 0x00000006
|
|
#define CYREG_BLE_BLERD_THRSHD4 0x402e00b8
|
|
#define CYFLD_BLE_BLERD_AGC18_36__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_AGC18_36__SIZE 0x00000006
|
|
#define CYFLD_BLE_BLERD_AGC36_18__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLERD_AGC36_18__SIZE 0x00000006
|
|
#define CYREG_BLE_BLERD_THRSHD5 0x402e00bc
|
|
#define CYFLD_BLE_BLERD_AGC0_18__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_AGC0_18__SIZE 0x00000006
|
|
#define CYFLD_BLE_BLERD_AGC18_0__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLERD_AGC18_0__SIZE 0x00000006
|
|
#define CYREG_BLE_BLERD_DC 0x402e00c0
|
|
#define CYFLD_BLE_BLERD_COMP_Q_CODE__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_COMP_Q_CODE__SIZE 0x00000008
|
|
#define CYFLD_BLE_BLERD_COMP_I_CODE__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLERD_COMP_I_CODE__SIZE 0x00000008
|
|
#define CYREG_BLE_BLERD_IQMIS 0x402e00c4
|
|
#define CYFLD_BLE_BLERD_IQCOMP_QVAL__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_IQCOMP_QVAL__SIZE 0x00000008
|
|
#define CYFLD_BLE_BLERD_IQCOMP_IVAL__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLERD_IQCOMP_IVAL__SIZE 0x00000008
|
|
#define CYREG_BLE_BLERD_DCCAL 0x402e00c8
|
|
#define CYFLD_BLE_BLERD_TEST_IBITS__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_TEST_IBITS__SIZE 0x00000006
|
|
#define CYFLD_BLE_BLERD_TEST_QBITS__OFFSET 0x00000006
|
|
#define CYFLD_BLE_BLERD_TEST_QBITS__SIZE 0x00000006
|
|
#define CYFLD_BLE_BLERD_TEST_MODE__OFFSET 0x0000000c
|
|
#define CYFLD_BLE_BLERD_TEST_MODE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_TEST_Q_POLARITY__OFFSET 0x0000000d
|
|
#define CYFLD_BLE_BLERD_TEST_Q_POLARITY__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_TEST_I_POLARITY__OFFSET 0x0000000e
|
|
#define CYFLD_BLE_BLERD_TEST_I_POLARITY__SIZE 0x00000001
|
|
#define CYREG_BLE_BLERD_RCCAL 0x402e00cc
|
|
#define CYFLD_BLE_BLERD_CODE_RX__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_CODE_RX__SIZE 0x00000005
|
|
#define CYFLD_BLE_BLERD_CODE_TX__OFFSET 0x00000005
|
|
#define CYFLD_BLE_BLERD_CODE_TX__SIZE 0x00000005
|
|
#define CYFLD_BLE_BLERD_SOFTRST_POWER_DIFF__OFFSET 0x0000000b
|
|
#define CYFLD_BLE_BLERD_SOFTRST_POWER_DIFF__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_SOFTRST_EN_TOSTR__OFFSET 0x0000000c
|
|
#define CYFLD_BLE_BLERD_SOFTRST_EN_TOSTR__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_SOFTRST_EN_TODIFF__OFFSET 0x0000000d
|
|
#define CYFLD_BLE_BLERD_SOFTRST_EN_TODIFF__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_AGC_GAIN_INC_TIMES_THRES__OFFSET 0x0000000e
|
|
#define CYFLD_BLE_BLERD_AGC_GAIN_INC_TIMES_THRES__SIZE 0x00000002
|
|
#define CYREG_BLE_BLERD_DSM1 0x402e00d0
|
|
#define CYFLD_BLE_BLERD_INDX_CODE3__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_INDX_CODE3__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLERD_INDX_CODE2__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLERD_INDX_CODE2__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLERD_INDX_CODE1__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLERD_INDX_CODE1__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLERD_INDX_CODE0__OFFSET 0x0000000c
|
|
#define CYFLD_BLE_BLERD_INDX_CODE0__SIZE 0x00000004
|
|
#define CYREG_BLE_BLERD_DSM2 0x402e00d4
|
|
#define CYFLD_BLE_BLERD_INDX_CODE7__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_INDX_CODE7__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLERD_INDX_CODE6__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLERD_INDX_CODE6__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLERD_INDX_CODE5__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLERD_INDX_CODE5__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLERD_INDX_CODE4__OFFSET 0x0000000c
|
|
#define CYFLD_BLE_BLERD_INDX_CODE4__SIZE 0x00000004
|
|
#define CYREG_BLE_BLERD_DSM3 0x402e00d8
|
|
#define CYFLD_BLE_BLERD_INDX_CODE11__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_INDX_CODE11__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLERD_INDX_CODE10__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLERD_INDX_CODE10__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLERD_INDX_CODE9__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLERD_INDX_CODE9__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLERD_INDX_CODE8__OFFSET 0x0000000c
|
|
#define CYFLD_BLE_BLERD_INDX_CODE8__SIZE 0x00000004
|
|
#define CYREG_BLE_BLERD_DSM4 0x402e00dc
|
|
#define CYFLD_BLE_BLERD_INDX_CODE15__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_INDX_CODE15__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLERD_INDX_CODE14__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLERD_INDX_CODE14__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLERD_INDX_CODE13__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLERD_INDX_CODE13__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLERD_INDX_CODE12__OFFSET 0x0000000c
|
|
#define CYFLD_BLE_BLERD_INDX_CODE12__SIZE 0x00000004
|
|
#define CYREG_BLE_BLERD_DSM5 0x402e00e0
|
|
#define CYFLD_BLE_BLERD_INDX_CODE19__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_INDX_CODE19__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLERD_INDX_CODE18__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLERD_INDX_CODE18__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLERD_INDX_CODE17__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLERD_INDX_CODE17__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLERD_INDX_CODE16__OFFSET 0x0000000c
|
|
#define CYFLD_BLE_BLERD_INDX_CODE16__SIZE 0x00000004
|
|
#define CYREG_BLE_BLERD_DSM6 0x402e00e4
|
|
#define CYFLD_BLE_BLERD_INDX_CODE23__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_INDX_CODE23__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLERD_INDX_CODE22__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLERD_INDX_CODE22__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLERD_INDX_CODE21__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLERD_INDX_CODE21__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLERD_INDX_CODE20__OFFSET 0x0000000c
|
|
#define CYFLD_BLE_BLERD_INDX_CODE20__SIZE 0x00000004
|
|
#define CYREG_BLE_BLERD_MONI 0x402e00e8
|
|
#define CYFLD_BLE_BLERD_PUP_SIG__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_PUP_SIG__SIZE 0x0000000b
|
|
#define CYFLD_BLE_BLERD_CBPF_CODE__OFFSET 0x0000000b
|
|
#define CYFLD_BLE_BLERD_CBPF_CODE__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLERD_LNA_CODE__OFFSET 0x0000000d
|
|
#define CYFLD_BLE_BLERD_LNA_CODE__SIZE 0x00000003
|
|
#define CYREG_BLE_BLERD_DBG_BB 0x402e00ec
|
|
#define CYFLD_BLE_BLERD_RX_OFFSET_Q_CODE__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_RX_OFFSET_Q_CODE__SIZE 0x00000008
|
|
#define CYFLD_BLE_BLERD_RX_OFFSET_I_CODE__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLERD_RX_OFFSET_I_CODE__SIZE 0x00000008
|
|
#define CYREG_BLE_BLERD_DBG_1 0x402e00f0
|
|
#define CYFLD_BLE_BLERD_FCAL_FINE_CODE__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_FCAL_FINE_CODE__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLERD_FCAL_COARSE_CODE__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLERD_FCAL_COARSE_CODE__SIZE 0x00000008
|
|
#define CYFLD_BLE_BLERD_FCAL_DONE__OFFSET 0x0000000c
|
|
#define CYFLD_BLE_BLERD_FCAL_DONE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_KVCAL_DONE__OFFSET 0x0000000d
|
|
#define CYFLD_BLE_BLERD_KVCAL_DONE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLERD_DCCAL_DONE__OFFSET 0x0000000e
|
|
#define CYFLD_BLE_BLERD_DCCAL_DONE__SIZE 0x00000001
|
|
#define CYREG_BLE_BLERD_DBG_2 0x402e00f4
|
|
#define CYFLD_BLE_BLERD_FCAL_CNT_LSB__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_FCAL_CNT_LSB__SIZE 0x00000010
|
|
#define CYREG_BLE_BLERD_DBG_3 0x402e00f8
|
|
#define CYFLD_BLE_BLERD_FCAL_CNT_MSB__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_FCAL_CNT_MSB__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLERD_RD_RCCAL_CODE__OFFSET 0x0000000a
|
|
#define CYFLD_BLE_BLERD_RD_RCCAL_CODE__SIZE 0x00000005
|
|
#define CYFLD_BLE_BLERD_RD_RCCAL_DONE__OFFSET 0x0000000f
|
|
#define CYFLD_BLE_BLERD_RD_RCCAL_DONE__SIZE 0x00000001
|
|
#define CYREG_BLE_BLERD_READ_IQ_1 0x402e0100
|
|
#define CYFLD_BLE_BLERD_ADC_1__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_ADC_1__SIZE 0x00000020
|
|
#define CYREG_BLE_BLERD_READ_IQ_2 0x402e0104
|
|
#define CYFLD_BLE_BLERD_ADC_2__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_ADC_2__SIZE 0x00000020
|
|
#define CYREG_BLE_BLERD_READ_IQ_3 0x402e0108
|
|
#define CYFLD_BLE_BLERD_ADC_3__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_ADC_3__SIZE 0x00000020
|
|
#define CYREG_BLE_BLERD_READ_IQ_4 0x402e010c
|
|
#define CYFLD_BLE_BLERD_ADC_4__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLERD_ADC_4__SIZE 0x00000020
|
|
#define CYDEV_BLE_BLELL_BASE 0x402e1000
|
|
#define CYDEV_BLE_BLELL_SIZE 0x00001000
|
|
#define CYREG_BLE_BLELL_COMMAND_REGISTER 0x402e1000
|
|
#define CYFLD_BLE_BLELL_COMMAND__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_COMMAND__SIZE 0x00000008
|
|
#define CYREG_BLE_BLELL_EVENT_INTR 0x402e1008
|
|
#define CYFLD_BLE_BLELL_ADV_INTR__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_ADV_INTR__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_SCAN_INTR__OFFSET 0x00000001
|
|
#define CYFLD_BLE_BLELL_SCAN_INTR__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_INIT_INTR__OFFSET 0x00000002
|
|
#define CYFLD_BLE_BLELL_INIT_INTR__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_CONN_INTR__OFFSET 0x00000003
|
|
#define CYFLD_BLE_BLELL_CONN_INTR__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_SM_INTR__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLELL_SM_INTR__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_DSM_INTR__OFFSET 0x00000005
|
|
#define CYFLD_BLE_BLELL_DSM_INTR__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_ENC_INTR__OFFSET 0x00000006
|
|
#define CYFLD_BLE_BLELL_ENC_INTR__SIZE 0x00000001
|
|
#define CYREG_BLE_BLELL_EVENT_ENABLE 0x402e1010
|
|
#define CYFLD_BLE_BLELL_ADV_INT_EN__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_ADV_INT_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_SCN_INT_EN__OFFSET 0x00000001
|
|
#define CYFLD_BLE_BLELL_SCN_INT_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_INIT_INT_EN__OFFSET 0x00000002
|
|
#define CYFLD_BLE_BLELL_INIT_INT_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_CONN_INT_EN__OFFSET 0x00000003
|
|
#define CYFLD_BLE_BLELL_CONN_INT_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_SM_INT_EN__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLELL_SM_INT_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_DSM_INT_EN__OFFSET 0x00000005
|
|
#define CYFLD_BLE_BLELL_DSM_INT_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_ENC_INT_EN__OFFSET 0x00000006
|
|
#define CYFLD_BLE_BLELL_ENC_INT_EN__SIZE 0x00000001
|
|
#define CYREG_BLE_BLELL_ADV_PARAMS 0x402e1018
|
|
#define CYFLD_BLE_BLELL_TX_ADDR__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_TX_ADDR__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_ADV_TYPE__OFFSET 0x00000001
|
|
#define CYFLD_BLE_BLELL_ADV_TYPE__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLELL_ADV_FILT_POLICY__OFFSET 0x00000003
|
|
#define CYFLD_BLE_BLELL_ADV_FILT_POLICY__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLELL_ADV_CHANNEL_MAP__OFFSET 0x00000005
|
|
#define CYFLD_BLE_BLELL_ADV_CHANNEL_MAP__SIZE 0x00000003
|
|
#define CYFLD_BLE_BLELL_RX_ADDR__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLELL_RX_ADDR__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_ADV_LOW_DUTY_CYCLE__OFFSET 0x0000000a
|
|
#define CYFLD_BLE_BLELL_ADV_LOW_DUTY_CYCLE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_RCV_TX_ADDR__OFFSET 0x0000000f
|
|
#define CYFLD_BLE_BLELL_RCV_TX_ADDR__SIZE 0x00000001
|
|
#define CYREG_BLE_BLELL_ADV_INTERVAL_TIMEOUT 0x402e101c
|
|
#define CYFLD_BLE_BLELL_ADV_INTERVAL__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_ADV_INTERVAL__SIZE 0x0000000f
|
|
#define CYREG_BLE_BLELL_ADV_INTR 0x402e1020
|
|
#define CYFLD_BLE_BLELL_ADV_STRT_INTR__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_ADV_STRT_INTR__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_ADV_CLOSE_INTR__OFFSET 0x00000001
|
|
#define CYFLD_BLE_BLELL_ADV_CLOSE_INTR__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_ADV_TX_INTR__OFFSET 0x00000002
|
|
#define CYFLD_BLE_BLELL_ADV_TX_INTR__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_SCAN_RSP_TX_INTR__OFFSET 0x00000003
|
|
#define CYFLD_BLE_BLELL_SCAN_RSP_TX_INTR__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_SCAN_REQ_RX_INTR__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLELL_SCAN_REQ_RX_INTR__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_CONN_REQ_RX_INTR__OFFSET 0x00000005
|
|
#define CYFLD_BLE_BLELL_CONN_REQ_RX_INTR__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_SLV_CONNECTED__OFFSET 0x00000006
|
|
#define CYFLD_BLE_BLELL_SLV_CONNECTED__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_ADV_TIMEOUT__OFFSET 0x00000007
|
|
#define CYFLD_BLE_BLELL_ADV_TIMEOUT__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_ADV_ON__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLELL_ADV_ON__SIZE 0x00000001
|
|
#define CYREG_BLE_BLELL_ADV_NEXT_INSTANT 0x402e1024
|
|
#define CYFLD_BLE_BLELL_ADV_NEXT_INSTANT__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_ADV_NEXT_INSTANT__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_SCAN_INTERVAL 0x402e1028
|
|
#define CYFLD_BLE_BLELL_SCAN_INTERVAL__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_SCAN_INTERVAL__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_SCAN_WINDOW 0x402e102c
|
|
#define CYFLD_BLE_BLELL_SCAN_WINDOW__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_SCAN_WINDOW__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_SCAN_PARAM 0x402e1030
|
|
#define CYFLD_BLE_BLELL_SCAN_TYPE__OFFSET 0x00000001
|
|
#define CYFLD_BLE_BLELL_SCAN_TYPE__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLELL_SCAN_FILT_POLICY__OFFSET 0x00000003
|
|
#define CYFLD_BLE_BLELL_SCAN_FILT_POLICY__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLELL_DUP_FILT_EN__OFFSET 0x00000005
|
|
#define CYFLD_BLE_BLELL_DUP_FILT_EN__SIZE 0x00000001
|
|
#define CYREG_BLE_BLELL_SCAN_INTR 0x402e1038
|
|
#define CYFLD_BLE_BLELL_SCAN_STRT_INTR__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_SCAN_STRT_INTR__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_SCAN_CLOSE_INTR__OFFSET 0x00000001
|
|
#define CYFLD_BLE_BLELL_SCAN_CLOSE_INTR__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_SCAN_TX_INTR__OFFSET 0x00000002
|
|
#define CYFLD_BLE_BLELL_SCAN_TX_INTR__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_ADV_RX_INTR__OFFSET 0x00000003
|
|
#define CYFLD_BLE_BLELL_ADV_RX_INTR__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_SCAN_RSP_RX_INTR__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLELL_SCAN_RSP_RX_INTR__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_SCAN_ON__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLELL_SCAN_ON__SIZE 0x00000001
|
|
#define CYREG_BLE_BLELL_SCAN_NEXT_INSTANT 0x402e103c
|
|
#define CYFLD_BLE_BLELL_NEXT_SCAN_INSTANT__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_NEXT_SCAN_INSTANT__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_INIT_INTERVAL 0x402e1040
|
|
#define CYFLD_BLE_BLELL_INIT_SCAN_INTERVAL__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_INIT_SCAN_INTERVAL__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_INIT_WINDOW 0x402e1044
|
|
#define CYFLD_BLE_BLELL_INIT_SCAN_WINDOW__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_INIT_SCAN_WINDOW__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_INIT_PARAM 0x402e1048
|
|
#define CYFLD_BLE_BLELL_RX_ADDR__RX_TX_ADDR__OFFSET 0x00000001
|
|
#define CYFLD_BLE_BLELL_RX_ADDR__RX_TX_ADDR__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_INIT_FILT_POLICY__OFFSET 0x00000003
|
|
#define CYFLD_BLE_BLELL_INIT_FILT_POLICY__SIZE 0x00000001
|
|
#define CYREG_BLE_BLELL_INIT_INTR 0x402e1050
|
|
#define CYFLD_BLE_BLELL_INIT_INTERVAL_EXPIRE_INTR__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_INIT_INTERVAL_EXPIRE_INTR__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_INIT_CLOSE_WINDOW_INR__OFFSET 0x00000001
|
|
#define CYFLD_BLE_BLELL_INIT_CLOSE_WINDOW_INR__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_INIT_TX_START_INTR__OFFSET 0x00000002
|
|
#define CYFLD_BLE_BLELL_INIT_TX_START_INTR__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_MASTER_CONN_CREATED__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLELL_MASTER_CONN_CREATED__SIZE 0x00000001
|
|
#define CYREG_BLE_BLELL_INIT_NEXT_INSTANT 0x402e1054
|
|
#define CYFLD_BLE_BLELL_INIT_NEXT_INSTANT__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_INIT_NEXT_INSTANT__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_DEVICE_RAND_ADDR_L 0x402e1058
|
|
#define CYFLD_BLE_BLELL_DEVICE_RAND_ADDR_L__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_DEVICE_RAND_ADDR_L__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_DEVICE_RAND_ADDR_M 0x402e105c
|
|
#define CYFLD_BLE_BLELL_DEVICE_RAND_ADDR_M__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_DEVICE_RAND_ADDR_M__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_DEVICE_RAND_ADDR_H 0x402e1060
|
|
#define CYFLD_BLE_BLELL_DEVICE_RAND_ADDR_H__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_DEVICE_RAND_ADDR_H__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_PEER_ADDR_L 0x402e1068
|
|
#define CYFLD_BLE_BLELL_PEER_ADDR_L__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_PEER_ADDR_L__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_PEER_ADDR_M 0x402e106c
|
|
#define CYFLD_BLE_BLELL_PEER_ADDR_M__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_PEER_ADDR_M__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_PEER_ADDR_H 0x402e1070
|
|
#define CYFLD_BLE_BLELL_PEER_ADDR_H__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_PEER_ADDR_H__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_WL_ADDR_TYPE 0x402e1078
|
|
#define CYFLD_BLE_BLELL_WL_ADDR_TYPE__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_WL_ADDR_TYPE__SIZE 0x00000008
|
|
#define CYREG_BLE_BLELL_WL_ENABLE 0x402e107c
|
|
#define CYFLD_BLE_BLELL_WL_ENABLE__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_WL_ENABLE__SIZE 0x00000008
|
|
#define CYREG_BLE_BLELL_TRANSMIT_WINDOW_OFFSET 0x402e1080
|
|
#define CYFLD_BLE_BLELL_TX_WINDOW_OFFSET__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_TX_WINDOW_OFFSET__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_TRANSMIT_WINDOW_SIZE 0x402e1084
|
|
#define CYFLD_BLE_BLELL_TX_WINDOW_SIZE__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_TX_WINDOW_SIZE__SIZE 0x00000008
|
|
#define CYREG_BLE_BLELL_DATA_CHANNELS_L0 0x402e1088
|
|
#define CYFLD_BLE_BLELL_DATA_CHANNELS_L0__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_DATA_CHANNELS_L0__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_DATA_CHANNELS_M0 0x402e108c
|
|
#define CYFLD_BLE_BLELL_DATA_CHANNELS_M0__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_DATA_CHANNELS_M0__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_DATA_CHANNELS_H0 0x402e1090
|
|
#define CYFLD_BLE_BLELL_DATA_CHANNELS_H0__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_DATA_CHANNELS_H0__SIZE 0x00000005
|
|
#define CYREG_BLE_BLELL_DATA_CHANNELS_L1 0x402e1098
|
|
#define CYFLD_BLE_BLELL_DATA_CHANNELS_L1__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_DATA_CHANNELS_L1__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_DATA_CHANNELS_M1 0x402e109c
|
|
#define CYFLD_BLE_BLELL_DATA_CHANNELS_M1__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_DATA_CHANNELS_M1__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_DATA_CHANNELS_H1 0x402e10a0
|
|
#define CYFLD_BLE_BLELL_DATA_CHANNELS_H1__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_DATA_CHANNELS_H1__SIZE 0x00000005
|
|
#define CYREG_BLE_BLELL_CONN_INTR 0x402e10a8
|
|
#define CYFLD_BLE_BLELL_CONN_CLOSED__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_CONN_CLOSED__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_CONN_ESTB__OFFSET 0x00000001
|
|
#define CYFLD_BLE_BLELL_CONN_ESTB__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_MAP_UPDT_DONE__OFFSET 0x00000002
|
|
#define CYFLD_BLE_BLELL_MAP_UPDT_DONE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_START_CE__OFFSET 0x00000003
|
|
#define CYFLD_BLE_BLELL_START_CE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_CLOSE_CE__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLELL_CLOSE_CE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_CE_TX_ACK__OFFSET 0x00000005
|
|
#define CYFLD_BLE_BLELL_CE_TX_ACK__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_CE_RX__OFFSET 0x00000006
|
|
#define CYFLD_BLE_BLELL_CE_RX__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_CON_UPDT_DONE__OFFSET 0x00000007
|
|
#define CYFLD_BLE_BLELL_CON_UPDT_DONE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_DISCON_STATUS__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLELL_DISCON_STATUS__SIZE 0x00000003
|
|
#define CYFLD_BLE_BLELL_RX_PDU_STATUS__OFFSET 0x0000000b
|
|
#define CYFLD_BLE_BLELL_RX_PDU_STATUS__SIZE 0x00000003
|
|
#define CYFLD_BLE_BLELL_PING_TIMER_EXPIRD_INTR__OFFSET 0x0000000e
|
|
#define CYFLD_BLE_BLELL_PING_TIMER_EXPIRD_INTR__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_PING_NEARLY_EXPIRD_INTR__OFFSET 0x0000000f
|
|
#define CYFLD_BLE_BLELL_PING_NEARLY_EXPIRD_INTR__SIZE 0x00000001
|
|
#define CYREG_BLE_BLELL_CONN_STATUS 0x402e10ac
|
|
#define CYFLD_BLE_BLELL_RECEIVE_PACKET_COUNT__OFFSET 0x0000000c
|
|
#define CYFLD_BLE_BLELL_RECEIVE_PACKET_COUNT__SIZE 0x00000004
|
|
#define CYREG_BLE_BLELL_CONN_INDEX 0x402e10b0
|
|
#define CYFLD_BLE_BLELL_CONN_INDEX__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_CONN_INDEX__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_WAKEUP_CONFIG 0x402e10b8
|
|
#define CYFLD_BLE_BLELL_OSC_STARTUP_DELAY__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_OSC_STARTUP_DELAY__SIZE 0x00000008
|
|
#define CYFLD_BLE_BLELL_DSM_OFFSET_TO_WAKEUP_INSTANT__OFFSET 0x0000000a
|
|
#define CYFLD_BLE_BLELL_DSM_OFFSET_TO_WAKEUP_INSTANT__SIZE 0x00000006
|
|
#define CYREG_BLE_BLELL_WAKEUP_CONTROL 0x402e10c0
|
|
#define CYFLD_BLE_BLELL_WAKEUP_INSTANT__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_WAKEUP_INSTANT__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_CLOCK_CONFIG 0x402e10c4
|
|
#define CYFLD_BLE_BLELL_ADV_CLK_GATE_EN__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_ADV_CLK_GATE_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_SCAN_CLK_GATE_EN__OFFSET 0x00000001
|
|
#define CYFLD_BLE_BLELL_SCAN_CLK_GATE_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_INIT_CLK_GATE_EN__OFFSET 0x00000002
|
|
#define CYFLD_BLE_BLELL_INIT_CLK_GATE_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_CONN_CLK_GATE_EN__OFFSET 0x00000003
|
|
#define CYFLD_BLE_BLELL_CONN_CLK_GATE_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_CORECLK_GATE_EN__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLELL_CORECLK_GATE_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_SYSCLK_GATE_EN__OFFSET 0x00000005
|
|
#define CYFLD_BLE_BLELL_SYSCLK_GATE_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_PHY_CLK_GATE_EN__OFFSET 0x00000006
|
|
#define CYFLD_BLE_BLELL_PHY_CLK_GATE_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_LLH_IDLE__OFFSET 0x00000007
|
|
#define CYFLD_BLE_BLELL_LLH_IDLE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_LPO_CLK_FREQ_SEL__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLELL_LPO_CLK_FREQ_SEL__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_LPO_SEL_EXTERNAL__OFFSET 0x00000009
|
|
#define CYFLD_BLE_BLELL_LPO_SEL_EXTERNAL__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_SM_AUTO_WKUP_EN__OFFSET 0x0000000a
|
|
#define CYFLD_BLE_BLELL_SM_AUTO_WKUP_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_SM_INTR_EN__OFFSET 0x0000000c
|
|
#define CYFLD_BLE_BLELL_SM_INTR_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_SLEEP_MODE_EN__OFFSET 0x0000000e
|
|
#define CYFLD_BLE_BLELL_SLEEP_MODE_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_DEEP_SLEEP_MODE_EN__OFFSET 0x0000000f
|
|
#define CYFLD_BLE_BLELL_DEEP_SLEEP_MODE_EN__SIZE 0x00000001
|
|
#define CYREG_BLE_BLELL_TIM_COUNTER_L 0x402e10c8
|
|
#define CYFLD_BLE_BLELL_TIM_REF_CLOCK__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_TIM_REF_CLOCK__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_POC_REG__TIM_CONTROL 0x402e10d8
|
|
#define CYFLD_BLE_BLELL_BB_CLK_FREQ_MINUS_1__OFFSET 0x00000003
|
|
#define CYFLD_BLE_BLELL_BB_CLK_FREQ_MINUS_1__SIZE 0x00000005
|
|
#define CYREG_BLE_BLELL_ADV_TX_DATA_FIFO 0x402e10e0
|
|
#define CYFLD_BLE_BLELL_ADV_TX_DATA__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_ADV_TX_DATA__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_ADV_SCN_RSP_TX_FIFO 0x402e10e8
|
|
#define CYFLD_BLE_BLELL_SCAN_RSP_DATA__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_SCAN_RSP_DATA__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_INIT_SCN_ADV_RX_FIFO 0x402e10f8
|
|
#define CYFLD_BLE_BLELL_ADV_SCAN_RSP_RX_DATA__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_ADV_SCAN_RSP_RX_DATA__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_CONN_INTERVAL 0x402e1100
|
|
#define CYFLD_BLE_BLELL_CONNECTION_INTERVAL__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_CONNECTION_INTERVAL__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_SUP_TIMEOUT 0x402e1104
|
|
#define CYFLD_BLE_BLELL_SUPERVISION_TIMEOUT__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_SUPERVISION_TIMEOUT__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_SLAVE_LATENCY 0x402e1108
|
|
#define CYFLD_BLE_BLELL_SLAVE_LATENCY__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_SLAVE_LATENCY__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_CE_LENGTH 0x402e110c
|
|
#define CYFLD_BLE_BLELL_CONNECTION_EVENT_LENGTH__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_CONNECTION_EVENT_LENGTH__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_PDU_ACCESS_ADDR_L_REGISTER 0x402e1110
|
|
#define CYFLD_BLE_BLELL_PDU_ACCESS_ADDRESS_LOWER_BITS__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_PDU_ACCESS_ADDRESS_LOWER_BITS__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_PDU_ACCESS_ADDR_H_REGISTER 0x402e1114
|
|
#define CYFLD_BLE_BLELL_PDU_ACCESS_ADDRESS_HIGHER_BITS__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_PDU_ACCESS_ADDRESS_HIGHER_BITS__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_CONN_CE_INSTANT 0x402e1118
|
|
#define CYFLD_BLE_BLELL_CE_INSTANT__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_CE_INSTANT__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_CE_CNFG_STS_REGISTER 0x402e111c
|
|
#define CYFLD_BLE_BLELL_DATA_LIST_INDEX_LAST_ACK_INDEX__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_DATA_LIST_INDEX_LAST_ACK_INDEX__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLELL_DATA_LIST_HEAD_UP__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLELL_DATA_LIST_HEAD_UP__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_MAS_SLV__OFFSET 0x00000005
|
|
#define CYFLD_BLE_BLELL_MAS_SLV__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_MD__OFFSET 0x00000006
|
|
#define CYFLD_BLE_BLELL_MD__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_MAP_INDEX__CURR_INDEX__OFFSET 0x00000007
|
|
#define CYFLD_BLE_BLELL_MAP_INDEX__CURR_INDEX__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_PAUSE_DATA__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLELL_PAUSE_DATA__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_CONN_ACTIVE__OFFSET 0x0000000a
|
|
#define CYFLD_BLE_BLELL_CONN_ACTIVE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_CURRENT_PDU_INDEX__OFFSET 0x0000000c
|
|
#define CYFLD_BLE_BLELL_CURRENT_PDU_INDEX__SIZE 0x00000004
|
|
#define CYREG_BLE_BLELL_NEXT_CE_INSTANT 0x402e1120
|
|
#define CYFLD_BLE_BLELL_NEXT_CE_INSTANT__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_NEXT_CE_INSTANT__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_CONN_CE_COUNTER 0x402e1124
|
|
#define CYFLD_BLE_BLELL_CONNECTION_EVENT_COUNTER__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_CONNECTION_EVENT_COUNTER__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_DATA_LIST_SENT_UPDATE__STATUS 0x402e1128
|
|
#define CYFLD_BLE_BLELL_LIST_INDEX__TX_SENT_3_0__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_LIST_INDEX__TX_SENT_3_0__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLELL_TX_SENT_4__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLELL_TX_SENT_4__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_SET_CLEAR__OFFSET 0x00000007
|
|
#define CYFLD_BLE_BLELL_SET_CLEAR__SIZE 0x00000001
|
|
#define CYREG_BLE_BLELL_DATA_LIST_ACK_UPDATE__STATUS 0x402e112c
|
|
#define CYFLD_BLE_BLELL_LIST_INDEX__TX_ACK_3_0__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_LIST_INDEX__TX_ACK_3_0__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLELL_TX_ACK_4__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLELL_TX_ACK_4__SIZE 0x00000001
|
|
#define CYREG_BLE_BLELL_DATA_MEM_DESCRIPTOR0 0x402e1140
|
|
#define CYFLD_BLE_BLELL_LLID__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_LLID__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLELL_DATA_LENGTH__OFFSET 0x00000002
|
|
#define CYFLD_BLE_BLELL_DATA_LENGTH__SIZE 0x00000005
|
|
#define CYREG_BLE_BLELL_DATA_MEM_DESCRIPTOR1 0x402e1144
|
|
#define CYREG_BLE_BLELL_DATA_MEM_DESCRIPTOR2 0x402e1148
|
|
#define CYREG_BLE_BLELL_DATA_MEM_DESCRIPTOR3 0x402e114c
|
|
#define CYREG_BLE_BLELL_DATA_MEM_DESCRIPTOR4 0x402e1150
|
|
#define CYREG_BLE_BLELL_WINDOW_WIDEN_INTVL 0x402e1160
|
|
#define CYFLD_BLE_BLELL_WINDOW_WIDEN_INTVL__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_WINDOW_WIDEN_INTVL__SIZE 0x0000000c
|
|
#define CYREG_BLE_BLELL_WINDOW_WIDEN_WINOFF 0x402e1164
|
|
#define CYFLD_BLE_BLELL_WINDOW_WIDEN_WINOFF__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_WINDOW_WIDEN_WINOFF__SIZE 0x0000000c
|
|
#define CYREG_BLE_BLELL_LE_RF_TEST_MODE 0x402e1170
|
|
#define CYFLD_BLE_BLELL_TEST_FREQUENCY__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_TEST_FREQUENCY__SIZE 0x00000006
|
|
#define CYFLD_BLE_BLELL_TEST_TYPE__OFFSET 0x00000006
|
|
#define CYFLD_BLE_BLELL_TEST_TYPE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_PKT_PAYLOAD__OFFSET 0x00000007
|
|
#define CYFLD_BLE_BLELL_PKT_PAYLOAD__SIZE 0x00000003
|
|
#define CYFLD_BLE_BLELL_TEST_LENGTH__OFFSET 0x0000000a
|
|
#define CYFLD_BLE_BLELL_TEST_LENGTH__SIZE 0x00000006
|
|
#define CYREG_BLE_BLELL_DTM_RX_PKT_COUNT 0x402e1174
|
|
#define CYFLD_BLE_BLELL_RX_PACKET_COUNT__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_RX_PACKET_COUNT__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_TXRX_HOP 0x402e1188
|
|
#define CYFLD_BLE_BLELL_HOP_CH_TX__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_HOP_CH_TX__SIZE 0x00000007
|
|
#define CYFLD_BLE_BLELL_HOP_CH_RX__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLELL_HOP_CH_RX__SIZE 0x00000007
|
|
#define CYREG_BLE_BLELL_TX_RX_ON_DELAY 0x402e1190
|
|
#define CYFLD_BLE_BLELL_RXON_DELAY__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_RXON_DELAY__SIZE 0x00000008
|
|
#define CYFLD_BLE_BLELL_TXON_DELAY__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLELL_TXON_DELAY__SIZE 0x00000008
|
|
#define CYREG_BLE_BLELL_DEV_PUB_ADDR_L 0x402e11c0
|
|
#define CYFLD_BLE_BLELL_DEV_PUB_ADDR_L__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_DEV_PUB_ADDR_L__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_DEV_PUB_ADDR_M 0x402e11c4
|
|
#define CYFLD_BLE_BLELL_DEV_PUB_ADDR_M__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_DEV_PUB_ADDR_M__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_DEV_PUB_ADDR_H 0x402e11c8
|
|
#define CYFLD_BLE_BLELL_DEV_PUB_ADDR_H__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_DEV_PUB_ADDR_H__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_ADV_CH_TX_POWER 0x402e11cc
|
|
#define CYFLD_BLE_BLELL_ADV_TRANSMIT_POWER__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_ADV_TRANSMIT_POWER__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_OFFSET_TO_FIRST_INSTANT 0x402e11d0
|
|
#define CYFLD_BLE_BLELL_OFFSET_TO_FIRST_EVENT__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_OFFSET_TO_FIRST_EVENT__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_ADV_CONFIG 0x402e11d4
|
|
#define CYFLD_BLE_BLELL_ADV_STRT_EN__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_ADV_STRT_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_ADV_CLS_EN__OFFSET 0x00000001
|
|
#define CYFLD_BLE_BLELL_ADV_CLS_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_ADV_TX_EN__OFFSET 0x00000002
|
|
#define CYFLD_BLE_BLELL_ADV_TX_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_SCN_RSP_TX_EN__OFFSET 0x00000003
|
|
#define CYFLD_BLE_BLELL_SCN_RSP_TX_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_ADV_SCN_REQ_RX_EN__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLELL_ADV_SCN_REQ_RX_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_ADV_CONN_REQ_RX_EN__OFFSET 0x00000005
|
|
#define CYFLD_BLE_BLELL_ADV_CONN_REQ_RX_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_SLV_CONNECTED_EN__OFFSET 0x00000006
|
|
#define CYFLD_BLE_BLELL_SLV_CONNECTED_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_ADV_TIMEOUT_EN__OFFSET 0x00000007
|
|
#define CYFLD_BLE_BLELL_ADV_TIMEOUT_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_ADV_RAND_DISABLE__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLELL_ADV_RAND_DISABLE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_ADV_PKT_INTERVAL__OFFSET 0x0000000b
|
|
#define CYFLD_BLE_BLELL_ADV_PKT_INTERVAL__SIZE 0x00000005
|
|
#define CYREG_BLE_BLELL_SCAN_CONFIG 0x402e11d8
|
|
#define CYFLD_BLE_BLELL_SCN_STRT_EN__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_SCN_STRT_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_SCN_CLOSE_EN__OFFSET 0x00000001
|
|
#define CYFLD_BLE_BLELL_SCN_CLOSE_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_SCN_TX_EN__OFFSET 0x00000002
|
|
#define CYFLD_BLE_BLELL_SCN_TX_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_ADV_RX_EN__OFFSET 0x00000003
|
|
#define CYFLD_BLE_BLELL_ADV_RX_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_SCN_RSP_RX_EN__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLELL_SCN_RSP_RX_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_BACKOFF_ENABLE__OFFSET 0x0000000b
|
|
#define CYFLD_BLE_BLELL_BACKOFF_ENABLE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_SCAN_CHANNEL_MAP__OFFSET 0x0000000d
|
|
#define CYFLD_BLE_BLELL_SCAN_CHANNEL_MAP__SIZE 0x00000003
|
|
#define CYREG_BLE_BLELL_INIT_CONFIG 0x402e11dc
|
|
#define CYFLD_BLE_BLELL_INIT_STRT_EN__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_INIT_STRT_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_INIT_CLOSE_EN__OFFSET 0x00000001
|
|
#define CYFLD_BLE_BLELL_INIT_CLOSE_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_CONN_REQ_TX_EN__OFFSET 0x00000002
|
|
#define CYFLD_BLE_BLELL_CONN_REQ_TX_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_CONN_CREATED__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLELL_CONN_CREATED__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_INIT_CHANNEL_MAP__OFFSET 0x0000000d
|
|
#define CYFLD_BLE_BLELL_INIT_CHANNEL_MAP__SIZE 0x00000003
|
|
#define CYREG_BLE_BLELL_CONN_CONFIG 0x402e11e0
|
|
#define CYFLD_BLE_BLELL_RX_PKT_LIMIT__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_RX_PKT_LIMIT__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLELL_RX_INTR_THRESHOLD__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLELL_RX_INTR_THRESHOLD__SIZE 0x00000004
|
|
#define CYFLD_BLE_BLELL_MD_BIT_CLEAR__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLELL_MD_BIT_CLEAR__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_DSM_SLOT_VARIANCE__OFFSET 0x0000000b
|
|
#define CYFLD_BLE_BLELL_DSM_SLOT_VARIANCE__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_SLV_MD_CONFIG__OFFSET 0x0000000c
|
|
#define CYFLD_BLE_BLELL_SLV_MD_CONFIG__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_EXTEND_CU_TX_WIN__OFFSET 0x0000000d
|
|
#define CYFLD_BLE_BLELL_EXTEND_CU_TX_WIN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_MASK_SUTO_AT_UPDT__OFFSET 0x0000000e
|
|
#define CYFLD_BLE_BLELL_MASK_SUTO_AT_UPDT__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_CONN_REQ_1SLOT_EARLY__OFFSET 0x0000000f
|
|
#define CYFLD_BLE_BLELL_CONN_REQ_1SLOT_EARLY__SIZE 0x00000001
|
|
#define CYREG_BLE_BLELL_CONN_CH_TX_POWER 0x402e11e4
|
|
#define CYFLD_BLE_BLELL_CONNCH_TRANSMIT_POWER__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_CONNCH_TRANSMIT_POWER__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_CONN_PARAM1 0x402e11e8
|
|
#define CYFLD_BLE_BLELL_SCA_PARAM__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_SCA_PARAM__SIZE 0x00000003
|
|
#define CYFLD_BLE_BLELL_HOP_INCREMENT_PARAM__OFFSET 0x00000003
|
|
#define CYFLD_BLE_BLELL_HOP_INCREMENT_PARAM__SIZE 0x00000005
|
|
#define CYFLD_BLE_BLELL_CRC_INIT_L__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLELL_CRC_INIT_L__SIZE 0x00000008
|
|
#define CYREG_BLE_BLELL_CONN_PARAM2 0x402e11ec
|
|
#define CYFLD_BLE_BLELL_CRC_INIT_H__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_CRC_INIT_H__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_CONN_INTR_MASK 0x402e11f0
|
|
#define CYFLD_BLE_BLELL_CONN_CL_INT_EN__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_CONN_CL_INT_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_CONN_ESTB_INT_EN__OFFSET 0x00000001
|
|
#define CYFLD_BLE_BLELL_CONN_ESTB_INT_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_MAP_UPDT_INT_EN__OFFSET 0x00000002
|
|
#define CYFLD_BLE_BLELL_MAP_UPDT_INT_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_START_CE_INT_EN__OFFSET 0x00000003
|
|
#define CYFLD_BLE_BLELL_START_CE_INT_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_CLOSE_CE_INT_EN__OFFSET 0x00000004
|
|
#define CYFLD_BLE_BLELL_CLOSE_CE_INT_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_CE_TX_ACK_INT_EN__OFFSET 0x00000005
|
|
#define CYFLD_BLE_BLELL_CE_TX_ACK_INT_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_CE_RX_INT_EN__OFFSET 0x00000006
|
|
#define CYFLD_BLE_BLELL_CE_RX_INT_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_CONN_UPDATE_INTR_EN__OFFSET 0x00000007
|
|
#define CYFLD_BLE_BLELL_CONN_UPDATE_INTR_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_RX_GOOD_PDU_INT_EN__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLELL_RX_GOOD_PDU_INT_EN__SIZE 0x00000001
|
|
#define CYFLD_BLE_BLELL_RX_BAD_PDU_INT_EN__OFFSET 0x00000009
|
|
#define CYFLD_BLE_BLELL_RX_BAD_PDU_INT_EN__SIZE 0x00000001
|
|
#define CYREG_BLE_BLELL_SLAVE_TIMING_CONTROL 0x402e11f4
|
|
#define CYFLD_BLE_BLELL_SLAVE_TIME_SET_VAL__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_SLAVE_TIME_SET_VAL__SIZE 0x00000008
|
|
#define CYFLD_BLE_BLELL_SLAVE_TIME_ADJ_VAL__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLELL_SLAVE_TIME_ADJ_VAL__SIZE 0x00000008
|
|
#define CYREG_BLE_BLELL_RECEIVE_TRIG_CTRL 0x402e11f8
|
|
#define CYFLD_BLE_BLELL_ACC_TRIGGER_THRESHOLD__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_ACC_TRIGGER_THRESHOLD__SIZE 0x00000006
|
|
#define CYFLD_BLE_BLELL_ACC_TRIGGER_TIMEOUT__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLELL_ACC_TRIGGER_TIMEOUT__SIZE 0x00000008
|
|
#define CYREG_BLE_BLELL_DPLL_CONFIG 0x402e1258
|
|
#define CYFLD_BLE_BLELL_DPLL_CORREL_CONFIG__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_DPLL_CORREL_CONFIG__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_WHITELIST_BASE_ADDR 0x402e1340
|
|
#define CYFLD_BLE_BLELL_WL_BASE_ADDR__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_WL_BASE_ADDR__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_CONN_UPDATE_NEW_INTERVAL 0x402e13a4
|
|
#define CYFLD_BLE_BLELL_CONN_UPDT_INTERVAL__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_CONN_UPDT_INTERVAL__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_CONN_UPDATE_NEW_LATENCY 0x402e13a8
|
|
#define CYFLD_BLE_BLELL_CONN_UPDT_SLV_LATENCY__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_CONN_UPDT_SLV_LATENCY__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_CONN_UPDATE_NEW_SUP_TO 0x402e13ac
|
|
#define CYFLD_BLE_BLELL_CONN_UPDT_SUP_TO__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_CONN_UPDT_SUP_TO__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_CONN_UPDATE_NEW_SL_INTERVAL 0x402e13b0
|
|
#define CYFLD_BLE_BLELL_SL_CONN_INTERVAL_VAL__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_SL_CONN_INTERVAL_VAL__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_CONN_REQ_WORD0 0x402e13c0
|
|
#define CYFLD_BLE_BLELL_ACCESS_ADDR_LOWER__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_ACCESS_ADDR_LOWER__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_CONN_REQ_WORD1 0x402e13c4
|
|
#define CYFLD_BLE_BLELL_ACCESS_ADDR_UPPER__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_ACCESS_ADDR_UPPER__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_CONN_REQ_WORD2 0x402e13c8
|
|
#define CYFLD_BLE_BLELL_TX_WINDOW_SIZE_VAL__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_TX_WINDOW_SIZE_VAL__SIZE 0x00000008
|
|
#define CYFLD_BLE_BLELL_CRC_INIT_LOWER__OFFSET 0x00000008
|
|
#define CYFLD_BLE_BLELL_CRC_INIT_LOWER__SIZE 0x00000008
|
|
#define CYREG_BLE_BLELL_CONN_REQ_WORD3 0x402e13cc
|
|
#define CYFLD_BLE_BLELL_CRC_INIT_UPPER__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_CRC_INIT_UPPER__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_CONN_REQ_WORD4 0x402e13d0
|
|
#define CYREG_BLE_BLELL_CONN_REQ_WORD5 0x402e13d4
|
|
#define CYFLD_BLE_BLELL_CONNECTION_INTERVAL_VAL__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_CONNECTION_INTERVAL_VAL__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_CONN_REQ_WORD6 0x402e13d8
|
|
#define CYFLD_BLE_BLELL_SLAVE_LATENCY_VAL__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_SLAVE_LATENCY_VAL__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_CONN_REQ_WORD7 0x402e13dc
|
|
#define CYFLD_BLE_BLELL_SUPERVISION_TIMEOUT_VAL__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_SUPERVISION_TIMEOUT_VAL__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_CONN_REQ_WORD8 0x402e13e0
|
|
#define CYFLD_BLE_BLELL_DATA_CHANNELS_LOWER__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_DATA_CHANNELS_LOWER__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_CONN_REQ_WORD9 0x402e13e4
|
|
#define CYFLD_BLE_BLELL_DATA_CHANNELS_MID__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_DATA_CHANNELS_MID__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_CONN_REQ_WORD10 0x402e13e8
|
|
#define CYFLD_BLE_BLELL_DATA_CHANNELS_UPPER__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_DATA_CHANNELS_UPPER__SIZE 0x00000005
|
|
#define CYREG_BLE_BLELL_CONN_REQ_WORD11 0x402e13ec
|
|
#define CYFLD_BLE_BLELL_HOP_INCREMENT_2__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_HOP_INCREMENT_2__SIZE 0x00000005
|
|
#define CYFLD_BLE_BLELL_SCA_2__OFFSET 0x00000005
|
|
#define CYFLD_BLE_BLELL_SCA_2__SIZE 0x00000003
|
|
#define CYREG_BLE_BLELL_PACKET_COUNTER0 0x402e1400
|
|
#define CYFLD_BLE_BLELL_PACKET_COUNTER_LOWER__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_PACKET_COUNTER_LOWER__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_PACKET_COUNTER1 0x402e1404
|
|
#define CYFLD_BLE_BLELL_PACKET_COUNTER_MIDDLE__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_PACKET_COUNTER_MIDDLE__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_PACKET_COUNTER2 0x402e1408
|
|
#define CYFLD_BLE_BLELL_PACKET_COUNTER_UPPER__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_PACKET_COUNTER_UPPER__SIZE 0x00000008
|
|
#define CYREG_BLE_BLELL_IV_MASTER0 0x402e1410
|
|
#define CYFLD_BLE_BLELL_IV_MASTER_LOWER__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_IV_MASTER_LOWER__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_IV_MASTER1 0x402e1414
|
|
#define CYFLD_BLE_BLELL_IV_MASTER_UPPER__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_IV_MASTER_UPPER__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_IV_SLAVE0 0x402e1418
|
|
#define CYFLD_BLE_BLELL_IV_SLAVE_LOWER__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_IV_SLAVE_LOWER__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_IV_SLAVE1 0x402e141c
|
|
#define CYFLD_BLE_BLELL_IV_SLAVE_UPPER__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_IV_SLAVE_UPPER__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_ENC_KEY0 0x402e1420
|
|
#define CYFLD_BLE_BLELL_ENC_KEY__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_ENC_KEY__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_ENC_KEY1 0x402e1424
|
|
#define CYREG_BLE_BLELL_ENC_KEY2 0x402e1428
|
|
#define CYREG_BLE_BLELL_ENC_KEY3 0x402e142c
|
|
#define CYREG_BLE_BLELL_ENC_KEY4 0x402e1430
|
|
#define CYREG_BLE_BLELL_ENC_KEY5 0x402e1434
|
|
#define CYREG_BLE_BLELL_ENC_KEY6 0x402e1438
|
|
#define CYREG_BLE_BLELL_ENC_KEY7 0x402e143c
|
|
#define CYREG_BLE_BLELL_DATA0 0x402e1440
|
|
#define CYFLD_BLE_BLELL_DATA0__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_DATA0__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_DATA1 0x402e1444
|
|
#define CYFLD_BLE_BLELL_DATA1__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_DATA1__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_DATA2 0x402e1448
|
|
#define CYFLD_BLE_BLELL_DATA2__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_DATA2__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_DATA3 0x402e144c
|
|
#define CYFLD_BLE_BLELL_DATA3__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_DATA3__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_DATA4 0x402e1450
|
|
#define CYFLD_BLE_BLELL_DATA4__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_DATA4__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_DATA5 0x402e1454
|
|
#define CYFLD_BLE_BLELL_DATA5__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_DATA5__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_DATA6 0x402e1458
|
|
#define CYFLD_BLE_BLELL_DATA6__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_DATA6__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_DATA7 0x402e145c
|
|
#define CYFLD_BLE_BLELL_DATA7__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_DATA7__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_DATA8 0x402e1460
|
|
#define CYFLD_BLE_BLELL_DATA8__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_DATA8__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_DATA9 0x402e1464
|
|
#define CYFLD_BLE_BLELL_DATA9__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_DATA9__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_DATA10 0x402e1468
|
|
#define CYFLD_BLE_BLELL_DATA10__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_DATA10__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_DATA11 0x402e146c
|
|
#define CYFLD_BLE_BLELL_DATA11__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_DATA11__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_DATA12 0x402e1470
|
|
#define CYFLD_BLE_BLELL_DATA12__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_DATA12__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_DATA13 0x402e1474
|
|
#define CYFLD_BLE_BLELL_DATA13__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_DATA13__SIZE 0x00000008
|
|
#define CYREG_BLE_BLELL_MIC_IN0 0x402e1478
|
|
#define CYFLD_BLE_BLELL_MIC_IN_LOWER__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_MIC_IN_LOWER__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_MIC_IN1 0x402e147c
|
|
#define CYFLD_BLE_BLELL_MIC_IN_UPPER__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_MIC_IN_UPPER__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_MIC_OUT0 0x402e1480
|
|
#define CYFLD_BLE_BLELL_MIC_OUT_LOWER__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_MIC_OUT_LOWER__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_MIC_OUT1 0x402e1484
|
|
#define CYFLD_BLE_BLELL_MIC_OUT_UPPER__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_MIC_OUT_UPPER__SIZE 0x00000010
|
|
#define CYREG_BLE_BLELL_ENC_PARAMS 0x402e1488
|
|
#define CYFLD_BLE_BLELL_DATA_PDU_HEADER__OFFSET 0x00000000
|
|
#define CYFLD_BLE_BLELL_DATA_PDU_HEADER__SIZE 0x00000002
|
|
#define CYFLD_BLE_BLELL_PAYLOAD_LENGTH__OFFSET 0x00000002
|
|
#define CYFLD_BLE_BLELL_PAYLOAD_LENGTH__SIZE 0x00000005
|
|
#define CYFLD_BLE_BLELL_DIRECTION__OFFSET 0x00000007
|
|
#define CYFLD_BLE_BLELL_DIRECTION__SIZE 0x00000001
|
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#define CYREG_BLE_BLELL_ENC_CONFIG 0x402e1490
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#define CYFLD_BLE_BLELL_START_PROC__OFFSET 0x00000000
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#define CYFLD_BLE_BLELL_START_PROC__SIZE 0x00000001
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#define CYFLD_BLE_BLELL_ECB_CCM__OFFSET 0x00000001
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#define CYFLD_BLE_BLELL_ECB_CCM__SIZE 0x00000001
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#define CYFLD_BLE_BLELL_DEC_ENC__OFFSET 0x00000002
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#define CYFLD_BLE_BLELL_DEC_ENC__SIZE 0x00000001
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#define CYREG_BLE_BLELL_ENC_INTR_EN 0x402e1498
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#define CYFLD_BLE_BLELL_AUTH_PASS_INTR_EN__OFFSET 0x00000000
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#define CYFLD_BLE_BLELL_AUTH_PASS_INTR_EN__SIZE 0x00000001
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#define CYFLD_BLE_BLELL_ECB_PROC_INTR_EN__OFFSET 0x00000001
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#define CYFLD_BLE_BLELL_ECB_PROC_INTR_EN__SIZE 0x00000001
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#define CYFLD_BLE_BLELL_CCM_PROC_INTR_EN__OFFSET 0x00000002
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#define CYFLD_BLE_BLELL_CCM_PROC_INTR_EN__SIZE 0x00000001
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#define CYREG_BLE_BLELL_ENC_INTR 0x402e14a0
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#define CYFLD_BLE_BLELL_AUTH_PASS_INTR__OFFSET 0x00000000
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#define CYFLD_BLE_BLELL_AUTH_PASS_INTR__SIZE 0x00000001
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#define CYFLD_BLE_BLELL_ECB_PROC_INTR__OFFSET 0x00000001
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#define CYFLD_BLE_BLELL_ECB_PROC_INTR__SIZE 0x00000001
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#define CYFLD_BLE_BLELL_CCM_PROC_INTR__OFFSET 0x00000002
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#define CYFLD_BLE_BLELL_CCM_PROC_INTR__SIZE 0x00000001
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#define CYFLD_BLE_BLELL_IN_DATA_CLEAR__OFFSET 0x00000003
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#define CYFLD_BLE_BLELL_IN_DATA_CLEAR__SIZE 0x00000001
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#define CYREG_BLE_BLELL_CONN_TXMEM_BASE_ADDR 0x402e1600
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#define CYFLD_BLE_BLELL_CONN_TX_MEM_BASE_ADDR__OFFSET 0x00000000
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#define CYFLD_BLE_BLELL_CONN_TX_MEM_BASE_ADDR__SIZE 0x00000010
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#define CYREG_BLE_BLELL_CONN_RXMEM_BASE_ADDR 0x402e1800
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#define CYFLD_BLE_BLELL_CONN_RX_MEM_BASE_ADDR__OFFSET 0x00000000
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#define CYFLD_BLE_BLELL_CONN_RX_MEM_BASE_ADDR__SIZE 0x00000010
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#define CYREG_BLE_BLELL_PDU_RESP_TIMER 0x402e1a04
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#define CYFLD_BLE_BLELL_PDU_RESP_TIME_VAL__OFFSET 0x00000000
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#define CYFLD_BLE_BLELL_PDU_RESP_TIME_VAL__SIZE 0x00000010
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#define CYREG_BLE_BLELL_NEXT_RESP_TIMER_EXP 0x402e1a08
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#define CYFLD_BLE_BLELL_NEXT_RESPONSE_INSTANT__OFFSET 0x00000000
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#define CYFLD_BLE_BLELL_NEXT_RESPONSE_INSTANT__SIZE 0x00000010
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#define CYREG_BLE_BLELL_NEXT_SUP_TO 0x402e1a0c
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#define CYFLD_BLE_BLELL_NEXT_TIMEOUT_INSTANT__OFFSET 0x00000000
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#define CYFLD_BLE_BLELL_NEXT_TIMEOUT_INSTANT__SIZE 0x00000010
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#define CYREG_BLE_BLELL_LLH_FEATURE_CONFIG 0x402e1a10
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#define CYFLD_BLE_BLELL_QUICK_TRANSMIT__OFFSET 0x00000000
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#define CYFLD_BLE_BLELL_QUICK_TRANSMIT__SIZE 0x00000001
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#define CYFLD_BLE_BLELL_SL_DSM_EN__OFFSET 0x00000001
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#define CYFLD_BLE_BLELL_SL_DSM_EN__SIZE 0x00000001
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#define CYREG_BLE_BLELL_WIN_MIN_STEP_SIZE 0x402e1a14
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#define CYFLD_BLE_BLELL_STEPDN__OFFSET 0x00000000
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#define CYFLD_BLE_BLELL_STEPDN__SIZE 0x00000004
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#define CYFLD_BLE_BLELL_STEPUP__OFFSET 0x00000004
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#define CYFLD_BLE_BLELL_STEPUP__SIZE 0x00000004
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#define CYFLD_BLE_BLELL_WINDOW_MIN_FW__OFFSET 0x00000008
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#define CYFLD_BLE_BLELL_WINDOW_MIN_FW__SIZE 0x00000008
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#define CYREG_BLE_BLELL_SLV_WIN_ADJ 0x402e1a18
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#define CYFLD_BLE_BLELL_SLV_WIN_ADJ__OFFSET 0x00000000
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#define CYFLD_BLE_BLELL_SLV_WIN_ADJ__SIZE 0x0000000b
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#define CYREG_BLE_BLELL_SL_CONN_INTERVAL 0x402e1a1c
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#define CYREG_BLE_BLELL_LE_PING_TIMER_ADDR 0x402e1a20
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#define CYFLD_BLE_BLELL_CONN_PING_TIMER_ADDR__OFFSET 0x00000000
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#define CYFLD_BLE_BLELL_CONN_PING_TIMER_ADDR__SIZE 0x00000010
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#define CYREG_BLE_BLELL_LE_PING_TIMER_OFFSET 0x402e1a24
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#define CYFLD_BLE_BLELL_CONN_PING_TIMER_OFFSET__OFFSET 0x00000000
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#define CYFLD_BLE_BLELL_CONN_PING_TIMER_OFFSET__SIZE 0x00000010
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#define CYREG_BLE_BLELL_LE_PING_TIMER_NEXT_EXP 0x402e1a28
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#define CYFLD_BLE_BLELL_CONN_PING_TIMER_NEXT_EXP__OFFSET 0x00000000
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#define CYFLD_BLE_BLELL_CONN_PING_TIMER_NEXT_EXP__SIZE 0x00000010
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#define CYREG_BLE_BLELL_LE_PING_TIMER_WRAP_COUNT 0x402e1a2c
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#define CYFLD_BLE_BLELL_CONN_SEC_CURRENT_WRAP__OFFSET 0x00000000
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#define CYFLD_BLE_BLELL_CONN_SEC_CURRENT_WRAP__SIZE 0x00000010
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#define CYREG_BLE_BLELL_TX_EN_EXT_DELAY 0x402e1e00
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#define CYFLD_BLE_BLELL_TXEN_EXT_DELAY__OFFSET 0x00000000
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#define CYFLD_BLE_BLELL_TXEN_EXT_DELAY__SIZE 0x00000005
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#define CYREG_BLE_BLELL_TX_RX_SYNTH_DELAY 0x402e1e04
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#define CYFLD_BLE_BLELL_RX_EN_DELAY__OFFSET 0x00000000
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#define CYFLD_BLE_BLELL_RX_EN_DELAY__SIZE 0x00000008
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#define CYFLD_BLE_BLELL_TX_EN_DELAY__OFFSET 0x00000008
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#define CYFLD_BLE_BLELL_TX_EN_DELAY__SIZE 0x00000008
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#define CYDEV_BLE_BLESS_BASE 0x402ef000
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#define CYDEV_BLE_BLESS_SIZE 0x00001000
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#define CYREG_BLE_BLESS_WCO_CONFIG 0x402ef000
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#define CYFLD_BLE_BLESS_LPM_EN__OFFSET 0x00000000
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#define CYFLD_BLE_BLESS_LPM_EN__SIZE 0x00000001
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#define CYFLD_BLE_BLESS_LPM_AUTO__OFFSET 0x00000001
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#define CYFLD_BLE_BLESS_LPM_AUTO__SIZE 0x00000001
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#define CYFLD_BLE_BLESS_EXT_INPUT_EN__OFFSET 0x00000002
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#define CYFLD_BLE_BLESS_EXT_INPUT_EN__SIZE 0x00000001
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#define CYFLD_BLE_BLESS_ENBUS__OFFSET 0x00000010
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#define CYFLD_BLE_BLESS_ENBUS__SIZE 0x00000008
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#define CYFLD_BLE_BLESS_ENABLE__OFFSET 0x0000001f
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#define CYFLD_BLE_BLESS_ENABLE__SIZE 0x00000001
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#define CYREG_BLE_BLESS_WCO_STATUS 0x402ef004
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#define CYFLD_BLE_BLESS_OUT_BLNK_A__OFFSET 0x00000000
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#define CYFLD_BLE_BLESS_OUT_BLNK_A__SIZE 0x00000001
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#define CYREG_BLE_BLESS_RF_CONFIG 0x402ef060
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#define CYFLD_BLE_BLESS_RF_ENABLE__OFFSET 0x00000000
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#define CYFLD_BLE_BLESS_RF_ENABLE__SIZE 0x00000001
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#define CYFLD_BLE_BLESS_DDFT_MUX_CFG1__OFFSET 0x00000004
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#define CYFLD_BLE_BLESS_DDFT_MUX_CFG1__SIZE 0x00000004
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#define CYFLD_BLE_BLESS_DDFT_MUX_CFG2__OFFSET 0x00000008
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#define CYFLD_BLE_BLESS_DDFT_MUX_CFG2__SIZE 0x00000004
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#define CYFLD_BLE_BLESS_BPKTCTL_FW__OFFSET 0x0000000e
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#define CYFLD_BLE_BLESS_BPKTCTL_FW__SIZE 0x00000001
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#define CYFLD_BLE_BLESS_BPKTCTL_FW_DRIVE__OFFSET 0x0000000f
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#define CYFLD_BLE_BLESS_BPKTCTL_FW_DRIVE__SIZE 0x00000001
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#define CYREG_BLE_BLESS_XTAL_CLK_DIV_CONFIG 0x402ef064
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#define CYFLD_BLE_BLESS_SYSCLK_DIV__OFFSET 0x00000000
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#define CYFLD_BLE_BLESS_SYSCLK_DIV__SIZE 0x00000002
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#define CYFLD_BLE_BLESS_LLCLK_DIV__OFFSET 0x00000002
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#define CYFLD_BLE_BLESS_LLCLK_DIV__SIZE 0x00000002
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#define CYREG_BLE_BLESS_LL_DSM_INTR_STAT 0x402ef068
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#define CYFLD_BLE_BLESS_DSM_ENTERED_INTR__OFFSET 0x00000000
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#define CYFLD_BLE_BLESS_DSM_ENTERED_INTR__SIZE 0x00000001
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#define CYFLD_BLE_BLESS_DSM_EXITED_INTR__OFFSET 0x00000001
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#define CYFLD_BLE_BLESS_DSM_EXITED_INTR__SIZE 0x00000001
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#define CYFLD_BLE_BLESS_XTAL_ON_INTR__OFFSET 0x00000008
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#define CYFLD_BLE_BLESS_XTAL_ON_INTR__SIZE 0x00000001
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#define CYREG_BLE_BLESS_LL_DSM_CTRL 0x402ef06c
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#define CYFLD_BLE_BLESS_DSM_EXIT__OFFSET 0x00000000
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#define CYFLD_BLE_BLESS_DSM_EXIT__SIZE 0x00000001
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#define CYFLD_BLE_BLESS_DSM_ENTERED_INTR_MASK__OFFSET 0x00000001
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#define CYFLD_BLE_BLESS_DSM_ENTERED_INTR_MASK__SIZE 0x00000001
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#define CYFLD_BLE_BLESS_DSM_EXITED_INTR_MASK__OFFSET 0x00000002
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#define CYFLD_BLE_BLESS_DSM_EXITED_INTR_MASK__SIZE 0x00000001
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#define CYFLD_BLE_BLESS_XTAL_ON_INTR_MASK__OFFSET 0x00000003
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#define CYFLD_BLE_BLESS_XTAL_ON_INTR_MASK__SIZE 0x00000001
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#define CYREG_BLE_BLESS_LL_CLK_EN 0x402ef070
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#define CYFLD_BLE_BLESS_CLK_EN__OFFSET 0x00000000
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#define CYFLD_BLE_BLESS_CLK_EN__SIZE 0x00000001
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#define CYFLD_BLE_BLESS_CY_CORREL_EN__OFFSET 0x00000001
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#define CYFLD_BLE_BLESS_CY_CORREL_EN__SIZE 0x00000001
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#define CYREG_BLE_BLESS_LF_CLK_CTRL 0x402ef074
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#define CYFLD_BLE_BLESS_DISABLE_LF_CLK__OFFSET 0x00000000
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#define CYFLD_BLE_BLESS_DISABLE_LF_CLK__SIZE 0x00000001
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#define CYREG_BLE_BLESS_WCO_TRIM 0x402eff00
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#define CYFLD_BLE_BLESS_XGM__OFFSET 0x00000000
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#define CYFLD_BLE_BLESS_XGM__SIZE 0x00000003
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#define CYFLD_BLE_BLESS_LPM_GM__OFFSET 0x00000004
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#define CYFLD_BLE_BLESS_LPM_GM__SIZE 0x00000002
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#define CYDEV_CTBM0_BASE 0x40300000
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#define CYDEV_CTBM0_SIZE 0x00010000
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#define CYREG_CTBM0_CTB_CTRL 0x40300000
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#define CYFLD_CTBM_DEEPSLEEP_ON__OFFSET 0x0000001e
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#define CYFLD_CTBM_DEEPSLEEP_ON__SIZE 0x00000001
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#define CYFLD_CTBM_ENABLED__OFFSET 0x0000001f
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#define CYFLD_CTBM_ENABLED__SIZE 0x00000001
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#define CYREG_CTBM0_OA_RES0_CTRL 0x40300004
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#define CYFLD_CTBM_OA0_PWR_MODE__OFFSET 0x00000000
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#define CYFLD_CTBM_OA0_PWR_MODE__SIZE 0x00000002
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#define CYFLD_CTBM_OA0_DRIVE_STR_SEL__OFFSET 0x00000002
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#define CYFLD_CTBM_OA0_DRIVE_STR_SEL__SIZE 0x00000001
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#define CYFLD_CTBM_OA0_COMP_EN__OFFSET 0x00000004
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#define CYFLD_CTBM_OA0_COMP_EN__SIZE 0x00000001
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#define CYFLD_CTBM_OA0_HYST_EN__OFFSET 0x00000005
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#define CYFLD_CTBM_OA0_HYST_EN__SIZE 0x00000001
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#define CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__OFFSET 0x00000006
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#define CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__SIZE 0x00000001
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#define CYFLD_CTBM_OA0_DSI_LEVEL__OFFSET 0x00000007
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#define CYFLD_CTBM_OA0_DSI_LEVEL__SIZE 0x00000001
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#define CYFLD_CTBM_OA0_COMPINT__OFFSET 0x00000008
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#define CYFLD_CTBM_OA0_COMPINT__SIZE 0x00000002
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#define CYVAL_CTBM_OA0_COMPINT_DISABLE 0x00000000
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#define CYVAL_CTBM_OA0_COMPINT_RISING 0x00000001
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#define CYVAL_CTBM_OA0_COMPINT_FALLING 0x00000002
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#define CYVAL_CTBM_OA0_COMPINT_BOTH 0x00000003
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#define CYFLD_CTBM_OA0_PUMP_EN__OFFSET 0x0000000b
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#define CYFLD_CTBM_OA0_PUMP_EN__SIZE 0x00000001
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#define CYREG_CTBM0_OA_RES1_CTRL 0x40300008
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#define CYFLD_CTBM_OA1_PWR_MODE__OFFSET 0x00000000
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#define CYFLD_CTBM_OA1_PWR_MODE__SIZE 0x00000002
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#define CYFLD_CTBM_OA1_DRIVE_STR_SEL__OFFSET 0x00000002
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#define CYFLD_CTBM_OA1_DRIVE_STR_SEL__SIZE 0x00000001
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#define CYFLD_CTBM_OA1_COMP_EN__OFFSET 0x00000004
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#define CYFLD_CTBM_OA1_COMP_EN__SIZE 0x00000001
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#define CYFLD_CTBM_OA1_HYST_EN__OFFSET 0x00000005
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#define CYFLD_CTBM_OA1_HYST_EN__SIZE 0x00000001
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#define CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__OFFSET 0x00000006
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#define CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__SIZE 0x00000001
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#define CYFLD_CTBM_OA1_DSI_LEVEL__OFFSET 0x00000007
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#define CYFLD_CTBM_OA1_DSI_LEVEL__SIZE 0x00000001
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#define CYFLD_CTBM_OA1_COMPINT__OFFSET 0x00000008
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#define CYFLD_CTBM_OA1_COMPINT__SIZE 0x00000002
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#define CYVAL_CTBM_OA1_COMPINT_DISABLE 0x00000000
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#define CYVAL_CTBM_OA1_COMPINT_RISING 0x00000001
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#define CYVAL_CTBM_OA1_COMPINT_FALLING 0x00000002
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#define CYVAL_CTBM_OA1_COMPINT_BOTH 0x00000003
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#define CYFLD_CTBM_OA1_PUMP_EN__OFFSET 0x0000000b
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#define CYFLD_CTBM_OA1_PUMP_EN__SIZE 0x00000001
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#define CYREG_CTBM0_COMP_STAT 0x4030000c
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#define CYFLD_CTBM_OA0_COMP__OFFSET 0x00000000
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#define CYFLD_CTBM_OA0_COMP__SIZE 0x00000001
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#define CYFLD_CTBM_OA1_COMP__OFFSET 0x00000010
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#define CYFLD_CTBM_OA1_COMP__SIZE 0x00000001
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#define CYREG_CTBM0_INTR 0x40300020
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#define CYFLD_CTBM_COMP0__OFFSET 0x00000000
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#define CYFLD_CTBM_COMP0__SIZE 0x00000001
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#define CYFLD_CTBM_COMP1__OFFSET 0x00000001
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#define CYFLD_CTBM_COMP1__SIZE 0x00000001
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#define CYREG_CTBM0_INTR_SET 0x40300024
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#define CYFLD_CTBM_COMP0_SET__OFFSET 0x00000000
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#define CYFLD_CTBM_COMP0_SET__SIZE 0x00000001
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#define CYFLD_CTBM_COMP1_SET__OFFSET 0x00000001
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#define CYFLD_CTBM_COMP1_SET__SIZE 0x00000001
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#define CYREG_CTBM0_INTR_MASK 0x40300028
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#define CYFLD_CTBM_COMP0_MASK__OFFSET 0x00000000
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#define CYFLD_CTBM_COMP0_MASK__SIZE 0x00000001
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#define CYFLD_CTBM_COMP1_MASK__OFFSET 0x00000001
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#define CYFLD_CTBM_COMP1_MASK__SIZE 0x00000001
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#define CYREG_CTBM0_INTR_MASKED 0x4030002c
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#define CYFLD_CTBM_COMP0_MASKED__OFFSET 0x00000000
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#define CYFLD_CTBM_COMP0_MASKED__SIZE 0x00000001
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#define CYFLD_CTBM_COMP1_MASKED__OFFSET 0x00000001
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#define CYFLD_CTBM_COMP1_MASKED__SIZE 0x00000001
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#define CYREG_CTBM0_DFT_CTRL 0x40300030
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#define CYFLD_CTBM_DFT_MODE__OFFSET 0x00000000
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#define CYFLD_CTBM_DFT_MODE__SIZE 0x00000003
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#define CYFLD_CTBM_DFT_EN__OFFSET 0x0000001f
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#define CYFLD_CTBM_DFT_EN__SIZE 0x00000001
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#define CYREG_CTBM0_OA0_SW 0x40300080
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#define CYFLD_CTBM_OA0P_A00__OFFSET 0x00000000
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#define CYFLD_CTBM_OA0P_A00__SIZE 0x00000001
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#define CYFLD_CTBM_OA0P_A20__OFFSET 0x00000002
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#define CYFLD_CTBM_OA0P_A20__SIZE 0x00000001
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#define CYFLD_CTBM_OA0P_A30__OFFSET 0x00000003
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#define CYFLD_CTBM_OA0P_A30__SIZE 0x00000001
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#define CYFLD_CTBM_OA0M_A11__OFFSET 0x00000008
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#define CYFLD_CTBM_OA0M_A11__SIZE 0x00000001
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#define CYFLD_CTBM_OA0M_A81__OFFSET 0x0000000e
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#define CYFLD_CTBM_OA0M_A81__SIZE 0x00000001
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#define CYFLD_CTBM_OA0O_D51__OFFSET 0x00000012
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#define CYFLD_CTBM_OA0O_D51__SIZE 0x00000001
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#define CYFLD_CTBM_OA0O_D81__OFFSET 0x00000015
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#define CYFLD_CTBM_OA0O_D81__SIZE 0x00000001
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#define CYREG_CTBM0_OA0_SW_CLEAR 0x40300084
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#define CYREG_CTBM0_OA1_SW 0x40300088
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#define CYFLD_CTBM_OA1P_A03__OFFSET 0x00000000
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#define CYFLD_CTBM_OA1P_A03__SIZE 0x00000001
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#define CYFLD_CTBM_OA1P_A13__OFFSET 0x00000001
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#define CYFLD_CTBM_OA1P_A13__SIZE 0x00000001
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#define CYFLD_CTBM_OA1P_A43__OFFSET 0x00000004
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#define CYFLD_CTBM_OA1P_A43__SIZE 0x00000001
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#define CYFLD_CTBM_OA1M_A22__OFFSET 0x00000008
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#define CYFLD_CTBM_OA1M_A22__SIZE 0x00000001
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#define CYFLD_CTBM_OA1M_A82__OFFSET 0x0000000e
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#define CYFLD_CTBM_OA1M_A82__SIZE 0x00000001
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#define CYFLD_CTBM_OA1O_D52__OFFSET 0x00000012
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#define CYFLD_CTBM_OA1O_D52__SIZE 0x00000001
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#define CYFLD_CTBM_OA1O_D62__OFFSET 0x00000013
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#define CYFLD_CTBM_OA1O_D62__SIZE 0x00000001
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#define CYFLD_CTBM_OA1O_D82__OFFSET 0x00000015
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#define CYFLD_CTBM_OA1O_D82__SIZE 0x00000001
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#define CYREG_CTBM0_OA1_SW_CLEAR 0x4030008c
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#define CYREG_CTBM0_CTB_SW_HW_CTRL 0x403000c0
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#define CYFLD_CTBM_P2_HW_CTRL__OFFSET 0x00000002
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#define CYFLD_CTBM_P2_HW_CTRL__SIZE 0x00000001
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#define CYFLD_CTBM_P3_HW_CTRL__OFFSET 0x00000003
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#define CYFLD_CTBM_P3_HW_CTRL__SIZE 0x00000001
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#define CYREG_CTBM0_CTB_SW_STATUS 0x403000c4
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#define CYFLD_CTBM_OA0O_D51_STAT__OFFSET 0x0000001c
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#define CYFLD_CTBM_OA0O_D51_STAT__SIZE 0x00000001
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#define CYFLD_CTBM_OA1O_D52_STAT__OFFSET 0x0000001d
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#define CYFLD_CTBM_OA1O_D52_STAT__SIZE 0x00000001
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#define CYFLD_CTBM_OA1O_D62_STAT__OFFSET 0x0000001e
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#define CYFLD_CTBM_OA1O_D62_STAT__SIZE 0x00000001
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#define CYREG_CTBM0_OA0_OFFSET_TRIM 0x40300f00
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#define CYFLD_CTBM_OA0_OFFSET_TRIM__OFFSET 0x00000000
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#define CYFLD_CTBM_OA0_OFFSET_TRIM__SIZE 0x00000006
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#define CYREG_CTBM0_OA0_SLOPE_OFFSET_TRIM 0x40300f04
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#define CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__OFFSET 0x00000000
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#define CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__SIZE 0x00000006
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#define CYREG_CTBM0_OA0_COMP_TRIM 0x40300f08
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#define CYFLD_CTBM_OA0_COMP_TRIM__OFFSET 0x00000000
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#define CYFLD_CTBM_OA0_COMP_TRIM__SIZE 0x00000002
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#define CYREG_CTBM0_OA1_OFFSET_TRIM 0x40300f0c
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#define CYFLD_CTBM_OA1_OFFSET_TRIM__OFFSET 0x00000000
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#define CYFLD_CTBM_OA1_OFFSET_TRIM__SIZE 0x00000006
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#define CYREG_CTBM0_OA1_SLOPE_OFFSET_TRIM 0x40300f10
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#define CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__OFFSET 0x00000000
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#define CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__SIZE 0x00000006
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#define CYREG_CTBM0_OA1_COMP_TRIM 0x40300f14
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#define CYFLD_CTBM_OA1_COMP_TRIM__OFFSET 0x00000000
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#define CYFLD_CTBM_OA1_COMP_TRIM__SIZE 0x00000002
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#define CYDEV_CTBM1_BASE 0x40310000
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#define CYDEV_CTBM1_SIZE 0x00010000
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#define CYREG_CTBM1_CTB_CTRL 0x40310000
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#define CYREG_CTBM1_OA_RES0_CTRL 0x40310004
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#define CYREG_CTBM1_OA_RES1_CTRL 0x40310008
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#define CYREG_CTBM1_COMP_STAT 0x4031000c
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#define CYREG_CTBM1_INTR 0x40310020
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#define CYREG_CTBM1_INTR_SET 0x40310024
|
|
#define CYREG_CTBM1_INTR_MASK 0x40310028
|
|
#define CYREG_CTBM1_INTR_MASKED 0x4031002c
|
|
#define CYREG_CTBM1_DFT_CTRL 0x40310030
|
|
#define CYREG_CTBM1_OA0_SW 0x40310080
|
|
#define CYREG_CTBM1_OA0_SW_CLEAR 0x40310084
|
|
#define CYREG_CTBM1_OA1_SW 0x40310088
|
|
#define CYREG_CTBM1_OA1_SW_CLEAR 0x4031008c
|
|
#define CYREG_CTBM1_CTB_SW_HW_CTRL 0x403100c0
|
|
#define CYREG_CTBM1_CTB_SW_STATUS 0x403100c4
|
|
#define CYREG_CTBM1_OA0_OFFSET_TRIM 0x40310f00
|
|
#define CYREG_CTBM1_OA0_SLOPE_OFFSET_TRIM 0x40310f04
|
|
#define CYREG_CTBM1_OA0_COMP_TRIM 0x40310f08
|
|
#define CYREG_CTBM1_OA1_OFFSET_TRIM 0x40310f0c
|
|
#define CYREG_CTBM1_OA1_SLOPE_OFFSET_TRIM 0x40310f10
|
|
#define CYREG_CTBM1_OA1_COMP_TRIM 0x40310f14
|
|
#define CYDEV_SAR_BASE 0x403a0000
|
|
#define CYDEV_SAR_SIZE 0x00010000
|
|
#define CYREG_SAR_CTRL 0x403a0000
|
|
#define CYFLD_SAR_VREF_SEL__OFFSET 0x00000004
|
|
#define CYFLD_SAR_VREF_SEL__SIZE 0x00000003
|
|
#define CYVAL_SAR_VREF_SEL_VREF0 0x00000000
|
|
#define CYVAL_SAR_VREF_SEL_VREF1 0x00000001
|
|
#define CYVAL_SAR_VREF_SEL_VREF2 0x00000002
|
|
#define CYVAL_SAR_VREF_SEL_VREF_AROUTE 0x00000003
|
|
#define CYVAL_SAR_VREF_SEL_VBGR 0x00000004
|
|
#define CYVAL_SAR_VREF_SEL_VREF_EXT 0x00000005
|
|
#define CYVAL_SAR_VREF_SEL_VDDA_DIV_2 0x00000006
|
|
#define CYVAL_SAR_VREF_SEL_VDDA 0x00000007
|
|
#define CYFLD_SAR_VREF_BYP_CAP_EN__OFFSET 0x00000007
|
|
#define CYFLD_SAR_VREF_BYP_CAP_EN__SIZE 0x00000001
|
|
#define CYFLD_SAR_NEG_SEL__OFFSET 0x00000009
|
|
#define CYFLD_SAR_NEG_SEL__SIZE 0x00000003
|
|
#define CYVAL_SAR_NEG_SEL_VSSA_KELVIN 0x00000000
|
|
#define CYVAL_SAR_NEG_SEL_ART_VSSA 0x00000001
|
|
#define CYVAL_SAR_NEG_SEL_P1 0x00000002
|
|
#define CYVAL_SAR_NEG_SEL_P3 0x00000003
|
|
#define CYVAL_SAR_NEG_SEL_P5 0x00000004
|
|
#define CYVAL_SAR_NEG_SEL_P7 0x00000005
|
|
#define CYVAL_SAR_NEG_SEL_ACORE 0x00000006
|
|
#define CYVAL_SAR_NEG_SEL_VREF 0x00000007
|
|
#define CYFLD_SAR_SAR_HW_CTRL_NEGVREF__OFFSET 0x0000000d
|
|
#define CYFLD_SAR_SAR_HW_CTRL_NEGVREF__SIZE 0x00000001
|
|
#define CYFLD_SAR_PWR_CTRL_VREF__OFFSET 0x0000000e
|
|
#define CYFLD_SAR_PWR_CTRL_VREF__SIZE 0x00000002
|
|
#define CYVAL_SAR_PWR_CTRL_VREF_NORMAL_PWR 0x00000000
|
|
#define CYVAL_SAR_PWR_CTRL_VREF_HALF_PWR 0x00000001
|
|
#define CYVAL_SAR_PWR_CTRL_VREF_THIRD_PWR 0x00000002
|
|
#define CYVAL_SAR_PWR_CTRL_VREF_QUARTER_PWR 0x00000003
|
|
#define CYFLD_SAR_SPARE__OFFSET 0x00000010
|
|
#define CYFLD_SAR_SPARE__SIZE 0x00000004
|
|
#define CYFLD_SAR_BOOSTPUMP_EN__OFFSET 0x00000014
|
|
#define CYFLD_SAR_BOOSTPUMP_EN__SIZE 0x00000001
|
|
#define CYFLD_SAR_ICONT_LV__OFFSET 0x00000018
|
|
#define CYFLD_SAR_ICONT_LV__SIZE 0x00000002
|
|
#define CYVAL_SAR_ICONT_LV_NORMAL_PWR 0x00000000
|
|
#define CYVAL_SAR_ICONT_LV_HALF_PWR 0x00000001
|
|
#define CYVAL_SAR_ICONT_LV_MORE_PWR 0x00000002
|
|
#define CYVAL_SAR_ICONT_LV_QUARTER_PWR 0x00000003
|
|
#define CYFLD_SAR_DEEPSLEEP_ON__OFFSET 0x0000001b
|
|
#define CYFLD_SAR_DEEPSLEEP_ON__SIZE 0x00000001
|
|
#define CYFLD_SAR_DSI_SYNC_CONFIG__OFFSET 0x0000001c
|
|
#define CYFLD_SAR_DSI_SYNC_CONFIG__SIZE 0x00000001
|
|
#define CYFLD_SAR_DSI_MODE__OFFSET 0x0000001d
|
|
#define CYFLD_SAR_DSI_MODE__SIZE 0x00000001
|
|
#define CYFLD_SAR_SWITCH_DISABLE__OFFSET 0x0000001e
|
|
#define CYFLD_SAR_SWITCH_DISABLE__SIZE 0x00000001
|
|
#define CYFLD_SAR_ENABLED__OFFSET 0x0000001f
|
|
#define CYFLD_SAR_ENABLED__SIZE 0x00000001
|
|
#define CYREG_SAR_SAMPLE_CTRL 0x403a0004
|
|
#define CYFLD_SAR_SUB_RESOLUTION__OFFSET 0x00000000
|
|
#define CYFLD_SAR_SUB_RESOLUTION__SIZE 0x00000001
|
|
#define CYVAL_SAR_SUB_RESOLUTION_8B 0x00000000
|
|
#define CYVAL_SAR_SUB_RESOLUTION_10B 0x00000001
|
|
#define CYFLD_SAR_LEFT_ALIGN__OFFSET 0x00000001
|
|
#define CYFLD_SAR_LEFT_ALIGN__SIZE 0x00000001
|
|
#define CYFLD_SAR_SINGLE_ENDED_SIGNED__OFFSET 0x00000002
|
|
#define CYFLD_SAR_SINGLE_ENDED_SIGNED__SIZE 0x00000001
|
|
#define CYVAL_SAR_SINGLE_ENDED_SIGNED_UNSIGNED 0x00000000
|
|
#define CYVAL_SAR_SINGLE_ENDED_SIGNED_SIGNED 0x00000001
|
|
#define CYFLD_SAR_DIFFERENTIAL_SIGNED__OFFSET 0x00000003
|
|
#define CYFLD_SAR_DIFFERENTIAL_SIGNED__SIZE 0x00000001
|
|
#define CYVAL_SAR_DIFFERENTIAL_SIGNED_UNSIGNED 0x00000000
|
|
#define CYVAL_SAR_DIFFERENTIAL_SIGNED_SIGNED 0x00000001
|
|
#define CYFLD_SAR_AVG_CNT__OFFSET 0x00000004
|
|
#define CYFLD_SAR_AVG_CNT__SIZE 0x00000003
|
|
#define CYFLD_SAR_AVG_SHIFT__OFFSET 0x00000007
|
|
#define CYFLD_SAR_AVG_SHIFT__SIZE 0x00000001
|
|
#define CYFLD_SAR_CONTINUOUS__OFFSET 0x00000010
|
|
#define CYFLD_SAR_CONTINUOUS__SIZE 0x00000001
|
|
#define CYFLD_SAR_DSI_TRIGGER_EN__OFFSET 0x00000011
|
|
#define CYFLD_SAR_DSI_TRIGGER_EN__SIZE 0x00000001
|
|
#define CYFLD_SAR_DSI_TRIGGER_LEVEL__OFFSET 0x00000012
|
|
#define CYFLD_SAR_DSI_TRIGGER_LEVEL__SIZE 0x00000001
|
|
#define CYFLD_SAR_DSI_SYNC_TRIGGER__OFFSET 0x00000013
|
|
#define CYFLD_SAR_DSI_SYNC_TRIGGER__SIZE 0x00000001
|
|
#define CYFLD_SAR_EOS_DSI_OUT_EN__OFFSET 0x0000001f
|
|
#define CYFLD_SAR_EOS_DSI_OUT_EN__SIZE 0x00000001
|
|
#define CYREG_SAR_SAMPLE_TIME01 0x403a0010
|
|
#define CYFLD_SAR_SAMPLE_TIME0__OFFSET 0x00000000
|
|
#define CYFLD_SAR_SAMPLE_TIME0__SIZE 0x0000000a
|
|
#define CYFLD_SAR_SAMPLE_TIME1__OFFSET 0x00000010
|
|
#define CYFLD_SAR_SAMPLE_TIME1__SIZE 0x0000000a
|
|
#define CYREG_SAR_SAMPLE_TIME23 0x403a0014
|
|
#define CYFLD_SAR_SAMPLE_TIME2__OFFSET 0x00000000
|
|
#define CYFLD_SAR_SAMPLE_TIME2__SIZE 0x0000000a
|
|
#define CYFLD_SAR_SAMPLE_TIME3__OFFSET 0x00000010
|
|
#define CYFLD_SAR_SAMPLE_TIME3__SIZE 0x0000000a
|
|
#define CYREG_SAR_RANGE_THRES 0x403a0018
|
|
#define CYFLD_SAR_RANGE_LOW__OFFSET 0x00000000
|
|
#define CYFLD_SAR_RANGE_LOW__SIZE 0x00000010
|
|
#define CYFLD_SAR_RANGE_HIGH__OFFSET 0x00000010
|
|
#define CYFLD_SAR_RANGE_HIGH__SIZE 0x00000010
|
|
#define CYREG_SAR_RANGE_COND 0x403a001c
|
|
#define CYFLD_SAR_RANGE_COND__OFFSET 0x0000001e
|
|
#define CYFLD_SAR_RANGE_COND__SIZE 0x00000002
|
|
#define CYVAL_SAR_RANGE_COND_BELOW 0x00000000
|
|
#define CYVAL_SAR_RANGE_COND_INSIDE 0x00000001
|
|
#define CYVAL_SAR_RANGE_COND_ABOVE 0x00000002
|
|
#define CYVAL_SAR_RANGE_COND_OUTSIDE 0x00000003
|
|
#define CYREG_SAR_CHAN_EN 0x403a0020
|
|
#define CYFLD_SAR_CHAN_EN__OFFSET 0x00000000
|
|
#define CYFLD_SAR_CHAN_EN__SIZE 0x00000010
|
|
#define CYREG_SAR_START_CTRL 0x403a0024
|
|
#define CYFLD_SAR_FW_TRIGGER__OFFSET 0x00000000
|
|
#define CYFLD_SAR_FW_TRIGGER__SIZE 0x00000001
|
|
#define CYREG_SAR_DFT_CTRL 0x403a0030
|
|
#define CYFLD_SAR_DLY_INC__OFFSET 0x00000000
|
|
#define CYFLD_SAR_DLY_INC__SIZE 0x00000001
|
|
#define CYFLD_SAR_HIZ__OFFSET 0x00000001
|
|
#define CYFLD_SAR_HIZ__SIZE 0x00000001
|
|
#define CYFLD_SAR_DFT_INC__OFFSET 0x00000010
|
|
#define CYFLD_SAR_DFT_INC__SIZE 0x00000004
|
|
#define CYFLD_SAR_DFT_OUTC__OFFSET 0x00000014
|
|
#define CYFLD_SAR_DFT_OUTC__SIZE 0x00000003
|
|
#define CYFLD_SAR_SEL_CSEL_DFT__OFFSET 0x00000018
|
|
#define CYFLD_SAR_SEL_CSEL_DFT__SIZE 0x00000004
|
|
#define CYFLD_SAR_EN_CSEL_DFT__OFFSET 0x0000001c
|
|
#define CYFLD_SAR_EN_CSEL_DFT__SIZE 0x00000001
|
|
#define CYFLD_SAR_DCEN__OFFSET 0x0000001d
|
|
#define CYFLD_SAR_DCEN__SIZE 0x00000001
|
|
#define CYFLD_SAR_ADFT_OVERRIDE__OFFSET 0x0000001f
|
|
#define CYFLD_SAR_ADFT_OVERRIDE__SIZE 0x00000001
|
|
#define CYREG_SAR_CHAN_CONFIG0 0x403a0080
|
|
#define CYFLD_SAR_PIN_ADDR__OFFSET 0x00000000
|
|
#define CYFLD_SAR_PIN_ADDR__SIZE 0x00000003
|
|
#define CYFLD_SAR_PORT_ADDR__OFFSET 0x00000004
|
|
#define CYFLD_SAR_PORT_ADDR__SIZE 0x00000003
|
|
#define CYVAL_SAR_PORT_ADDR_SARMUX 0x00000000
|
|
#define CYVAL_SAR_PORT_ADDR_CTB0 0x00000001
|
|
#define CYVAL_SAR_PORT_ADDR_CTB1 0x00000002
|
|
#define CYVAL_SAR_PORT_ADDR_CTB2 0x00000003
|
|
#define CYVAL_SAR_PORT_ADDR_CTB3 0x00000004
|
|
#define CYVAL_SAR_PORT_ADDR_AROUTE_VIRT2 0x00000005
|
|
#define CYVAL_SAR_PORT_ADDR_AROUTE_VIRT1 0x00000006
|
|
#define CYVAL_SAR_PORT_ADDR_SARMUX_VIRT 0x00000007
|
|
#define CYFLD_SAR_DIFFERENTIAL_EN__OFFSET 0x00000008
|
|
#define CYFLD_SAR_DIFFERENTIAL_EN__SIZE 0x00000001
|
|
#define CYFLD_SAR_RESOLUTION__OFFSET 0x00000009
|
|
#define CYFLD_SAR_RESOLUTION__SIZE 0x00000001
|
|
#define CYVAL_SAR_RESOLUTION_MAXRES 0x00000000
|
|
#define CYVAL_SAR_RESOLUTION_SUBRES 0x00000001
|
|
#define CYFLD_SAR_AVG_EN__OFFSET 0x0000000a
|
|
#define CYFLD_SAR_AVG_EN__SIZE 0x00000001
|
|
#define CYFLD_SAR_SAMPLE_TIME_SEL__OFFSET 0x0000000c
|
|
#define CYFLD_SAR_SAMPLE_TIME_SEL__SIZE 0x00000002
|
|
#define CYFLD_SAR_DSI_OUT_EN__OFFSET 0x0000001f
|
|
#define CYFLD_SAR_DSI_OUT_EN__SIZE 0x00000001
|
|
#define CYREG_SAR_CHAN_CONFIG1 0x403a0084
|
|
#define CYREG_SAR_CHAN_CONFIG2 0x403a0088
|
|
#define CYREG_SAR_CHAN_CONFIG3 0x403a008c
|
|
#define CYREG_SAR_CHAN_CONFIG4 0x403a0090
|
|
#define CYREG_SAR_CHAN_CONFIG5 0x403a0094
|
|
#define CYREG_SAR_CHAN_CONFIG6 0x403a0098
|
|
#define CYREG_SAR_CHAN_CONFIG7 0x403a009c
|
|
#define CYREG_SAR_CHAN_CONFIG8 0x403a00a0
|
|
#define CYREG_SAR_CHAN_CONFIG9 0x403a00a4
|
|
#define CYREG_SAR_CHAN_CONFIG10 0x403a00a8
|
|
#define CYREG_SAR_CHAN_CONFIG11 0x403a00ac
|
|
#define CYREG_SAR_CHAN_CONFIG12 0x403a00b0
|
|
#define CYREG_SAR_CHAN_CONFIG13 0x403a00b4
|
|
#define CYREG_SAR_CHAN_CONFIG14 0x403a00b8
|
|
#define CYREG_SAR_CHAN_CONFIG15 0x403a00bc
|
|
#define CYREG_SAR_CHAN_WORK0 0x403a0100
|
|
#define CYFLD_SAR_WORK__OFFSET 0x00000000
|
|
#define CYFLD_SAR_WORK__SIZE 0x00000010
|
|
#define CYFLD_SAR_CHAN_WORK_VALID_MIR__OFFSET 0x0000001f
|
|
#define CYFLD_SAR_CHAN_WORK_VALID_MIR__SIZE 0x00000001
|
|
#define CYREG_SAR_CHAN_WORK1 0x403a0104
|
|
#define CYREG_SAR_CHAN_WORK2 0x403a0108
|
|
#define CYREG_SAR_CHAN_WORK3 0x403a010c
|
|
#define CYREG_SAR_CHAN_WORK4 0x403a0110
|
|
#define CYREG_SAR_CHAN_WORK5 0x403a0114
|
|
#define CYREG_SAR_CHAN_WORK6 0x403a0118
|
|
#define CYREG_SAR_CHAN_WORK7 0x403a011c
|
|
#define CYREG_SAR_CHAN_WORK8 0x403a0120
|
|
#define CYREG_SAR_CHAN_WORK9 0x403a0124
|
|
#define CYREG_SAR_CHAN_WORK10 0x403a0128
|
|
#define CYREG_SAR_CHAN_WORK11 0x403a012c
|
|
#define CYREG_SAR_CHAN_WORK12 0x403a0130
|
|
#define CYREG_SAR_CHAN_WORK13 0x403a0134
|
|
#define CYREG_SAR_CHAN_WORK14 0x403a0138
|
|
#define CYREG_SAR_CHAN_WORK15 0x403a013c
|
|
#define CYREG_SAR_CHAN_RESULT0 0x403a0180
|
|
#define CYFLD_SAR_RESULT__OFFSET 0x00000000
|
|
#define CYFLD_SAR_RESULT__SIZE 0x00000010
|
|
#define CYFLD_SAR_SATURATE_INTR_MIR__OFFSET 0x0000001d
|
|
#define CYFLD_SAR_SATURATE_INTR_MIR__SIZE 0x00000001
|
|
#define CYFLD_SAR_RANGE_INTR_MIR__OFFSET 0x0000001e
|
|
#define CYFLD_SAR_RANGE_INTR_MIR__SIZE 0x00000001
|
|
#define CYFLD_SAR_CHAN_RESULT_VALID_MIR__OFFSET 0x0000001f
|
|
#define CYFLD_SAR_CHAN_RESULT_VALID_MIR__SIZE 0x00000001
|
|
#define CYREG_SAR_CHAN_RESULT1 0x403a0184
|
|
#define CYREG_SAR_CHAN_RESULT2 0x403a0188
|
|
#define CYREG_SAR_CHAN_RESULT3 0x403a018c
|
|
#define CYREG_SAR_CHAN_RESULT4 0x403a0190
|
|
#define CYREG_SAR_CHAN_RESULT5 0x403a0194
|
|
#define CYREG_SAR_CHAN_RESULT6 0x403a0198
|
|
#define CYREG_SAR_CHAN_RESULT7 0x403a019c
|
|
#define CYREG_SAR_CHAN_RESULT8 0x403a01a0
|
|
#define CYREG_SAR_CHAN_RESULT9 0x403a01a4
|
|
#define CYREG_SAR_CHAN_RESULT10 0x403a01a8
|
|
#define CYREG_SAR_CHAN_RESULT11 0x403a01ac
|
|
#define CYREG_SAR_CHAN_RESULT12 0x403a01b0
|
|
#define CYREG_SAR_CHAN_RESULT13 0x403a01b4
|
|
#define CYREG_SAR_CHAN_RESULT14 0x403a01b8
|
|
#define CYREG_SAR_CHAN_RESULT15 0x403a01bc
|
|
#define CYREG_SAR_CHAN_WORK_VALID 0x403a0200
|
|
#define CYFLD_SAR_CHAN_WORK_VALID__OFFSET 0x00000000
|
|
#define CYFLD_SAR_CHAN_WORK_VALID__SIZE 0x00000010
|
|
#define CYREG_SAR_CHAN_RESULT_VALID 0x403a0204
|
|
#define CYFLD_SAR_CHAN_RESULT_VALID__OFFSET 0x00000000
|
|
#define CYFLD_SAR_CHAN_RESULT_VALID__SIZE 0x00000010
|
|
#define CYREG_SAR_STATUS 0x403a0208
|
|
#define CYFLD_SAR_CUR_CHAN__OFFSET 0x00000000
|
|
#define CYFLD_SAR_CUR_CHAN__SIZE 0x00000005
|
|
#define CYFLD_SAR_SW_VREF_NEG__OFFSET 0x0000001e
|
|
#define CYFLD_SAR_SW_VREF_NEG__SIZE 0x00000001
|
|
#define CYFLD_SAR_BUSY__OFFSET 0x0000001f
|
|
#define CYFLD_SAR_BUSY__SIZE 0x00000001
|
|
#define CYREG_SAR_AVG_STAT 0x403a020c
|
|
#define CYFLD_SAR_CUR_AVG_ACCU__OFFSET 0x00000000
|
|
#define CYFLD_SAR_CUR_AVG_ACCU__SIZE 0x00000014
|
|
#define CYFLD_SAR_CUR_AVG_CNT__OFFSET 0x00000018
|
|
#define CYFLD_SAR_CUR_AVG_CNT__SIZE 0x00000008
|
|
#define CYREG_SAR_INTR 0x403a0210
|
|
#define CYFLD_SAR_EOS_INTR__OFFSET 0x00000000
|
|
#define CYFLD_SAR_EOS_INTR__SIZE 0x00000001
|
|
#define CYFLD_SAR_OVERFLOW_INTR__OFFSET 0x00000001
|
|
#define CYFLD_SAR_OVERFLOW_INTR__SIZE 0x00000001
|
|
#define CYFLD_SAR_FW_COLLISION_INTR__OFFSET 0x00000002
|
|
#define CYFLD_SAR_FW_COLLISION_INTR__SIZE 0x00000001
|
|
#define CYFLD_SAR_DSI_COLLISION_INTR__OFFSET 0x00000003
|
|
#define CYFLD_SAR_DSI_COLLISION_INTR__SIZE 0x00000001
|
|
#define CYFLD_SAR_INJ_EOC_INTR__OFFSET 0x00000004
|
|
#define CYFLD_SAR_INJ_EOC_INTR__SIZE 0x00000001
|
|
#define CYFLD_SAR_INJ_SATURATE_INTR__OFFSET 0x00000005
|
|
#define CYFLD_SAR_INJ_SATURATE_INTR__SIZE 0x00000001
|
|
#define CYFLD_SAR_INJ_RANGE_INTR__OFFSET 0x00000006
|
|
#define CYFLD_SAR_INJ_RANGE_INTR__SIZE 0x00000001
|
|
#define CYFLD_SAR_INJ_COLLISION_INTR__OFFSET 0x00000007
|
|
#define CYFLD_SAR_INJ_COLLISION_INTR__SIZE 0x00000001
|
|
#define CYREG_SAR_INTR_SET 0x403a0214
|
|
#define CYFLD_SAR_EOS_SET__OFFSET 0x00000000
|
|
#define CYFLD_SAR_EOS_SET__SIZE 0x00000001
|
|
#define CYFLD_SAR_OVERFLOW_SET__OFFSET 0x00000001
|
|
#define CYFLD_SAR_OVERFLOW_SET__SIZE 0x00000001
|
|
#define CYFLD_SAR_FW_COLLISION_SET__OFFSET 0x00000002
|
|
#define CYFLD_SAR_FW_COLLISION_SET__SIZE 0x00000001
|
|
#define CYFLD_SAR_DSI_COLLISION_SET__OFFSET 0x00000003
|
|
#define CYFLD_SAR_DSI_COLLISION_SET__SIZE 0x00000001
|
|
#define CYFLD_SAR_INJ_EOC_SET__OFFSET 0x00000004
|
|
#define CYFLD_SAR_INJ_EOC_SET__SIZE 0x00000001
|
|
#define CYFLD_SAR_INJ_SATURATE_SET__OFFSET 0x00000005
|
|
#define CYFLD_SAR_INJ_SATURATE_SET__SIZE 0x00000001
|
|
#define CYFLD_SAR_INJ_RANGE_SET__OFFSET 0x00000006
|
|
#define CYFLD_SAR_INJ_RANGE_SET__SIZE 0x00000001
|
|
#define CYFLD_SAR_INJ_COLLISION_SET__OFFSET 0x00000007
|
|
#define CYFLD_SAR_INJ_COLLISION_SET__SIZE 0x00000001
|
|
#define CYREG_SAR_INTR_MASK 0x403a0218
|
|
#define CYFLD_SAR_EOS_MASK__OFFSET 0x00000000
|
|
#define CYFLD_SAR_EOS_MASK__SIZE 0x00000001
|
|
#define CYFLD_SAR_OVERFLOW_MASK__OFFSET 0x00000001
|
|
#define CYFLD_SAR_OVERFLOW_MASK__SIZE 0x00000001
|
|
#define CYFLD_SAR_FW_COLLISION_MASK__OFFSET 0x00000002
|
|
#define CYFLD_SAR_FW_COLLISION_MASK__SIZE 0x00000001
|
|
#define CYFLD_SAR_DSI_COLLISION_MASK__OFFSET 0x00000003
|
|
#define CYFLD_SAR_DSI_COLLISION_MASK__SIZE 0x00000001
|
|
#define CYFLD_SAR_INJ_EOC_MASK__OFFSET 0x00000004
|
|
#define CYFLD_SAR_INJ_EOC_MASK__SIZE 0x00000001
|
|
#define CYFLD_SAR_INJ_SATURATE_MASK__OFFSET 0x00000005
|
|
#define CYFLD_SAR_INJ_SATURATE_MASK__SIZE 0x00000001
|
|
#define CYFLD_SAR_INJ_RANGE_MASK__OFFSET 0x00000006
|
|
#define CYFLD_SAR_INJ_RANGE_MASK__SIZE 0x00000001
|
|
#define CYFLD_SAR_INJ_COLLISION_MASK__OFFSET 0x00000007
|
|
#define CYFLD_SAR_INJ_COLLISION_MASK__SIZE 0x00000001
|
|
#define CYREG_SAR_INTR_MASKED 0x403a021c
|
|
#define CYFLD_SAR_EOS_MASKED__OFFSET 0x00000000
|
|
#define CYFLD_SAR_EOS_MASKED__SIZE 0x00000001
|
|
#define CYFLD_SAR_OVERFLOW_MASKED__OFFSET 0x00000001
|
|
#define CYFLD_SAR_OVERFLOW_MASKED__SIZE 0x00000001
|
|
#define CYFLD_SAR_FW_COLLISION_MASKED__OFFSET 0x00000002
|
|
#define CYFLD_SAR_FW_COLLISION_MASKED__SIZE 0x00000001
|
|
#define CYFLD_SAR_DSI_COLLISION_MASKED__OFFSET 0x00000003
|
|
#define CYFLD_SAR_DSI_COLLISION_MASKED__SIZE 0x00000001
|
|
#define CYFLD_SAR_INJ_EOC_MASKED__OFFSET 0x00000004
|
|
#define CYFLD_SAR_INJ_EOC_MASKED__SIZE 0x00000001
|
|
#define CYFLD_SAR_INJ_SATURATE_MASKED__OFFSET 0x00000005
|
|
#define CYFLD_SAR_INJ_SATURATE_MASKED__SIZE 0x00000001
|
|
#define CYFLD_SAR_INJ_RANGE_MASKED__OFFSET 0x00000006
|
|
#define CYFLD_SAR_INJ_RANGE_MASKED__SIZE 0x00000001
|
|
#define CYFLD_SAR_INJ_COLLISION_MASKED__OFFSET 0x00000007
|
|
#define CYFLD_SAR_INJ_COLLISION_MASKED__SIZE 0x00000001
|
|
#define CYREG_SAR_SATURATE_INTR 0x403a0220
|
|
#define CYFLD_SAR_SATURATE_INTR__OFFSET 0x00000000
|
|
#define CYFLD_SAR_SATURATE_INTR__SIZE 0x00000010
|
|
#define CYREG_SAR_SATURATE_INTR_SET 0x403a0224
|
|
#define CYFLD_SAR_SATURATE_SET__OFFSET 0x00000000
|
|
#define CYFLD_SAR_SATURATE_SET__SIZE 0x00000010
|
|
#define CYREG_SAR_SATURATE_INTR_MASK 0x403a0228
|
|
#define CYFLD_SAR_SATURATE_MASK__OFFSET 0x00000000
|
|
#define CYFLD_SAR_SATURATE_MASK__SIZE 0x00000010
|
|
#define CYREG_SAR_SATURATE_INTR_MASKED 0x403a022c
|
|
#define CYFLD_SAR_SATURATE_MASKED__OFFSET 0x00000000
|
|
#define CYFLD_SAR_SATURATE_MASKED__SIZE 0x00000010
|
|
#define CYREG_SAR_RANGE_INTR 0x403a0230
|
|
#define CYFLD_SAR_RANGE_INTR__OFFSET 0x00000000
|
|
#define CYFLD_SAR_RANGE_INTR__SIZE 0x00000010
|
|
#define CYREG_SAR_RANGE_INTR_SET 0x403a0234
|
|
#define CYFLD_SAR_RANGE_SET__OFFSET 0x00000000
|
|
#define CYFLD_SAR_RANGE_SET__SIZE 0x00000010
|
|
#define CYREG_SAR_RANGE_INTR_MASK 0x403a0238
|
|
#define CYFLD_SAR_RANGE_MASK__OFFSET 0x00000000
|
|
#define CYFLD_SAR_RANGE_MASK__SIZE 0x00000010
|
|
#define CYREG_SAR_RANGE_INTR_MASKED 0x403a023c
|
|
#define CYFLD_SAR_RANGE_MASKED__OFFSET 0x00000000
|
|
#define CYFLD_SAR_RANGE_MASKED__SIZE 0x00000010
|
|
#define CYREG_SAR_INTR_CAUSE 0x403a0240
|
|
#define CYFLD_SAR_EOS_MASKED_MIR__OFFSET 0x00000000
|
|
#define CYFLD_SAR_EOS_MASKED_MIR__SIZE 0x00000001
|
|
#define CYFLD_SAR_OVERFLOW_MASKED_MIR__OFFSET 0x00000001
|
|
#define CYFLD_SAR_OVERFLOW_MASKED_MIR__SIZE 0x00000001
|
|
#define CYFLD_SAR_FW_COLLISION_MASKED_MIR__OFFSET 0x00000002
|
|
#define CYFLD_SAR_FW_COLLISION_MASKED_MIR__SIZE 0x00000001
|
|
#define CYFLD_SAR_DSI_COLLISION_MASKED_MIR__OFFSET 0x00000003
|
|
#define CYFLD_SAR_DSI_COLLISION_MASKED_MIR__SIZE 0x00000001
|
|
#define CYFLD_SAR_INJ_EOC_MASKED_MIR__OFFSET 0x00000004
|
|
#define CYFLD_SAR_INJ_EOC_MASKED_MIR__SIZE 0x00000001
|
|
#define CYFLD_SAR_INJ_SATURATE_MASKED_MIR__OFFSET 0x00000005
|
|
#define CYFLD_SAR_INJ_SATURATE_MASKED_MIR__SIZE 0x00000001
|
|
#define CYFLD_SAR_INJ_RANGE_MASKED_MIR__OFFSET 0x00000006
|
|
#define CYFLD_SAR_INJ_RANGE_MASKED_MIR__SIZE 0x00000001
|
|
#define CYFLD_SAR_INJ_COLLISION_MASKED_MIR__OFFSET 0x00000007
|
|
#define CYFLD_SAR_INJ_COLLISION_MASKED_MIR__SIZE 0x00000001
|
|
#define CYFLD_SAR_SATURATE_MASKED_RED__OFFSET 0x0000001e
|
|
#define CYFLD_SAR_SATURATE_MASKED_RED__SIZE 0x00000001
|
|
#define CYFLD_SAR_RANGE_MASKED_RED__OFFSET 0x0000001f
|
|
#define CYFLD_SAR_RANGE_MASKED_RED__SIZE 0x00000001
|
|
#define CYREG_SAR_INJ_CHAN_CONFIG 0x403a0280
|
|
#define CYFLD_SAR_INJ_PIN_ADDR__OFFSET 0x00000000
|
|
#define CYFLD_SAR_INJ_PIN_ADDR__SIZE 0x00000003
|
|
#define CYFLD_SAR_INJ_PORT_ADDR__OFFSET 0x00000004
|
|
#define CYFLD_SAR_INJ_PORT_ADDR__SIZE 0x00000003
|
|
#define CYVAL_SAR_INJ_PORT_ADDR_SARMUX 0x00000000
|
|
#define CYVAL_SAR_INJ_PORT_ADDR_CTB0 0x00000001
|
|
#define CYVAL_SAR_INJ_PORT_ADDR_CTB1 0x00000002
|
|
#define CYVAL_SAR_INJ_PORT_ADDR_CTB2 0x00000003
|
|
#define CYVAL_SAR_INJ_PORT_ADDR_CTB3 0x00000004
|
|
#define CYVAL_SAR_INJ_PORT_ADDR_AROUTE_VIRT 0x00000006
|
|
#define CYVAL_SAR_INJ_PORT_ADDR_SARMUX_VIRT 0x00000007
|
|
#define CYFLD_SAR_INJ_DIFFERENTIAL_EN__OFFSET 0x00000008
|
|
#define CYFLD_SAR_INJ_DIFFERENTIAL_EN__SIZE 0x00000001
|
|
#define CYFLD_SAR_INJ_RESOLUTION__OFFSET 0x00000009
|
|
#define CYFLD_SAR_INJ_RESOLUTION__SIZE 0x00000001
|
|
#define CYVAL_SAR_INJ_RESOLUTION_12B 0x00000000
|
|
#define CYVAL_SAR_INJ_RESOLUTION_SUBRES 0x00000001
|
|
#define CYFLD_SAR_INJ_AVG_EN__OFFSET 0x0000000a
|
|
#define CYFLD_SAR_INJ_AVG_EN__SIZE 0x00000001
|
|
#define CYFLD_SAR_INJ_SAMPLE_TIME_SEL__OFFSET 0x0000000c
|
|
#define CYFLD_SAR_INJ_SAMPLE_TIME_SEL__SIZE 0x00000002
|
|
#define CYFLD_SAR_INJ_TAILGATING__OFFSET 0x0000001e
|
|
#define CYFLD_SAR_INJ_TAILGATING__SIZE 0x00000001
|
|
#define CYFLD_SAR_INJ_START_EN__OFFSET 0x0000001f
|
|
#define CYFLD_SAR_INJ_START_EN__SIZE 0x00000001
|
|
#define CYREG_SAR_INJ_RESULT 0x403a0290
|
|
#define CYFLD_SAR_INJ_RESULT__OFFSET 0x00000000
|
|
#define CYFLD_SAR_INJ_RESULT__SIZE 0x00000010
|
|
#define CYFLD_SAR_INJ_COLLISION_INTR_MIR__OFFSET 0x0000001c
|
|
#define CYFLD_SAR_INJ_COLLISION_INTR_MIR__SIZE 0x00000001
|
|
#define CYFLD_SAR_INJ_SATURATE_INTR_MIR__OFFSET 0x0000001d
|
|
#define CYFLD_SAR_INJ_SATURATE_INTR_MIR__SIZE 0x00000001
|
|
#define CYFLD_SAR_INJ_RANGE_INTR_MIR__OFFSET 0x0000001e
|
|
#define CYFLD_SAR_INJ_RANGE_INTR_MIR__SIZE 0x00000001
|
|
#define CYFLD_SAR_INJ_EOC_INTR_MIR__OFFSET 0x0000001f
|
|
#define CYFLD_SAR_INJ_EOC_INTR_MIR__SIZE 0x00000001
|
|
#define CYREG_SAR_MUX_SWITCH0 0x403a0300
|
|
#define CYFLD_SAR_MUX_FW_P0_VPLUS__OFFSET 0x00000000
|
|
#define CYFLD_SAR_MUX_FW_P0_VPLUS__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_FW_P1_VPLUS__OFFSET 0x00000001
|
|
#define CYFLD_SAR_MUX_FW_P1_VPLUS__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_FW_P2_VPLUS__OFFSET 0x00000002
|
|
#define CYFLD_SAR_MUX_FW_P2_VPLUS__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_FW_P3_VPLUS__OFFSET 0x00000003
|
|
#define CYFLD_SAR_MUX_FW_P3_VPLUS__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_FW_P4_VPLUS__OFFSET 0x00000004
|
|
#define CYFLD_SAR_MUX_FW_P4_VPLUS__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_FW_P5_VPLUS__OFFSET 0x00000005
|
|
#define CYFLD_SAR_MUX_FW_P5_VPLUS__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_FW_P6_VPLUS__OFFSET 0x00000006
|
|
#define CYFLD_SAR_MUX_FW_P6_VPLUS__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_FW_P7_VPLUS__OFFSET 0x00000007
|
|
#define CYFLD_SAR_MUX_FW_P7_VPLUS__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_FW_P0_VMINUS__OFFSET 0x00000008
|
|
#define CYFLD_SAR_MUX_FW_P0_VMINUS__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_FW_P1_VMINUS__OFFSET 0x00000009
|
|
#define CYFLD_SAR_MUX_FW_P1_VMINUS__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_FW_P2_VMINUS__OFFSET 0x0000000a
|
|
#define CYFLD_SAR_MUX_FW_P2_VMINUS__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_FW_P3_VMINUS__OFFSET 0x0000000b
|
|
#define CYFLD_SAR_MUX_FW_P3_VMINUS__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_FW_P4_VMINUS__OFFSET 0x0000000c
|
|
#define CYFLD_SAR_MUX_FW_P4_VMINUS__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_FW_P5_VMINUS__OFFSET 0x0000000d
|
|
#define CYFLD_SAR_MUX_FW_P5_VMINUS__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_FW_P6_VMINUS__OFFSET 0x0000000e
|
|
#define CYFLD_SAR_MUX_FW_P6_VMINUS__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_FW_P7_VMINUS__OFFSET 0x0000000f
|
|
#define CYFLD_SAR_MUX_FW_P7_VMINUS__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_FW_VSSA_VMINUS__OFFSET 0x00000010
|
|
#define CYFLD_SAR_MUX_FW_VSSA_VMINUS__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_FW_TEMP_VPLUS__OFFSET 0x00000011
|
|
#define CYFLD_SAR_MUX_FW_TEMP_VPLUS__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__OFFSET 0x00000012
|
|
#define CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__OFFSET 0x00000013
|
|
#define CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__OFFSET 0x00000014
|
|
#define CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__OFFSET 0x00000015
|
|
#define CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__OFFSET 0x00000016
|
|
#define CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__OFFSET 0x00000017
|
|
#define CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__OFFSET 0x00000018
|
|
#define CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__OFFSET 0x00000019
|
|
#define CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_FW_P4_COREIO0__OFFSET 0x0000001a
|
|
#define CYFLD_SAR_MUX_FW_P4_COREIO0__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_FW_P5_COREIO1__OFFSET 0x0000001b
|
|
#define CYFLD_SAR_MUX_FW_P5_COREIO1__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_FW_P6_COREIO2__OFFSET 0x0000001c
|
|
#define CYFLD_SAR_MUX_FW_P6_COREIO2__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_FW_P7_COREIO3__OFFSET 0x0000001d
|
|
#define CYFLD_SAR_MUX_FW_P7_COREIO3__SIZE 0x00000001
|
|
#define CYREG_SAR_MUX_SWITCH_CLEAR0 0x403a0304
|
|
#define CYREG_SAR_MUX_SWITCH1 0x403a0308
|
|
#define CYFLD_SAR_MUX_FW_P4_DFT_INP__OFFSET 0x00000000
|
|
#define CYFLD_SAR_MUX_FW_P4_DFT_INP__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_FW_P5_DFT_INM__OFFSET 0x00000001
|
|
#define CYFLD_SAR_MUX_FW_P5_DFT_INM__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__OFFSET 0x00000002
|
|
#define CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__OFFSET 0x00000003
|
|
#define CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__SIZE 0x00000001
|
|
#define CYREG_SAR_MUX_SWITCH_CLEAR1 0x403a030c
|
|
#define CYREG_SAR_MUX_SWITCH_HW_CTRL 0x403a0340
|
|
#define CYFLD_SAR_MUX_HW_CTRL_P0__OFFSET 0x00000000
|
|
#define CYFLD_SAR_MUX_HW_CTRL_P0__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_HW_CTRL_P1__OFFSET 0x00000001
|
|
#define CYFLD_SAR_MUX_HW_CTRL_P1__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_HW_CTRL_P2__OFFSET 0x00000002
|
|
#define CYFLD_SAR_MUX_HW_CTRL_P2__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_HW_CTRL_P3__OFFSET 0x00000003
|
|
#define CYFLD_SAR_MUX_HW_CTRL_P3__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_HW_CTRL_P4__OFFSET 0x00000004
|
|
#define CYFLD_SAR_MUX_HW_CTRL_P4__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_HW_CTRL_P5__OFFSET 0x00000005
|
|
#define CYFLD_SAR_MUX_HW_CTRL_P5__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_HW_CTRL_P6__OFFSET 0x00000006
|
|
#define CYFLD_SAR_MUX_HW_CTRL_P6__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_HW_CTRL_P7__OFFSET 0x00000007
|
|
#define CYFLD_SAR_MUX_HW_CTRL_P7__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_HW_CTRL_VSSA__OFFSET 0x00000010
|
|
#define CYFLD_SAR_MUX_HW_CTRL_VSSA__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_HW_CTRL_TEMP__OFFSET 0x00000011
|
|
#define CYFLD_SAR_MUX_HW_CTRL_TEMP__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__OFFSET 0x00000012
|
|
#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__OFFSET 0x00000013
|
|
#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_HW_CTRL_SARBUS0__OFFSET 0x00000016
|
|
#define CYFLD_SAR_MUX_HW_CTRL_SARBUS0__SIZE 0x00000001
|
|
#define CYFLD_SAR_MUX_HW_CTRL_SARBUS1__OFFSET 0x00000017
|
|
#define CYFLD_SAR_MUX_HW_CTRL_SARBUS1__SIZE 0x00000001
|
|
#define CYREG_SAR_MUX_SWITCH_STATUS 0x403a0348
|
|
#define CYREG_SAR_PUMP_CTRL 0x403a0380
|
|
#define CYFLD_SAR_CLOCK_SEL__OFFSET 0x00000000
|
|
#define CYFLD_SAR_CLOCK_SEL__SIZE 0x00000001
|
|
#define CYREG_SAR_ANA_TRIM 0x403a0f00
|
|
#define CYFLD_SAR_CAP_TRIM__OFFSET 0x00000000
|
|
#define CYFLD_SAR_CAP_TRIM__SIZE 0x00000003
|
|
#define CYFLD_SAR_TRIMUNIT__OFFSET 0x00000003
|
|
#define CYFLD_SAR_TRIMUNIT__SIZE 0x00000001
|
|
#define CYREG_SAR_WOUNDING 0x403a0f04
|
|
#define CYFLD_SAR_WOUND_RESOLUTION__OFFSET 0x00000000
|
|
#define CYFLD_SAR_WOUND_RESOLUTION__SIZE 0x00000002
|
|
#define CYVAL_SAR_WOUND_RESOLUTION_12BIT 0x00000000
|
|
#define CYVAL_SAR_WOUND_RESOLUTION_10BIT 0x00000001
|
|
#define CYVAL_SAR_WOUND_RESOLUTION_8BIT 0x00000002
|
|
#define CYVAL_SAR_WOUND_RESOLUTION_8BIT_TOO 0x00000003
|
|
#define CYDEV_PASS_BASE 0x403f0000
|
|
#define CYDEV_PASS_SIZE 0x00010000
|
|
#define CYREG_PASS_INTR_CAUSE 0x403f0000
|
|
#define CYFLD_PASS_CTB0_INT__OFFSET 0x00000000
|
|
#define CYFLD_PASS_CTB0_INT__SIZE 0x00000001
|
|
#define CYFLD_PASS_CTB1_INT__OFFSET 0x00000001
|
|
#define CYFLD_PASS_CTB1_INT__SIZE 0x00000001
|
|
#define CYREG_PASS_DFT_CTRL 0x403f0030
|
|
#define CYFLD_PASS_DSAB_ADFT_RES_EN__OFFSET 0x00000000
|
|
#define CYFLD_PASS_DSAB_ADFT_RES_EN__SIZE 0x00000001
|
|
#define CYDEV_PASS_DSAB_BASE 0x403f0e00
|
|
#define CYDEV_PASS_DSAB_SIZE 0x00000100
|
|
#define CYREG_PASS_DSAB_DSAB_CTRL 0x403f0e00
|
|
#define CYFLD_PASS_DSAB_CURRENT_SEL__OFFSET 0x00000000
|
|
#define CYFLD_PASS_DSAB_CURRENT_SEL__SIZE 0x00000006
|
|
#define CYFLD_PASS_DSAB_SEL_OUT__OFFSET 0x00000008
|
|
#define CYFLD_PASS_DSAB_SEL_OUT__SIZE 0x00000004
|
|
#define CYFLD_PASS_DSAB_ENABLED__OFFSET 0x0000001f
|
|
#define CYFLD_PASS_DSAB_ENABLED__SIZE 0x00000001
|
|
#define CYREG_PASS_DSAB_DSAB_DFT 0x403f0e04
|
|
#define CYFLD_PASS_DSAB_EN_DFT__OFFSET 0x00000000
|
|
#define CYFLD_PASS_DSAB_EN_DFT__SIZE 0x00000004
|
|
#define CYREG_PASS_DSAB_TRIM 0x403f0f00
|
|
#define CYFLD_PASS_IBIAS_TRIM__OFFSET 0x00000000
|
|
#define CYFLD_PASS_IBIAS_TRIM__SIZE 0x00000004
|
|
#define CYDEV_CM0_BASE 0xe0000000
|
|
#define CYDEV_CM0_SIZE 0x00100000
|
|
#define CYREG_CM0_DWT_PID4 0xe0001fd0
|
|
#define CYFLD_CM0_VALUE__OFFSET 0x00000000
|
|
#define CYFLD_CM0_VALUE__SIZE 0x00000020
|
|
#define CYREG_CM0_DWT_PID0 0xe0001fe0
|
|
#define CYREG_CM0_DWT_PID1 0xe0001fe4
|
|
#define CYREG_CM0_DWT_PID2 0xe0001fe8
|
|
#define CYREG_CM0_DWT_PID3 0xe0001fec
|
|
#define CYREG_CM0_DWT_CID0 0xe0001ff0
|
|
#define CYREG_CM0_DWT_CID1 0xe0001ff4
|
|
#define CYREG_CM0_DWT_CID2 0xe0001ff8
|
|
#define CYREG_CM0_DWT_CID3 0xe0001ffc
|
|
#define CYREG_CM0_BP_PID4 0xe0002fd0
|
|
#define CYREG_CM0_BP_PID0 0xe0002fe0
|
|
#define CYREG_CM0_BP_PID1 0xe0002fe4
|
|
#define CYREG_CM0_BP_PID2 0xe0002fe8
|
|
#define CYREG_CM0_BP_PID3 0xe0002fec
|
|
#define CYREG_CM0_BP_CID0 0xe0002ff0
|
|
#define CYREG_CM0_BP_CID1 0xe0002ff4
|
|
#define CYREG_CM0_BP_CID2 0xe0002ff8
|
|
#define CYREG_CM0_BP_CID3 0xe0002ffc
|
|
#define CYREG_CM0_SYST_CSR 0xe000e010
|
|
#define CYFLD_CM0_ENABLE__OFFSET 0x00000000
|
|
#define CYFLD_CM0_ENABLE__SIZE 0x00000001
|
|
#define CYFLD_CM0_TICKINT__OFFSET 0x00000001
|
|
#define CYFLD_CM0_TICKINT__SIZE 0x00000001
|
|
#define CYFLD_CM0_CLKSOURCE__OFFSET 0x00000002
|
|
#define CYFLD_CM0_CLKSOURCE__SIZE 0x00000001
|
|
#define CYFLD_CM0_COUNTFLAG__OFFSET 0x00000010
|
|
#define CYFLD_CM0_COUNTFLAG__SIZE 0x00000001
|
|
#define CYREG_CM0_SYST_RVR 0xe000e014
|
|
#define CYFLD_CM0_RELOAD__OFFSET 0x00000000
|
|
#define CYFLD_CM0_RELOAD__SIZE 0x00000018
|
|
#define CYREG_CM0_SYST_CVR 0xe000e018
|
|
#define CYFLD_CM0_CURRENT__OFFSET 0x00000000
|
|
#define CYFLD_CM0_CURRENT__SIZE 0x00000018
|
|
#define CYREG_CM0_SYST_CALIB 0xe000e01c
|
|
#define CYFLD_CM0_TENMS__OFFSET 0x00000000
|
|
#define CYFLD_CM0_TENMS__SIZE 0x00000018
|
|
#define CYFLD_CM0_SKEW__OFFSET 0x0000001e
|
|
#define CYFLD_CM0_SKEW__SIZE 0x00000001
|
|
#define CYFLD_CM0_NOREF__OFFSET 0x0000001f
|
|
#define CYFLD_CM0_NOREF__SIZE 0x00000001
|
|
#define CYREG_CM0_ISER 0xe000e100
|
|
#define CYFLD_CM0_SETENA__OFFSET 0x00000000
|
|
#define CYFLD_CM0_SETENA__SIZE 0x00000020
|
|
#define CYREG_CM0_ICER 0xe000e180
|
|
#define CYFLD_CM0_CLRENA__OFFSET 0x00000000
|
|
#define CYFLD_CM0_CLRENA__SIZE 0x00000020
|
|
#define CYREG_CM0_ISPR 0xe000e200
|
|
#define CYFLD_CM0_SETPEND__OFFSET 0x00000000
|
|
#define CYFLD_CM0_SETPEND__SIZE 0x00000020
|
|
#define CYREG_CM0_ICPR 0xe000e280
|
|
#define CYFLD_CM0_CLRPEND__OFFSET 0x00000000
|
|
#define CYFLD_CM0_CLRPEND__SIZE 0x00000020
|
|
#define CYREG_CM0_IPR0 0xe000e400
|
|
#define CYFLD_CM0_PRI_N0__OFFSET 0x00000006
|
|
#define CYFLD_CM0_PRI_N0__SIZE 0x00000002
|
|
#define CYFLD_CM0_PRI_N1__OFFSET 0x0000000e
|
|
#define CYFLD_CM0_PRI_N1__SIZE 0x00000002
|
|
#define CYFLD_CM0_PRI_N2__OFFSET 0x00000016
|
|
#define CYFLD_CM0_PRI_N2__SIZE 0x00000002
|
|
#define CYFLD_CM0_PRI_N3__OFFSET 0x0000001e
|
|
#define CYFLD_CM0_PRI_N3__SIZE 0x00000002
|
|
#define CYREG_CM0_IPR1 0xe000e404
|
|
#define CYREG_CM0_IPR2 0xe000e408
|
|
#define CYREG_CM0_IPR3 0xe000e40c
|
|
#define CYREG_CM0_IPR4 0xe000e410
|
|
#define CYREG_CM0_IPR5 0xe000e414
|
|
#define CYREG_CM0_IPR6 0xe000e418
|
|
#define CYREG_CM0_IPR7 0xe000e41c
|
|
#define CYREG_CM0_CPUID 0xe000ed00
|
|
#define CYFLD_CM0_REVISION__OFFSET 0x00000000
|
|
#define CYFLD_CM0_REVISION__SIZE 0x00000004
|
|
#define CYFLD_CM0_PARTNO__OFFSET 0x00000004
|
|
#define CYFLD_CM0_PARTNO__SIZE 0x0000000c
|
|
#define CYFLD_CM0_CONSTANT__OFFSET 0x00000010
|
|
#define CYFLD_CM0_CONSTANT__SIZE 0x00000004
|
|
#define CYFLD_CM0_VARIANT__OFFSET 0x00000014
|
|
#define CYFLD_CM0_VARIANT__SIZE 0x00000004
|
|
#define CYFLD_CM0_IMPLEMENTER__OFFSET 0x00000018
|
|
#define CYFLD_CM0_IMPLEMENTER__SIZE 0x00000008
|
|
#define CYREG_CM0_ICSR 0xe000ed04
|
|
#define CYFLD_CM0_VECTACTIVE__OFFSET 0x00000000
|
|
#define CYFLD_CM0_VECTACTIVE__SIZE 0x00000009
|
|
#define CYFLD_CM0_VECTPENDING__OFFSET 0x0000000c
|
|
#define CYFLD_CM0_VECTPENDING__SIZE 0x00000009
|
|
#define CYFLD_CM0_ISRPENDING__OFFSET 0x00000016
|
|
#define CYFLD_CM0_ISRPENDING__SIZE 0x00000001
|
|
#define CYFLD_CM0_ISRPREEMPT__OFFSET 0x00000017
|
|
#define CYFLD_CM0_ISRPREEMPT__SIZE 0x00000001
|
|
#define CYFLD_CM0_PENDSTCLR__OFFSET 0x00000019
|
|
#define CYFLD_CM0_PENDSTCLR__SIZE 0x00000001
|
|
#define CYFLD_CM0_PENDSTSETb__OFFSET 0x0000001a
|
|
#define CYFLD_CM0_PENDSTSETb__SIZE 0x00000001
|
|
#define CYFLD_CM0_PENDSVCLR__OFFSET 0x0000001b
|
|
#define CYFLD_CM0_PENDSVCLR__SIZE 0x00000001
|
|
#define CYFLD_CM0_PENDSVSET__OFFSET 0x0000001c
|
|
#define CYFLD_CM0_PENDSVSET__SIZE 0x00000001
|
|
#define CYFLD_CM0_NMIPENDSET__OFFSET 0x0000001f
|
|
#define CYFLD_CM0_NMIPENDSET__SIZE 0x00000001
|
|
#define CYREG_CM0_AIRCR 0xe000ed0c
|
|
#define CYFLD_CM0_VECTCLRACTIVE__OFFSET 0x00000001
|
|
#define CYFLD_CM0_VECTCLRACTIVE__SIZE 0x00000001
|
|
#define CYFLD_CM0_SYSRESETREQ__OFFSET 0x00000002
|
|
#define CYFLD_CM0_SYSRESETREQ__SIZE 0x00000001
|
|
#define CYFLD_CM0_ENDIANNESS__OFFSET 0x0000000f
|
|
#define CYFLD_CM0_ENDIANNESS__SIZE 0x00000001
|
|
#define CYFLD_CM0_VECTKEY__OFFSET 0x00000010
|
|
#define CYFLD_CM0_VECTKEY__SIZE 0x00000010
|
|
#define CYREG_CM0_SCR 0xe000ed10
|
|
#define CYFLD_CM0_SLEEPONEXIT__OFFSET 0x00000001
|
|
#define CYFLD_CM0_SLEEPONEXIT__SIZE 0x00000001
|
|
#define CYFLD_CM0_SLEEPDEEP__OFFSET 0x00000002
|
|
#define CYFLD_CM0_SLEEPDEEP__SIZE 0x00000001
|
|
#define CYFLD_CM0_SEVONPEND__OFFSET 0x00000004
|
|
#define CYFLD_CM0_SEVONPEND__SIZE 0x00000001
|
|
#define CYREG_CM0_CCR 0xe000ed14
|
|
#define CYFLD_CM0_UNALIGN_TRP__OFFSET 0x00000003
|
|
#define CYFLD_CM0_UNALIGN_TRP__SIZE 0x00000001
|
|
#define CYFLD_CM0_STKALIGN__OFFSET 0x00000009
|
|
#define CYFLD_CM0_STKALIGN__SIZE 0x00000001
|
|
#define CYREG_CM0_SHPR2 0xe000ed1c
|
|
#define CYFLD_CM0_PRI_11__OFFSET 0x0000001e
|
|
#define CYFLD_CM0_PRI_11__SIZE 0x00000002
|
|
#define CYREG_CM0_SHPR3 0xe000ed20
|
|
#define CYFLD_CM0_PRI_14__OFFSET 0x00000016
|
|
#define CYFLD_CM0_PRI_14__SIZE 0x00000002
|
|
#define CYFLD_CM0_PRI_15__OFFSET 0x0000001e
|
|
#define CYFLD_CM0_PRI_15__SIZE 0x00000002
|
|
#define CYREG_CM0_SHCSR 0xe000ed24
|
|
#define CYFLD_CM0_SVCALLPENDED__OFFSET 0x0000000f
|
|
#define CYFLD_CM0_SVCALLPENDED__SIZE 0x00000001
|
|
#define CYREG_CM0_SCS_PID4 0xe000efd0
|
|
#define CYREG_CM0_SCS_PID0 0xe000efe0
|
|
#define CYREG_CM0_SCS_PID1 0xe000efe4
|
|
#define CYREG_CM0_SCS_PID2 0xe000efe8
|
|
#define CYREG_CM0_SCS_PID3 0xe000efec
|
|
#define CYREG_CM0_SCS_CID0 0xe000eff0
|
|
#define CYREG_CM0_SCS_CID1 0xe000eff4
|
|
#define CYREG_CM0_SCS_CID2 0xe000eff8
|
|
#define CYREG_CM0_SCS_CID3 0xe000effc
|
|
#define CYREG_CM0_ROM_SCS 0xe00ff000
|
|
#define CYREG_CM0_ROM_DWT 0xe00ff004
|
|
#define CYREG_CM0_ROM_BPU 0xe00ff008
|
|
#define CYREG_CM0_ROM_END 0xe00ff00c
|
|
#define CYREG_CM0_ROM_CSMT 0xe00fffcc
|
|
#define CYREG_CM0_ROM_PID4 0xe00fffd0
|
|
#define CYREG_CM0_ROM_PID0 0xe00fffe0
|
|
#define CYREG_CM0_ROM_PID1 0xe00fffe4
|
|
#define CYREG_CM0_ROM_PID2 0xe00fffe8
|
|
#define CYREG_CM0_ROM_PID3 0xe00fffec
|
|
#define CYREG_CM0_ROM_CID0 0xe00ffff0
|
|
#define CYREG_CM0_ROM_CID1 0xe00ffff4
|
|
#define CYREG_CM0_ROM_CID2 0xe00ffff8
|
|
#define CYREG_CM0_ROM_CID3 0xe00ffffc
|
|
#define CYDEV_ROMTABLE_BASE 0xf0000000
|
|
#define CYDEV_ROMTABLE_SIZE 0x00001000
|
|
#define CYREG_ROMTABLE_ADDR 0xf0000000
|
|
#define CYFLD_ROMTABLE_PRESENT__OFFSET 0x00000000
|
|
#define CYFLD_ROMTABLE_PRESENT__SIZE 0x00000001
|
|
#define CYFLD_ROMTABLE_FORMAT_32BIT__OFFSET 0x00000001
|
|
#define CYFLD_ROMTABLE_FORMAT_32BIT__SIZE 0x00000001
|
|
#define CYFLD_ROMTABLE_ADDR_OFFSET__OFFSET 0x0000000c
|
|
#define CYFLD_ROMTABLE_ADDR_OFFSET__SIZE 0x00000014
|
|
#define CYREG_ROMTABLE_DID 0xf0000fcc
|
|
#define CYFLD_ROMTABLE_VALUE__OFFSET 0x00000000
|
|
#define CYFLD_ROMTABLE_VALUE__SIZE 0x00000020
|
|
#define CYREG_ROMTABLE_PID4 0xf0000fd0
|
|
#define CYFLD_ROMTABLE_JEP_CONTINUATION__OFFSET 0x00000000
|
|
#define CYFLD_ROMTABLE_JEP_CONTINUATION__SIZE 0x00000004
|
|
#define CYFLD_ROMTABLE_COUNT__OFFSET 0x00000004
|
|
#define CYFLD_ROMTABLE_COUNT__SIZE 0x00000004
|
|
#define CYREG_ROMTABLE_PID5 0xf0000fd4
|
|
#define CYREG_ROMTABLE_PID6 0xf0000fd8
|
|
#define CYREG_ROMTABLE_PID7 0xf0000fdc
|
|
#define CYREG_ROMTABLE_PID0 0xf0000fe0
|
|
#define CYFLD_ROMTABLE_PN_MIN__OFFSET 0x00000000
|
|
#define CYFLD_ROMTABLE_PN_MIN__SIZE 0x00000008
|
|
#define CYREG_ROMTABLE_PID1 0xf0000fe4
|
|
#define CYFLD_ROMTABLE_PN_MAJ__OFFSET 0x00000000
|
|
#define CYFLD_ROMTABLE_PN_MAJ__SIZE 0x00000004
|
|
#define CYFLD_ROMTABLE_JEPID_MIN__OFFSET 0x00000004
|
|
#define CYFLD_ROMTABLE_JEPID_MIN__SIZE 0x00000004
|
|
#define CYREG_ROMTABLE_PID2 0xf0000fe8
|
|
#define CYFLD_ROMTABLE_JEPID_MAJ__OFFSET 0x00000000
|
|
#define CYFLD_ROMTABLE_JEPID_MAJ__SIZE 0x00000003
|
|
#define CYFLD_ROMTABLE_REV__OFFSET 0x00000004
|
|
#define CYFLD_ROMTABLE_REV__SIZE 0x00000004
|
|
#define CYREG_ROMTABLE_PID3 0xf0000fec
|
|
#define CYFLD_ROMTABLE_CM__OFFSET 0x00000000
|
|
#define CYFLD_ROMTABLE_CM__SIZE 0x00000004
|
|
#define CYFLD_ROMTABLE_REV_AND__OFFSET 0x00000004
|
|
#define CYFLD_ROMTABLE_REV_AND__SIZE 0x00000004
|
|
#define CYREG_ROMTABLE_CID0 0xf0000ff0
|
|
#define CYREG_ROMTABLE_CID1 0xf0000ff4
|
|
#define CYREG_ROMTABLE_CID2 0xf0000ff8
|
|
#define CYREG_ROMTABLE_CID3 0xf0000ffc
|
|
#define CYDEV_FLS_SECTOR_SIZE 0x00010000
|
|
#define CYDEV_FLS_ROW_SIZE 0x00000080
|
|
#define CYREG_SFLASH_PROT_ROW00 CYREG_SFLASH_PROT_ROW0
|
|
#define CYREG_SFLASH_PROT_ROW01 CYREG_SFLASH_PROT_ROW1
|
|
#define CYREG_SFLASH_PROT_ROW02 CYREG_SFLASH_PROT_ROW2
|
|
#define CYREG_SFLASH_PROT_ROW03 CYREG_SFLASH_PROT_ROW3
|
|
#define CYREG_SFLASH_PROT_ROW04 CYREG_SFLASH_PROT_ROW4
|
|
#define CYREG_SFLASH_PROT_ROW05 CYREG_SFLASH_PROT_ROW5
|
|
#define CYREG_SFLASH_PROT_ROW06 CYREG_SFLASH_PROT_ROW6
|
|
#define CYREG_SFLASH_PROT_ROW07 CYREG_SFLASH_PROT_ROW7
|
|
#define CYREG_SFLASH_PROT_ROW08 CYREG_SFLASH_PROT_ROW8
|
|
#define CYREG_SFLASH_PROT_ROW09 CYREG_SFLASH_PROT_ROW9
|
|
#define CYREG_SFLASH_AV_PAIRS_8B000 CYREG_SFLASH_AV_PAIRS_8B0
|
|
#define CYREG_SFLASH_AV_PAIRS_8B001 CYREG_SFLASH_AV_PAIRS_8B1
|
|
#define CYREG_SFLASH_AV_PAIRS_8B002 CYREG_SFLASH_AV_PAIRS_8B2
|
|
#define CYREG_SFLASH_AV_PAIRS_8B003 CYREG_SFLASH_AV_PAIRS_8B3
|
|
#define CYREG_SFLASH_AV_PAIRS_8B004 CYREG_SFLASH_AV_PAIRS_8B4
|
|
#define CYREG_SFLASH_AV_PAIRS_8B005 CYREG_SFLASH_AV_PAIRS_8B5
|
|
#define CYREG_SFLASH_AV_PAIRS_8B006 CYREG_SFLASH_AV_PAIRS_8B6
|
|
#define CYREG_SFLASH_AV_PAIRS_8B007 CYREG_SFLASH_AV_PAIRS_8B7
|
|
#define CYREG_SFLASH_AV_PAIRS_8B008 CYREG_SFLASH_AV_PAIRS_8B8
|
|
#define CYREG_SFLASH_AV_PAIRS_8B009 CYREG_SFLASH_AV_PAIRS_8B9
|
|
#define CYREG_SFLASH_AV_PAIRS_8B010 CYREG_SFLASH_AV_PAIRS_8B10
|
|
#define CYREG_SFLASH_AV_PAIRS_8B011 CYREG_SFLASH_AV_PAIRS_8B11
|
|
#define CYREG_SFLASH_AV_PAIRS_8B012 CYREG_SFLASH_AV_PAIRS_8B12
|
|
#define CYREG_SFLASH_AV_PAIRS_8B013 CYREG_SFLASH_AV_PAIRS_8B13
|
|
#define CYREG_SFLASH_AV_PAIRS_8B014 CYREG_SFLASH_AV_PAIRS_8B14
|
|
#define CYREG_SFLASH_AV_PAIRS_8B015 CYREG_SFLASH_AV_PAIRS_8B15
|
|
#define CYREG_SFLASH_AV_PAIRS_8B016 CYREG_SFLASH_AV_PAIRS_8B16
|
|
#define CYREG_SFLASH_AV_PAIRS_8B017 CYREG_SFLASH_AV_PAIRS_8B17
|
|
#define CYREG_SFLASH_AV_PAIRS_8B018 CYREG_SFLASH_AV_PAIRS_8B18
|
|
#define CYREG_SFLASH_AV_PAIRS_8B019 CYREG_SFLASH_AV_PAIRS_8B19
|
|
#define CYREG_SFLASH_AV_PAIRS_8B020 CYREG_SFLASH_AV_PAIRS_8B20
|
|
#define CYREG_SFLASH_AV_PAIRS_8B021 CYREG_SFLASH_AV_PAIRS_8B21
|
|
#define CYREG_SFLASH_AV_PAIRS_8B022 CYREG_SFLASH_AV_PAIRS_8B22
|
|
#define CYREG_SFLASH_AV_PAIRS_8B023 CYREG_SFLASH_AV_PAIRS_8B23
|
|
#define CYREG_SFLASH_AV_PAIRS_8B024 CYREG_SFLASH_AV_PAIRS_8B24
|
|
#define CYREG_SFLASH_AV_PAIRS_8B025 CYREG_SFLASH_AV_PAIRS_8B25
|
|
#define CYREG_SFLASH_AV_PAIRS_8B026 CYREG_SFLASH_AV_PAIRS_8B26
|
|
#define CYREG_SFLASH_AV_PAIRS_8B027 CYREG_SFLASH_AV_PAIRS_8B27
|
|
#define CYREG_SFLASH_AV_PAIRS_8B028 CYREG_SFLASH_AV_PAIRS_8B28
|
|
#define CYREG_SFLASH_AV_PAIRS_8B029 CYREG_SFLASH_AV_PAIRS_8B29
|
|
#define CYREG_SFLASH_AV_PAIRS_8B030 CYREG_SFLASH_AV_PAIRS_8B30
|
|
#define CYREG_SFLASH_AV_PAIRS_8B031 CYREG_SFLASH_AV_PAIRS_8B31
|
|
#define CYREG_SFLASH_AV_PAIRS_8B032 CYREG_SFLASH_AV_PAIRS_8B32
|
|
#define CYREG_SFLASH_AV_PAIRS_8B033 CYREG_SFLASH_AV_PAIRS_8B33
|
|
#define CYREG_SFLASH_AV_PAIRS_8B034 CYREG_SFLASH_AV_PAIRS_8B34
|
|
#define CYREG_SFLASH_AV_PAIRS_8B035 CYREG_SFLASH_AV_PAIRS_8B35
|
|
#define CYREG_SFLASH_AV_PAIRS_8B036 CYREG_SFLASH_AV_PAIRS_8B36
|
|
#define CYREG_SFLASH_AV_PAIRS_8B037 CYREG_SFLASH_AV_PAIRS_8B37
|
|
#define CYREG_SFLASH_AV_PAIRS_8B038 CYREG_SFLASH_AV_PAIRS_8B38
|
|
#define CYREG_SFLASH_AV_PAIRS_8B039 CYREG_SFLASH_AV_PAIRS_8B39
|
|
#define CYREG_SFLASH_AV_PAIRS_8B040 CYREG_SFLASH_AV_PAIRS_8B40
|
|
#define CYREG_SFLASH_AV_PAIRS_8B041 CYREG_SFLASH_AV_PAIRS_8B41
|
|
#define CYREG_SFLASH_AV_PAIRS_8B042 CYREG_SFLASH_AV_PAIRS_8B42
|
|
#define CYREG_SFLASH_AV_PAIRS_8B043 CYREG_SFLASH_AV_PAIRS_8B43
|
|
#define CYREG_SFLASH_AV_PAIRS_8B044 CYREG_SFLASH_AV_PAIRS_8B44
|
|
#define CYREG_SFLASH_AV_PAIRS_8B045 CYREG_SFLASH_AV_PAIRS_8B45
|
|
#define CYREG_SFLASH_AV_PAIRS_8B046 CYREG_SFLASH_AV_PAIRS_8B46
|
|
#define CYREG_SFLASH_AV_PAIRS_8B047 CYREG_SFLASH_AV_PAIRS_8B47
|
|
#define CYREG_SFLASH_AV_PAIRS_8B048 CYREG_SFLASH_AV_PAIRS_8B48
|
|
#define CYREG_SFLASH_AV_PAIRS_8B049 CYREG_SFLASH_AV_PAIRS_8B49
|
|
#define CYREG_SFLASH_AV_PAIRS_8B050 CYREG_SFLASH_AV_PAIRS_8B50
|
|
#define CYREG_SFLASH_AV_PAIRS_8B051 CYREG_SFLASH_AV_PAIRS_8B51
|
|
#define CYREG_SFLASH_AV_PAIRS_8B052 CYREG_SFLASH_AV_PAIRS_8B52
|
|
#define CYREG_SFLASH_AV_PAIRS_8B053 CYREG_SFLASH_AV_PAIRS_8B53
|
|
#define CYREG_SFLASH_AV_PAIRS_8B054 CYREG_SFLASH_AV_PAIRS_8B54
|
|
#define CYREG_SFLASH_AV_PAIRS_8B055 CYREG_SFLASH_AV_PAIRS_8B55
|
|
#define CYREG_SFLASH_AV_PAIRS_8B056 CYREG_SFLASH_AV_PAIRS_8B56
|
|
#define CYREG_SFLASH_AV_PAIRS_8B057 CYREG_SFLASH_AV_PAIRS_8B57
|
|
#define CYREG_SFLASH_AV_PAIRS_8B058 CYREG_SFLASH_AV_PAIRS_8B58
|
|
#define CYREG_SFLASH_AV_PAIRS_8B059 CYREG_SFLASH_AV_PAIRS_8B59
|
|
#define CYREG_SFLASH_AV_PAIRS_8B060 CYREG_SFLASH_AV_PAIRS_8B60
|
|
#define CYREG_SFLASH_AV_PAIRS_8B061 CYREG_SFLASH_AV_PAIRS_8B61
|
|
#define CYREG_SFLASH_AV_PAIRS_8B062 CYREG_SFLASH_AV_PAIRS_8B62
|
|
#define CYREG_SFLASH_AV_PAIRS_8B063 CYREG_SFLASH_AV_PAIRS_8B63
|
|
#define CYREG_SFLASH_AV_PAIRS_8B064 CYREG_SFLASH_AV_PAIRS_8B64
|
|
#define CYREG_SFLASH_AV_PAIRS_8B065 CYREG_SFLASH_AV_PAIRS_8B65
|
|
#define CYREG_SFLASH_AV_PAIRS_8B066 CYREG_SFLASH_AV_PAIRS_8B66
|
|
#define CYREG_SFLASH_AV_PAIRS_8B067 CYREG_SFLASH_AV_PAIRS_8B67
|
|
#define CYREG_SFLASH_AV_PAIRS_8B068 CYREG_SFLASH_AV_PAIRS_8B68
|
|
#define CYREG_SFLASH_AV_PAIRS_8B069 CYREG_SFLASH_AV_PAIRS_8B69
|
|
#define CYREG_SFLASH_AV_PAIRS_8B070 CYREG_SFLASH_AV_PAIRS_8B70
|
|
#define CYREG_SFLASH_AV_PAIRS_8B071 CYREG_SFLASH_AV_PAIRS_8B71
|
|
#define CYREG_SFLASH_AV_PAIRS_8B072 CYREG_SFLASH_AV_PAIRS_8B72
|
|
#define CYREG_SFLASH_AV_PAIRS_8B073 CYREG_SFLASH_AV_PAIRS_8B73
|
|
#define CYREG_SFLASH_AV_PAIRS_8B074 CYREG_SFLASH_AV_PAIRS_8B74
|
|
#define CYREG_SFLASH_AV_PAIRS_8B075 CYREG_SFLASH_AV_PAIRS_8B75
|
|
#define CYREG_SFLASH_AV_PAIRS_8B076 CYREG_SFLASH_AV_PAIRS_8B76
|
|
#define CYREG_SFLASH_AV_PAIRS_8B077 CYREG_SFLASH_AV_PAIRS_8B77
|
|
#define CYREG_SFLASH_AV_PAIRS_8B078 CYREG_SFLASH_AV_PAIRS_8B78
|
|
#define CYREG_SFLASH_AV_PAIRS_8B079 CYREG_SFLASH_AV_PAIRS_8B79
|
|
#define CYREG_SFLASH_AV_PAIRS_8B080 CYREG_SFLASH_AV_PAIRS_8B80
|
|
#define CYREG_SFLASH_AV_PAIRS_8B081 CYREG_SFLASH_AV_PAIRS_8B81
|
|
#define CYREG_SFLASH_AV_PAIRS_8B082 CYREG_SFLASH_AV_PAIRS_8B82
|
|
#define CYREG_SFLASH_AV_PAIRS_8B083 CYREG_SFLASH_AV_PAIRS_8B83
|
|
#define CYREG_SFLASH_AV_PAIRS_8B084 CYREG_SFLASH_AV_PAIRS_8B84
|
|
#define CYREG_SFLASH_AV_PAIRS_8B085 CYREG_SFLASH_AV_PAIRS_8B85
|
|
#define CYREG_SFLASH_AV_PAIRS_8B086 CYREG_SFLASH_AV_PAIRS_8B86
|
|
#define CYREG_SFLASH_AV_PAIRS_8B087 CYREG_SFLASH_AV_PAIRS_8B87
|
|
#define CYREG_SFLASH_AV_PAIRS_8B088 CYREG_SFLASH_AV_PAIRS_8B88
|
|
#define CYREG_SFLASH_AV_PAIRS_8B089 CYREG_SFLASH_AV_PAIRS_8B89
|
|
#define CYREG_SFLASH_AV_PAIRS_8B090 CYREG_SFLASH_AV_PAIRS_8B90
|
|
#define CYREG_SFLASH_AV_PAIRS_8B091 CYREG_SFLASH_AV_PAIRS_8B91
|
|
#define CYREG_SFLASH_AV_PAIRS_8B092 CYREG_SFLASH_AV_PAIRS_8B92
|
|
#define CYREG_SFLASH_AV_PAIRS_8B093 CYREG_SFLASH_AV_PAIRS_8B93
|
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#define CYREG_SFLASH_AV_PAIRS_8B094 CYREG_SFLASH_AV_PAIRS_8B94
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#define CYREG_SFLASH_AV_PAIRS_8B095 CYREG_SFLASH_AV_PAIRS_8B95
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#define CYREG_SFLASH_AV_PAIRS_8B096 CYREG_SFLASH_AV_PAIRS_8B96
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#define CYREG_SFLASH_AV_PAIRS_8B097 CYREG_SFLASH_AV_PAIRS_8B97
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#define CYREG_SFLASH_AV_PAIRS_8B098 CYREG_SFLASH_AV_PAIRS_8B98
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#define CYREG_SFLASH_AV_PAIRS_8B099 CYREG_SFLASH_AV_PAIRS_8B99
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#define CYREG_SFLASH_AV_PAIRS_32B00 CYREG_SFLASH_AV_PAIRS_32B0
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#define CYREG_SFLASH_AV_PAIRS_32B01 CYREG_SFLASH_AV_PAIRS_32B1
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#define CYREG_SFLASH_AV_PAIRS_32B02 CYREG_SFLASH_AV_PAIRS_32B2
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#define CYREG_SFLASH_AV_PAIRS_32B03 CYREG_SFLASH_AV_PAIRS_32B3
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#define CYREG_SFLASH_AV_PAIRS_32B04 CYREG_SFLASH_AV_PAIRS_32B4
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#define CYREG_SFLASH_AV_PAIRS_32B05 CYREG_SFLASH_AV_PAIRS_32B5
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#define CYREG_SFLASH_AV_PAIRS_32B06 CYREG_SFLASH_AV_PAIRS_32B6
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#define CYREG_SFLASH_AV_PAIRS_32B07 CYREG_SFLASH_AV_PAIRS_32B7
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#define CYREG_SFLASH_AV_PAIRS_32B08 CYREG_SFLASH_AV_PAIRS_32B8
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#define CYREG_SFLASH_AV_PAIRS_32B09 CYREG_SFLASH_AV_PAIRS_32B9
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#define CYREG_SFLASH_PE_TE_DATA00 CYREG_SFLASH_PE_TE_DATA0
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#define CYREG_SFLASH_PE_TE_DATA01 CYREG_SFLASH_PE_TE_DATA1
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#define CYREG_SFLASH_PE_TE_DATA02 CYREG_SFLASH_PE_TE_DATA2
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#define CYREG_SFLASH_PE_TE_DATA03 CYREG_SFLASH_PE_TE_DATA3
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#define CYREG_SFLASH_PE_TE_DATA04 CYREG_SFLASH_PE_TE_DATA4
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#define CYREG_SFLASH_PE_TE_DATA05 CYREG_SFLASH_PE_TE_DATA5
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#define CYREG_SFLASH_PE_TE_DATA06 CYREG_SFLASH_PE_TE_DATA6
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#define CYREG_SFLASH_PE_TE_DATA07 CYREG_SFLASH_PE_TE_DATA7
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#define CYREG_SFLASH_PE_TE_DATA08 CYREG_SFLASH_PE_TE_DATA8
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#define CYREG_SFLASH_PE_TE_DATA09 CYREG_SFLASH_PE_TE_DATA9
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#define CYREG_SFLASH_IMO_TRIM00 CYREG_SFLASH_IMO_TRIM0
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#define CYREG_SFLASH_IMO_TRIM01 CYREG_SFLASH_IMO_TRIM1
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#define CYREG_SFLASH_IMO_TRIM02 CYREG_SFLASH_IMO_TRIM2
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#define CYREG_SFLASH_IMO_TRIM03 CYREG_SFLASH_IMO_TRIM3
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#define CYREG_SFLASH_IMO_TRIM04 CYREG_SFLASH_IMO_TRIM4
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#define CYREG_SFLASH_IMO_TRIM05 CYREG_SFLASH_IMO_TRIM5
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#define CYREG_SFLASH_IMO_TRIM06 CYREG_SFLASH_IMO_TRIM6
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#define CYREG_SFLASH_IMO_TRIM07 CYREG_SFLASH_IMO_TRIM7
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#define CYREG_SFLASH_IMO_TRIM08 CYREG_SFLASH_IMO_TRIM8
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#define CYREG_SFLASH_IMO_TRIM09 CYREG_SFLASH_IMO_TRIM9
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#define CYREG_SFLASH_ALT_PROT_ROW000 CYREG_SFLASH_ALT_PROT_ROW0
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#define CYREG_SFLASH_ALT_PROT_ROW001 CYREG_SFLASH_ALT_PROT_ROW1
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#define CYREG_SFLASH_ALT_PROT_ROW002 CYREG_SFLASH_ALT_PROT_ROW2
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#define CYREG_SFLASH_ALT_PROT_ROW003 CYREG_SFLASH_ALT_PROT_ROW3
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#define CYREG_SFLASH_ALT_PROT_ROW004 CYREG_SFLASH_ALT_PROT_ROW4
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#define CYREG_SFLASH_ALT_PROT_ROW005 CYREG_SFLASH_ALT_PROT_ROW5
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#define CYREG_SFLASH_ALT_PROT_ROW006 CYREG_SFLASH_ALT_PROT_ROW6
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#define CYREG_SFLASH_ALT_PROT_ROW007 CYREG_SFLASH_ALT_PROT_ROW7
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#define CYREG_SFLASH_ALT_PROT_ROW008 CYREG_SFLASH_ALT_PROT_ROW8
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#define CYREG_SFLASH_ALT_PROT_ROW009 CYREG_SFLASH_ALT_PROT_ROW9
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#define CYREG_SFLASH_ALT_PROT_ROW010 CYREG_SFLASH_ALT_PROT_ROW10
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#define CYREG_SFLASH_ALT_PROT_ROW011 CYREG_SFLASH_ALT_PROT_ROW11
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#define CYREG_SFLASH_ALT_PROT_ROW012 CYREG_SFLASH_ALT_PROT_ROW12
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#define CYREG_SFLASH_ALT_PROT_ROW013 CYREG_SFLASH_ALT_PROT_ROW13
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#define CYREG_SFLASH_ALT_PROT_ROW014 CYREG_SFLASH_ALT_PROT_ROW14
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#define CYREG_SFLASH_ALT_PROT_ROW015 CYREG_SFLASH_ALT_PROT_ROW15
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#define CYREG_SFLASH_ALT_PROT_ROW016 CYREG_SFLASH_ALT_PROT_ROW16
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#define CYREG_SFLASH_ALT_PROT_ROW017 CYREG_SFLASH_ALT_PROT_ROW17
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#define CYREG_SFLASH_ALT_PROT_ROW018 CYREG_SFLASH_ALT_PROT_ROW18
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#define CYREG_SFLASH_ALT_PROT_ROW019 CYREG_SFLASH_ALT_PROT_ROW19
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#define CYREG_SFLASH_ALT_PROT_ROW020 CYREG_SFLASH_ALT_PROT_ROW20
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#define CYREG_SFLASH_ALT_PROT_ROW021 CYREG_SFLASH_ALT_PROT_ROW21
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#define CYREG_SFLASH_ALT_PROT_ROW022 CYREG_SFLASH_ALT_PROT_ROW22
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#define CYREG_SFLASH_ALT_PROT_ROW023 CYREG_SFLASH_ALT_PROT_ROW23
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#define CYREG_SFLASH_ALT_PROT_ROW024 CYREG_SFLASH_ALT_PROT_ROW24
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#define CYREG_SFLASH_ALT_PROT_ROW025 CYREG_SFLASH_ALT_PROT_ROW25
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#define CYREG_SFLASH_ALT_PROT_ROW026 CYREG_SFLASH_ALT_PROT_ROW26
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#define CYREG_SFLASH_ALT_PROT_ROW027 CYREG_SFLASH_ALT_PROT_ROW27
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#define CYREG_SFLASH_ALT_PROT_ROW028 CYREG_SFLASH_ALT_PROT_ROW28
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#define CYREG_SFLASH_ALT_PROT_ROW029 CYREG_SFLASH_ALT_PROT_ROW29
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#define CYREG_SFLASH_ALT_PROT_ROW030 CYREG_SFLASH_ALT_PROT_ROW30
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#define CYREG_SFLASH_ALT_PROT_ROW031 CYREG_SFLASH_ALT_PROT_ROW31
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#define CYREG_SFLASH_ALT_PROT_ROW032 CYREG_SFLASH_ALT_PROT_ROW32
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#define CYREG_SFLASH_ALT_PROT_ROW033 CYREG_SFLASH_ALT_PROT_ROW33
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#define CYREG_SFLASH_ALT_PROT_ROW034 CYREG_SFLASH_ALT_PROT_ROW34
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#define CYREG_SFLASH_ALT_PROT_ROW035 CYREG_SFLASH_ALT_PROT_ROW35
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#define CYREG_SFLASH_ALT_PROT_ROW036 CYREG_SFLASH_ALT_PROT_ROW36
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#define CYREG_SFLASH_ALT_PROT_ROW037 CYREG_SFLASH_ALT_PROT_ROW37
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#define CYREG_SFLASH_ALT_PROT_ROW038 CYREG_SFLASH_ALT_PROT_ROW38
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#define CYREG_SFLASH_ALT_PROT_ROW039 CYREG_SFLASH_ALT_PROT_ROW39
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#define CYREG_SFLASH_ALT_PROT_ROW040 CYREG_SFLASH_ALT_PROT_ROW40
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#define CYREG_SFLASH_ALT_PROT_ROW041 CYREG_SFLASH_ALT_PROT_ROW41
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#define CYREG_SFLASH_ALT_PROT_ROW042 CYREG_SFLASH_ALT_PROT_ROW42
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#define CYREG_SFLASH_ALT_PROT_ROW043 CYREG_SFLASH_ALT_PROT_ROW43
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#define CYREG_SFLASH_ALT_PROT_ROW044 CYREG_SFLASH_ALT_PROT_ROW44
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#define CYREG_SFLASH_ALT_PROT_ROW045 CYREG_SFLASH_ALT_PROT_ROW45
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#define CYREG_SFLASH_ALT_PROT_ROW046 CYREG_SFLASH_ALT_PROT_ROW46
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#define CYREG_SFLASH_ALT_PROT_ROW047 CYREG_SFLASH_ALT_PROT_ROW47
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#define CYREG_SFLASH_ALT_PROT_ROW048 CYREG_SFLASH_ALT_PROT_ROW48
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#define CYREG_SFLASH_ALT_PROT_ROW049 CYREG_SFLASH_ALT_PROT_ROW49
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#define CYREG_SFLASH_ALT_PROT_ROW050 CYREG_SFLASH_ALT_PROT_ROW50
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#define CYREG_SFLASH_ALT_PROT_ROW051 CYREG_SFLASH_ALT_PROT_ROW51
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#define CYREG_SFLASH_ALT_PROT_ROW052 CYREG_SFLASH_ALT_PROT_ROW52
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#define CYREG_SFLASH_ALT_PROT_ROW053 CYREG_SFLASH_ALT_PROT_ROW53
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#define CYREG_SFLASH_ALT_PROT_ROW054 CYREG_SFLASH_ALT_PROT_ROW54
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#define CYREG_SFLASH_ALT_PROT_ROW055 CYREG_SFLASH_ALT_PROT_ROW55
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#define CYREG_SFLASH_ALT_PROT_ROW056 CYREG_SFLASH_ALT_PROT_ROW56
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#define CYREG_SFLASH_ALT_PROT_ROW057 CYREG_SFLASH_ALT_PROT_ROW57
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#define CYREG_SFLASH_ALT_PROT_ROW058 CYREG_SFLASH_ALT_PROT_ROW58
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#define CYREG_SFLASH_ALT_PROT_ROW059 CYREG_SFLASH_ALT_PROT_ROW59
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#define CYREG_SFLASH_ALT_PROT_ROW060 CYREG_SFLASH_ALT_PROT_ROW60
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#define CYREG_SFLASH_ALT_PROT_ROW061 CYREG_SFLASH_ALT_PROT_ROW61
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#define CYREG_SFLASH_ALT_PROT_ROW062 CYREG_SFLASH_ALT_PROT_ROW62
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#define CYREG_SFLASH_ALT_PROT_ROW063 CYREG_SFLASH_ALT_PROT_ROW63
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#define CYREG_SFLASH_ALT_PROT_ROW064 CYREG_SFLASH_ALT_PROT_ROW64
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#define CYREG_SFLASH_ALT_PROT_ROW065 CYREG_SFLASH_ALT_PROT_ROW65
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#define CYREG_SFLASH_ALT_PROT_ROW066 CYREG_SFLASH_ALT_PROT_ROW66
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#define CYREG_SFLASH_ALT_PROT_ROW067 CYREG_SFLASH_ALT_PROT_ROW67
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#define CYREG_SFLASH_ALT_PROT_ROW068 CYREG_SFLASH_ALT_PROT_ROW68
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#define CYREG_SFLASH_ALT_PROT_ROW069 CYREG_SFLASH_ALT_PROT_ROW69
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#define CYREG_SFLASH_ALT_PROT_ROW070 CYREG_SFLASH_ALT_PROT_ROW70
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#define CYREG_SFLASH_ALT_PROT_ROW071 CYREG_SFLASH_ALT_PROT_ROW71
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#define CYREG_SFLASH_ALT_PROT_ROW072 CYREG_SFLASH_ALT_PROT_ROW72
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#define CYREG_SFLASH_ALT_PROT_ROW073 CYREG_SFLASH_ALT_PROT_ROW73
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#define CYREG_SFLASH_ALT_PROT_ROW074 CYREG_SFLASH_ALT_PROT_ROW74
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#define CYREG_SFLASH_ALT_PROT_ROW075 CYREG_SFLASH_ALT_PROT_ROW75
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#define CYREG_SFLASH_ALT_PROT_ROW076 CYREG_SFLASH_ALT_PROT_ROW76
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#define CYREG_SFLASH_ALT_PROT_ROW077 CYREG_SFLASH_ALT_PROT_ROW77
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#define CYREG_SFLASH_ALT_PROT_ROW078 CYREG_SFLASH_ALT_PROT_ROW78
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#define CYREG_SFLASH_ALT_PROT_ROW079 CYREG_SFLASH_ALT_PROT_ROW79
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#define CYREG_SFLASH_ALT_PROT_ROW080 CYREG_SFLASH_ALT_PROT_ROW80
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#define CYREG_SFLASH_ALT_PROT_ROW081 CYREG_SFLASH_ALT_PROT_ROW81
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#define CYREG_SFLASH_ALT_PROT_ROW082 CYREG_SFLASH_ALT_PROT_ROW82
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#define CYREG_SFLASH_ALT_PROT_ROW083 CYREG_SFLASH_ALT_PROT_ROW83
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#define CYREG_SFLASH_ALT_PROT_ROW084 CYREG_SFLASH_ALT_PROT_ROW84
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#define CYREG_SFLASH_ALT_PROT_ROW085 CYREG_SFLASH_ALT_PROT_ROW85
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#define CYREG_SFLASH_ALT_PROT_ROW086 CYREG_SFLASH_ALT_PROT_ROW86
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#define CYREG_SFLASH_ALT_PROT_ROW087 CYREG_SFLASH_ALT_PROT_ROW87
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#define CYREG_SFLASH_ALT_PROT_ROW088 CYREG_SFLASH_ALT_PROT_ROW88
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#define CYREG_SFLASH_ALT_PROT_ROW089 CYREG_SFLASH_ALT_PROT_ROW89
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#define CYREG_SFLASH_ALT_PROT_ROW090 CYREG_SFLASH_ALT_PROT_ROW90
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#define CYREG_SFLASH_ALT_PROT_ROW091 CYREG_SFLASH_ALT_PROT_ROW91
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#define CYREG_SFLASH_ALT_PROT_ROW092 CYREG_SFLASH_ALT_PROT_ROW92
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#define CYREG_SFLASH_ALT_PROT_ROW093 CYREG_SFLASH_ALT_PROT_ROW93
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#define CYREG_SFLASH_ALT_PROT_ROW094 CYREG_SFLASH_ALT_PROT_ROW94
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#define CYREG_SFLASH_ALT_PROT_ROW095 CYREG_SFLASH_ALT_PROT_ROW95
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#define CYREG_SFLASH_ALT_PROT_ROW096 CYREG_SFLASH_ALT_PROT_ROW96
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#define CYREG_SFLASH_ALT_PROT_ROW097 CYREG_SFLASH_ALT_PROT_ROW97
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#define CYREG_SFLASH_ALT_PROT_ROW098 CYREG_SFLASH_ALT_PROT_ROW98
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#define CYREG_SFLASH_ALT_PROT_ROW099 CYREG_SFLASH_ALT_PROT_ROW99
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#define CYREG_PERI_PCLK_CTL00 CYREG_PERI_PCLK_CTL0
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#define CYREG_PERI_PCLK_CTL01 CYREG_PERI_PCLK_CTL1
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#define CYREG_PERI_PCLK_CTL02 CYREG_PERI_PCLK_CTL2
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#define CYREG_PERI_PCLK_CTL03 CYREG_PERI_PCLK_CTL3
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#define CYREG_PERI_PCLK_CTL04 CYREG_PERI_PCLK_CTL4
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#define CYREG_PERI_PCLK_CTL05 CYREG_PERI_PCLK_CTL5
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#define CYREG_PERI_PCLK_CTL06 CYREG_PERI_PCLK_CTL6
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#define CYREG_PERI_PCLK_CTL07 CYREG_PERI_PCLK_CTL7
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#define CYREG_PERI_PCLK_CTL08 CYREG_PERI_PCLK_CTL8
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#define CYREG_PERI_PCLK_CTL09 CYREG_PERI_PCLK_CTL9
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#define CYREG_PERI_DIV_16_CTL00 CYREG_PERI_DIV_16_CTL0
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#define CYREG_PERI_DIV_16_CTL01 CYREG_PERI_DIV_16_CTL1
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#define CYREG_PERI_DIV_16_CTL02 CYREG_PERI_DIV_16_CTL2
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#define CYREG_PERI_DIV_16_CTL03 CYREG_PERI_DIV_16_CTL3
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#define CYREG_PERI_DIV_16_CTL04 CYREG_PERI_DIV_16_CTL4
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#define CYREG_PERI_DIV_16_CTL05 CYREG_PERI_DIV_16_CTL5
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#define CYREG_PERI_DIV_16_CTL06 CYREG_PERI_DIV_16_CTL6
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#define CYREG_PERI_DIV_16_CTL07 CYREG_PERI_DIV_16_CTL7
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#define CYREG_PERI_DIV_16_CTL08 CYREG_PERI_DIV_16_CTL8
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#define CYREG_PERI_DIV_16_CTL09 CYREG_PERI_DIV_16_CTL9
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#define CYREG_PERI_DIV_16_5_CTL00 CYREG_PERI_DIV_16_5_CTL0
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#define CYREG_PERI_DIV_16_5_CTL01 CYREG_PERI_DIV_16_5_CTL1
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#define CYREG_UDB_W8_A0_00 CYREG_UDB_W8_A00
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#define CYREG_UDB_W8_A0_01 CYREG_UDB_W8_A01
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#define CYREG_UDB_W8_A0_02 CYREG_UDB_W8_A02
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#define CYREG_UDB_W8_A0_03 CYREG_UDB_W8_A03
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#define CYREG_UDB_W8_A1_00 CYREG_UDB_W8_A10
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#define CYREG_UDB_W8_A1_01 CYREG_UDB_W8_A11
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#define CYREG_UDB_W8_A1_02 CYREG_UDB_W8_A12
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#define CYREG_UDB_W8_A1_03 CYREG_UDB_W8_A13
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#define CYREG_UDB_W8_D0_00 CYREG_UDB_W8_D00
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#define CYREG_UDB_W8_D0_01 CYREG_UDB_W8_D01
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#define CYREG_UDB_W8_D0_02 CYREG_UDB_W8_D02
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#define CYREG_UDB_W8_D0_03 CYREG_UDB_W8_D03
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#define CYREG_UDB_W8_D1_00 CYREG_UDB_W8_D10
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#define CYREG_UDB_W8_D1_01 CYREG_UDB_W8_D11
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#define CYREG_UDB_W8_D1_02 CYREG_UDB_W8_D12
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#define CYREG_UDB_W8_D1_03 CYREG_UDB_W8_D13
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#define CYREG_UDB_W8_F0_00 CYREG_UDB_W8_F00
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#define CYREG_UDB_W8_F0_01 CYREG_UDB_W8_F01
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#define CYREG_UDB_W8_F0_02 CYREG_UDB_W8_F02
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#define CYREG_UDB_W8_F0_03 CYREG_UDB_W8_F03
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#define CYREG_UDB_W8_F1_00 CYREG_UDB_W8_F10
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#define CYREG_UDB_W8_F1_01 CYREG_UDB_W8_F11
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#define CYREG_UDB_W8_F1_02 CYREG_UDB_W8_F12
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#define CYREG_UDB_W8_F1_03 CYREG_UDB_W8_F13
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#define CYREG_UDB_W8_ST_00 CYREG_UDB_W8_ST0
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#define CYREG_UDB_W8_ST_01 CYREG_UDB_W8_ST1
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#define CYREG_UDB_W8_ST_02 CYREG_UDB_W8_ST2
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#define CYREG_UDB_W8_ST_03 CYREG_UDB_W8_ST3
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#define CYREG_UDB_W8_CTL_00 CYREG_UDB_W8_CTL0
|
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#define CYREG_UDB_W8_CTL_01 CYREG_UDB_W8_CTL1
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#define CYREG_UDB_W8_CTL_02 CYREG_UDB_W8_CTL2
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#define CYREG_UDB_W8_CTL_03 CYREG_UDB_W8_CTL3
|
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#define CYREG_UDB_W8_MSK_00 CYREG_UDB_W8_MSK0
|
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#define CYREG_UDB_W8_MSK_01 CYREG_UDB_W8_MSK1
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#define CYREG_UDB_W8_MSK_02 CYREG_UDB_W8_MSK2
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#define CYREG_UDB_W8_MSK_03 CYREG_UDB_W8_MSK3
|
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#define CYREG_UDB_W8_ACTL_00 CYREG_UDB_W8_ACTL0
|
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#define CYREG_UDB_W8_ACTL_01 CYREG_UDB_W8_ACTL1
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#define CYREG_UDB_W8_ACTL_02 CYREG_UDB_W8_ACTL2
|
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#define CYREG_UDB_W8_ACTL_03 CYREG_UDB_W8_ACTL3
|
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#define CYREG_UDB_W8_MC_00 CYREG_UDB_W8_MC0
|
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#define CYREG_UDB_W8_MC_01 CYREG_UDB_W8_MC1
|
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#define CYREG_UDB_W8_MC_02 CYREG_UDB_W8_MC2
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#define CYREG_UDB_W8_MC_03 CYREG_UDB_W8_MC3
|
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#define CYREG_UDB_CAT16_A_00 CYREG_UDB_CAT16_A0
|
|
#define CYREG_UDB_CAT16_A_01 CYREG_UDB_CAT16_A1
|
|
#define CYREG_UDB_CAT16_A_02 CYREG_UDB_CAT16_A2
|
|
#define CYREG_UDB_CAT16_A_03 CYREG_UDB_CAT16_A3
|
|
#define CYREG_UDB_CAT16_D_00 CYREG_UDB_CAT16_D0
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#define CYREG_UDB_CAT16_D_01 CYREG_UDB_CAT16_D1
|
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#define CYREG_UDB_CAT16_D_02 CYREG_UDB_CAT16_D2
|
|
#define CYREG_UDB_CAT16_D_03 CYREG_UDB_CAT16_D3
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|
#define CYREG_UDB_CAT16_F_00 CYREG_UDB_CAT16_F0
|
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#define CYREG_UDB_CAT16_F_01 CYREG_UDB_CAT16_F1
|
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#define CYREG_UDB_CAT16_F_02 CYREG_UDB_CAT16_F2
|
|
#define CYREG_UDB_CAT16_F_03 CYREG_UDB_CAT16_F3
|
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#define CYREG_UDB_CAT16_CTL_ST_00 CYREG_UDB_CAT16_CTL_ST0
|
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#define CYREG_UDB_CAT16_CTL_ST_01 CYREG_UDB_CAT16_CTL_ST1
|
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#define CYREG_UDB_CAT16_CTL_ST_02 CYREG_UDB_CAT16_CTL_ST2
|
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#define CYREG_UDB_CAT16_CTL_ST_03 CYREG_UDB_CAT16_CTL_ST3
|
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#define CYREG_UDB_CAT16_ACTL_MSK_00 CYREG_UDB_CAT16_ACTL_MSK0
|
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#define CYREG_UDB_CAT16_ACTL_MSK_01 CYREG_UDB_CAT16_ACTL_MSK1
|
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#define CYREG_UDB_CAT16_ACTL_MSK_02 CYREG_UDB_CAT16_ACTL_MSK2
|
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#define CYREG_UDB_CAT16_ACTL_MSK_03 CYREG_UDB_CAT16_ACTL_MSK3
|
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#define CYREG_UDB_CAT16_MC_00 CYREG_UDB_CAT16_MC0
|
|
#define CYREG_UDB_CAT16_MC_01 CYREG_UDB_CAT16_MC1
|
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#define CYREG_UDB_CAT16_MC_02 CYREG_UDB_CAT16_MC2
|
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#define CYREG_UDB_CAT16_MC_03 CYREG_UDB_CAT16_MC3
|
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#define CYREG_UDB_W16_A0_00 CYREG_UDB_W16_A00
|
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#define CYREG_UDB_W16_A0_01 CYREG_UDB_W16_A01
|
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#define CYREG_UDB_W16_A0_02 CYREG_UDB_W16_A02
|
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#define CYREG_UDB_W16_A1_00 CYREG_UDB_W16_A10
|
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#define CYREG_UDB_W16_A1_01 CYREG_UDB_W16_A11
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#define CYREG_UDB_W16_A1_02 CYREG_UDB_W16_A12
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#define CYREG_UDB_W16_D0_00 CYREG_UDB_W16_D00
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#define CYREG_UDB_W16_D0_01 CYREG_UDB_W16_D01
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#define CYREG_UDB_W16_D0_02 CYREG_UDB_W16_D02
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#define CYREG_UDB_W16_D1_00 CYREG_UDB_W16_D10
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#define CYREG_UDB_W16_D1_01 CYREG_UDB_W16_D11
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#define CYREG_UDB_W16_D1_02 CYREG_UDB_W16_D12
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#define CYREG_UDB_W16_F0_00 CYREG_UDB_W16_F00
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#define CYREG_UDB_W16_F0_01 CYREG_UDB_W16_F01
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#define CYREG_UDB_W16_F0_02 CYREG_UDB_W16_F02
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#define CYREG_UDB_W16_F1_00 CYREG_UDB_W16_F10
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#define CYREG_UDB_W16_F1_01 CYREG_UDB_W16_F11
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#define CYREG_UDB_W16_F1_02 CYREG_UDB_W16_F12
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#define CYREG_UDB_W16_ST_00 CYREG_UDB_W16_ST0
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#define CYREG_UDB_W16_ST_01 CYREG_UDB_W16_ST1
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#define CYREG_UDB_W16_ST_02 CYREG_UDB_W16_ST2
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#define CYREG_UDB_W16_CTL_00 CYREG_UDB_W16_CTL0
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#define CYREG_UDB_W16_CTL_01 CYREG_UDB_W16_CTL1
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#define CYREG_UDB_W16_CTL_02 CYREG_UDB_W16_CTL2
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#define CYREG_UDB_W16_MSK_00 CYREG_UDB_W16_MSK0
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#define CYREG_UDB_W16_MSK_01 CYREG_UDB_W16_MSK1
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#define CYREG_UDB_W16_MSK_02 CYREG_UDB_W16_MSK2
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#define CYREG_UDB_W16_ACTL_00 CYREG_UDB_W16_ACTL0
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#define CYREG_UDB_W16_ACTL_01 CYREG_UDB_W16_ACTL1
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#define CYREG_UDB_W16_ACTL_02 CYREG_UDB_W16_ACTL2
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#define CYREG_UDB_W16_MC_00 CYREG_UDB_W16_MC0
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#define CYREG_UDB_W16_MC_01 CYREG_UDB_W16_MC1
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#define CYREG_UDB_W16_MC_02 CYREG_UDB_W16_MC2
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#define CYREG_UDB_W32_A0_00 CYREG_UDB_W32_A0
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#define CYREG_UDB_W32_A1_00 CYREG_UDB_W32_A1
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#define CYREG_UDB_W32_D0_00 CYREG_UDB_W32_D0
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#define CYREG_UDB_W32_D1_00 CYREG_UDB_W32_D1
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#define CYREG_UDB_W32_F0_00 CYREG_UDB_W32_F0
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#define CYREG_UDB_W32_F1_00 CYREG_UDB_W32_F1
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#define CYREG_UDB_W32_ST_00 CYREG_UDB_W32_ST
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#define CYREG_UDB_W32_CTL_00 CYREG_UDB_W32_CTL
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#define CYREG_UDB_W32_MSK_00 CYREG_UDB_W32_MSK
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#define CYREG_UDB_W32_ACTL_00 CYREG_UDB_W32_ACTL
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#define CYREG_UDB_W32_MC_00 CYREG_UDB_W32_MC
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#define CYREG_SCB0_EZ_DATA000 CYREG_SCB0_EZ_DATA0
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#define CYREG_SCB0_EZ_DATA001 CYREG_SCB0_EZ_DATA1
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#define CYREG_SCB0_EZ_DATA002 CYREG_SCB0_EZ_DATA2
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#define CYREG_SCB0_EZ_DATA003 CYREG_SCB0_EZ_DATA3
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#define CYREG_SCB0_EZ_DATA004 CYREG_SCB0_EZ_DATA4
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#define CYREG_SCB0_EZ_DATA005 CYREG_SCB0_EZ_DATA5
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#define CYREG_SCB0_EZ_DATA006 CYREG_SCB0_EZ_DATA6
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#define CYREG_SCB0_EZ_DATA007 CYREG_SCB0_EZ_DATA7
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#define CYREG_SCB0_EZ_DATA008 CYREG_SCB0_EZ_DATA8
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#define CYREG_SCB0_EZ_DATA009 CYREG_SCB0_EZ_DATA9
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#define CYREG_SCB0_EZ_DATA010 CYREG_SCB0_EZ_DATA10
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#define CYREG_SCB0_EZ_DATA011 CYREG_SCB0_EZ_DATA11
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#define CYREG_SCB0_EZ_DATA012 CYREG_SCB0_EZ_DATA12
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#define CYREG_SCB0_EZ_DATA013 CYREG_SCB0_EZ_DATA13
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#define CYREG_SCB0_EZ_DATA014 CYREG_SCB0_EZ_DATA14
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#define CYREG_SCB0_EZ_DATA015 CYREG_SCB0_EZ_DATA15
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#define CYREG_SCB0_EZ_DATA016 CYREG_SCB0_EZ_DATA16
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#define CYREG_SCB0_EZ_DATA017 CYREG_SCB0_EZ_DATA17
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#define CYREG_SCB0_EZ_DATA018 CYREG_SCB0_EZ_DATA18
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#define CYREG_SCB0_EZ_DATA019 CYREG_SCB0_EZ_DATA19
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#define CYREG_SCB0_EZ_DATA020 CYREG_SCB0_EZ_DATA20
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#define CYREG_SCB0_EZ_DATA021 CYREG_SCB0_EZ_DATA21
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#define CYREG_SCB0_EZ_DATA022 CYREG_SCB0_EZ_DATA22
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#define CYREG_SCB0_EZ_DATA023 CYREG_SCB0_EZ_DATA23
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#define CYREG_SCB0_EZ_DATA024 CYREG_SCB0_EZ_DATA24
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#define CYREG_SCB0_EZ_DATA025 CYREG_SCB0_EZ_DATA25
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#define CYREG_SCB0_EZ_DATA026 CYREG_SCB0_EZ_DATA26
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#define CYREG_SCB0_EZ_DATA027 CYREG_SCB0_EZ_DATA27
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#define CYREG_SCB0_EZ_DATA028 CYREG_SCB0_EZ_DATA28
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#define CYREG_SCB0_EZ_DATA029 CYREG_SCB0_EZ_DATA29
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#define CYREG_SCB0_EZ_DATA030 CYREG_SCB0_EZ_DATA30
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#define CYREG_SCB0_EZ_DATA031 CYREG_SCB0_EZ_DATA31
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#define CYREG_SCB1_EZ_DATA000 CYREG_SCB1_EZ_DATA0
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#define CYREG_SCB1_EZ_DATA001 CYREG_SCB1_EZ_DATA1
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#define CYREG_SCB1_EZ_DATA002 CYREG_SCB1_EZ_DATA2
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#define CYREG_SCB1_EZ_DATA003 CYREG_SCB1_EZ_DATA3
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#define CYREG_SCB1_EZ_DATA004 CYREG_SCB1_EZ_DATA4
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#define CYREG_SCB1_EZ_DATA005 CYREG_SCB1_EZ_DATA5
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#define CYREG_SCB1_EZ_DATA006 CYREG_SCB1_EZ_DATA6
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#define CYREG_SCB1_EZ_DATA007 CYREG_SCB1_EZ_DATA7
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#define CYREG_SCB1_EZ_DATA008 CYREG_SCB1_EZ_DATA8
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#define CYREG_SCB1_EZ_DATA009 CYREG_SCB1_EZ_DATA9
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#define CYREG_SCB1_EZ_DATA010 CYREG_SCB1_EZ_DATA10
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#define CYREG_SCB1_EZ_DATA011 CYREG_SCB1_EZ_DATA11
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#define CYREG_SCB1_EZ_DATA012 CYREG_SCB1_EZ_DATA12
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#define CYREG_SCB1_EZ_DATA013 CYREG_SCB1_EZ_DATA13
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#define CYREG_SCB1_EZ_DATA014 CYREG_SCB1_EZ_DATA14
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#define CYREG_SCB1_EZ_DATA015 CYREG_SCB1_EZ_DATA15
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#define CYREG_SCB1_EZ_DATA016 CYREG_SCB1_EZ_DATA16
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#define CYREG_SCB1_EZ_DATA017 CYREG_SCB1_EZ_DATA17
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#define CYREG_SCB1_EZ_DATA018 CYREG_SCB1_EZ_DATA18
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#define CYREG_SCB1_EZ_DATA019 CYREG_SCB1_EZ_DATA19
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#define CYREG_SCB1_EZ_DATA020 CYREG_SCB1_EZ_DATA20
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#define CYREG_SCB1_EZ_DATA021 CYREG_SCB1_EZ_DATA21
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#define CYREG_SCB1_EZ_DATA022 CYREG_SCB1_EZ_DATA22
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#define CYREG_SCB1_EZ_DATA023 CYREG_SCB1_EZ_DATA23
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#define CYREG_SCB1_EZ_DATA024 CYREG_SCB1_EZ_DATA24
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#define CYREG_SCB1_EZ_DATA025 CYREG_SCB1_EZ_DATA25
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#define CYREG_SCB1_EZ_DATA026 CYREG_SCB1_EZ_DATA26
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#define CYREG_SCB1_EZ_DATA027 CYREG_SCB1_EZ_DATA27
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#define CYREG_SCB1_EZ_DATA028 CYREG_SCB1_EZ_DATA28
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#define CYREG_SCB1_EZ_DATA029 CYREG_SCB1_EZ_DATA29
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#define CYREG_SCB1_EZ_DATA030 CYREG_SCB1_EZ_DATA30
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#define CYREG_SCB1_EZ_DATA031 CYREG_SCB1_EZ_DATA31
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#define CYREG_SAR_CHAN_CONFIG00 CYREG_SAR_CHAN_CONFIG0
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#define CYREG_SAR_CHAN_CONFIG01 CYREG_SAR_CHAN_CONFIG1
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#define CYREG_SAR_CHAN_CONFIG02 CYREG_SAR_CHAN_CONFIG2
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#define CYREG_SAR_CHAN_CONFIG03 CYREG_SAR_CHAN_CONFIG3
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#define CYREG_SAR_CHAN_CONFIG04 CYREG_SAR_CHAN_CONFIG4
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#define CYREG_SAR_CHAN_CONFIG05 CYREG_SAR_CHAN_CONFIG5
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#define CYREG_SAR_CHAN_CONFIG06 CYREG_SAR_CHAN_CONFIG6
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#define CYREG_SAR_CHAN_CONFIG07 CYREG_SAR_CHAN_CONFIG7
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#define CYREG_SAR_CHAN_CONFIG08 CYREG_SAR_CHAN_CONFIG8
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#define CYREG_SAR_CHAN_CONFIG09 CYREG_SAR_CHAN_CONFIG9
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#define CYREG_SAR_CHAN_WORK00 CYREG_SAR_CHAN_WORK0
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#define CYREG_SAR_CHAN_WORK01 CYREG_SAR_CHAN_WORK1
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#define CYREG_SAR_CHAN_WORK02 CYREG_SAR_CHAN_WORK2
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#define CYREG_SAR_CHAN_WORK03 CYREG_SAR_CHAN_WORK3
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#define CYREG_SAR_CHAN_WORK04 CYREG_SAR_CHAN_WORK4
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#define CYREG_SAR_CHAN_WORK05 CYREG_SAR_CHAN_WORK5
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#define CYREG_SAR_CHAN_WORK06 CYREG_SAR_CHAN_WORK6
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#define CYREG_SAR_CHAN_WORK07 CYREG_SAR_CHAN_WORK7
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#define CYREG_SAR_CHAN_WORK08 CYREG_SAR_CHAN_WORK8
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#define CYREG_SAR_CHAN_WORK09 CYREG_SAR_CHAN_WORK9
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#define CYREG_SAR_CHAN_RESULT00 CYREG_SAR_CHAN_RESULT0
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#define CYREG_SAR_CHAN_RESULT01 CYREG_SAR_CHAN_RESULT1
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#define CYREG_SAR_CHAN_RESULT02 CYREG_SAR_CHAN_RESULT2
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#define CYREG_SAR_CHAN_RESULT03 CYREG_SAR_CHAN_RESULT3
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#define CYREG_SAR_CHAN_RESULT04 CYREG_SAR_CHAN_RESULT4
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#define CYREG_SAR_CHAN_RESULT05 CYREG_SAR_CHAN_RESULT5
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#define CYREG_SAR_CHAN_RESULT06 CYREG_SAR_CHAN_RESULT6
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#define CYREG_SAR_CHAN_RESULT07 CYREG_SAR_CHAN_RESULT7
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#define CYREG_SAR_CHAN_RESULT08 CYREG_SAR_CHAN_RESULT8
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#define CYREG_SAR_CHAN_RESULT09 CYREG_SAR_CHAN_RESULT9
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