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#***************************************************************************
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#sjplacer
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#Version: 1.1
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#Build Date: May 8 2015 09:27:37
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#File Generated: May 29 2015 00:00:20
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#Purpose:
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#Copyright (C) 2010-2011 by Softjin Technologies Pvt Ltd. All rights reserved.
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#***************************************************************************
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Executing : C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\bin/sjplacer.exe --proj-name BLE Lab 1_1 --netlist-vh2 BLE Lab 1_1_p.vh2 --arch-file C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\dev/arch/p4_udb2x2.ark --rrg-file C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\dev/psoc4/3/route_arch-rrg.cydata --irq-file C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\dev/psoc4/3/irqconn.cydata --dsi-conn-file C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\dev/psoc4/3/dsiconn.cydata --pins-file pins_56-QFN.xml --lib-file BLE Lab 1_1_p.lib --sdc-file BLE Lab 1_1.sdc --io-pcf BLE Lab 1_1.pci --outdir .
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Softjin Techologies Placer, Version 1.1
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Build Date : May 8 2015 08:51:53
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D2004: Option and Settings Summary
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=============================================================
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Netlist vh2 file - BLE Lab 1_1_p.vh2
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Architecture file - C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\dev/arch/p4_udb2x2.ark
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Package -
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Defparam file -
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SDC file - BLE Lab 1_1.sdc
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Output directory - .
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Timing library - BLE Lab 1_1_p.lib
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IO Placement file - BLE Lab 1_1.pci
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D2050: Starting reading inputs for placer
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=============================================================
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D2065: Reading netlist file : "BLE Lab 1_1_p.vh2"
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D2065: Reading arch file : "C:\Program Files (x86)\Cypress\PSoC Creator\3.2\PSoC Creator\dev/arch/p4_udb2x2.ark"
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D2051: Reading of inputs for placer completed successfully
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D2053: Starting placement of the design
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=============================================================
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Phase 2
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Phase 3
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I2659: No Constrained paths were found. The placer will run in non-timing driven mode.
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Design Statistics after Packing
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Number of Combinational MCs : 0
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Number of Sequential MCs : 0
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Number of DPs : 0
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Number of Controls : 0
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Number of Status : 0
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Number of SyncCells : 0
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Number of count7cells : 0
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Device Utilization Summary after Packing
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Macrocells : 0/32
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UDBS : 0/4
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IOs : 1/38
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D2088: Phase 3, elapsed time : 0.0 (sec)
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Phase 4
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D2088: Phase 4, elapsed time : 0.0 (sec)
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Phase 8
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D2088: Phase 8, elapsed time : 0.0 (sec)
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D2054: Placement of the design completed successfully
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I2076: Total run-time: 0.3 sec.
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