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(DELAYFILE
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(SDFVERSION "IEEE 1497 4.0")
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(DATE "2015-05-28T18:30:21Z")
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(DESIGN "BLE Lab 1_1")
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(VENDOR "Cypress Semiconductor")
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(PROGRAM "PSoC Creator")
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(VERSION " 3.2")
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(DIVIDER .)
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(TIMESCALE 1 ns)
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(CELL
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(CELLTYPE "BLE Lab 1_1")
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(INSTANCE *)
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(DELAY
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(ABSOLUTE
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(INTERCONNECT ClockBlock.hfclk \\BLE\:bless_isr\\.clock (0.000:0.000:0.000))
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(INTERCONNECT ClockBlock.ff_div_7 \\PWM\:cy_m0s8_tcpwm_1\\.clock (0.000:0.000:0.000))
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(INTERCONNECT \\PWM\:cy_m0s8_tcpwm_1\\.line_out_compl Red_LED\(0\).pin_input (2.660:2.660:2.660))
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(INTERCONNECT Red_LED\(0\).pad_out Red_LED\(0\).pad_in (0.000:0.000:0.000))
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(INTERCONNECT \\BLE\:cy_m0s8_ble\\.interrupt \\BLE\:bless_isr\\.interrupt (1.000:1.000:1.000))
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(INTERCONNECT Red_LED\(0\).pad_out Red_LED\(0\)_PAD (0.000:0.000:0.000))
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(INTERCONNECT Red_LED\(0\)_PAD Red_LED\(0\).pad_in (0.000:0.000:0.000))
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)
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)
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)
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)
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