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--
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-- Conversion of BLE Lab 1_1.v to vh2:
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--
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-- Cypress Semiconductor - WARP Version 6.3 IR 41
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-- Fri May 29 00:00:20 2015
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--
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USE cypress.cypress.all;
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USE cypress.rtlpkg.all;
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ENTITY top_RTL IS
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ATTRIBUTE part_name of top_RTL:TYPE IS "cpsoc3";
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END top_RTL;
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--------------------------------------------------------
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ARCHITECTURE R_T_L OF top_RTL IS
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SIGNAL \PWM:Net_81\ : bit;
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SIGNAL \PWM:Net_75\ : bit;
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SIGNAL \PWM:Net_69\ : bit;
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SIGNAL \PWM:Net_66\ : bit;
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SIGNAL \PWM:Net_82\ : bit;
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SIGNAL \PWM:Net_72\ : bit;
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SIGNAL Net_88 : bit;
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SIGNAL Net_87 : bit;
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SIGNAL Net_89 : bit;
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SIGNAL Net_15 : bit;
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SIGNAL Net_94 : bit;
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SIGNAL Net_86 : bit;
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SIGNAL Net_43 : bit;
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SIGNAL tmpOE__Red_LED_net_0 : bit;
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SIGNAL tmpFB_0__Red_LED_net_0 : bit;
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SIGNAL tmpIO_0__Red_LED_net_0 : bit;
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TERMINAL tmpSIOVREF__Red_LED_net_0 : bit;
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SIGNAL zero : bit;
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SIGNAL one : bit;
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SIGNAL tmpINTERRUPT_0__Red_LED_net_0 : bit;
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SIGNAL \BLE:Net_15\ : bit;
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SIGNAL \BLE:Net_53\ : bit;
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SIGNAL Net_97 : bit;
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SIGNAL \BLE:Net_55\ : bit;
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BEGIN
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zero <= ('0') ;
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tmpOE__Red_LED_net_0 <= ('1') ;
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\PWM:cy_m0s8_tcpwm_1\:cy_m0s8_tcpwm_v1_0
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GENERIC MAP(cy_registers=>"")
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PORT MAP(clock=>Net_43,
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capture=>zero,
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count=>tmpOE__Red_LED_net_0,
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reload=>zero,
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stop=>zero,
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start=>zero,
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underflow=>Net_88,
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overflow=>Net_87,
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compare_match=>Net_89,
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line_out=>Net_15,
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line_out_compl=>Net_94,
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interrupt=>Net_86);
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Red_LED:cy_psoc3_pins_v1_10
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GENERIC MAP(id=>"e851a3b9-efb8-48be-bbb8-b303b216c393",
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drive_mode=>"110",
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ibuf_enabled=>"1",
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init_dr_st=>"1",
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input_sync=>"1",
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input_clk_en=>'0',
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input_sync_mode=>"0",
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intr_mode=>"00",
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invert_in_clock=>'0',
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invert_in_clock_en=>'0',
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invert_in_reset=>'0',
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invert_out_clock=>'0',
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invert_out_clock_en=>'0',
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invert_out_reset=>'0',
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io_voltage=>"",
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layout_mode=>"CONTIGUOUS",
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output_conn=>"1",
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output_sync=>"0",
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output_clk_en=>'0',
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output_mode=>"0",
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output_reset=>'0',
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output_clock_mode=>"0",
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oe_sync=>"0",
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oe_conn=>"0",
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oe_reset=>'0',
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pin_aliases=>"",
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pin_mode=>"O",
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por_state=>4,
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sio_group_cnt=>0,
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sio_hifreq=>"",
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sio_hyst=>"1",
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sio_ibuf=>"00000000",
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sio_info=>"00",
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sio_obuf=>"00000000",
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sio_refsel=>"00000000",
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sio_vtrip=>"00000000",
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slew_rate=>"0",
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spanning=>'0',
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sw_only=>'0',
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vtrip=>"10",
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width=>1,
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port_alias_required=>'0',
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port_alias_group=>"",
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use_annotation=>"0",
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pa_in_clock=>-1,
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pa_in_clock_en=>-1,
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pa_in_reset=>-1,
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pa_out_clock=>-1,
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pa_out_clock_en=>-1,
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pa_out_reset=>-1,
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ovt_needed=>"0",
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ovt_slew_control=>"00",
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ovt_hyst_trim=>"0",
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input_buffer_sel=>"00")
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PORT MAP(oe=>(tmpOE__Red_LED_net_0),
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y=>Net_94,
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fb=>(tmpFB_0__Red_LED_net_0),
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analog=>(open),
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io=>(tmpIO_0__Red_LED_net_0),
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siovref=>(tmpSIOVREF__Red_LED_net_0),
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annotation=>(open),
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in_clock=>zero,
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in_clock_en=>tmpOE__Red_LED_net_0,
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in_reset=>zero,
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out_clock=>zero,
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out_clock_en=>tmpOE__Red_LED_net_0,
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out_reset=>zero,
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interrupt=>tmpINTERRUPT_0__Red_LED_net_0);
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Clock_1:cy_clock_v1_0
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GENERIC MAP(cy_registers=>"",
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id=>"502c747e-1e09-4108-bab0-4787f98217a0",
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source_clock_id=>"",
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divisor=>0,
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period=>"1000000000000",
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is_direct=>'0',
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is_digital=>'0')
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PORT MAP(clock_out=>Net_43,
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dig_domain_out=>open);
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\BLE:cy_m0s8_ble\:cy_m0s8_ble_v1_0
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GENERIC MAP(cy_registers=>"")
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PORT MAP(interrupt=>\BLE:Net_15\,
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rf_ext_pa_en=>open);
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\BLE:bless_isr\:cy_isr_v1_0
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GENERIC MAP(int_type=>"10")
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PORT MAP(int_signal=>\BLE:Net_15\);
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\BLE:LFCLK\:cy_clock_v1_0
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GENERIC MAP(cy_registers=>"",
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id=>"7cf87599-d45a-4c9e-b4dc-420f19ab3e2f/5ae6fa4d-f41a-4a35-8821-7ce70389cb0c",
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source_clock_id=>"9A908CA6-5BB3-4db0-B098-959E5D90882B",
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divisor=>0,
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period=>"0",
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is_direct=>'1',
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is_digital=>'0')
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PORT MAP(clock_out=>\BLE:Net_53\,
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dig_domain_out=>open);
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END R_T_L;
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