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/*******************************************************************************
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* File Name: Clock_1.c
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* Version 2.20
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*
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* Description:
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* Provides system API for the clocking, interrupts and watchdog timer.
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*
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* Note:
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* Documentation of the API's in this file is located in the
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* System Reference Guide provided with PSoC Creator.
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*
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********************************************************************************
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* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
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* You may use this file only in accordance with the license, terms, conditions,
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* disclaimers, and limitations in the end user license agreement accompanying
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* the software package with which this file was provided.
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*******************************************************************************/
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#include <cydevice_trm.h>
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#include "Clock_1.h"
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#if defined CYREG_PERI_DIV_CMD
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/*******************************************************************************
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* Function Name: Clock_1_StartEx
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********************************************************************************
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*
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* Summary:
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* Starts the clock, aligned to the specified running clock.
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*
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* Parameters:
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* alignClkDiv: The divider to which phase alignment is performed when the
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* clock is started.
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*
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* Returns:
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* None
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*
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*******************************************************************************/
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void Clock_1_StartEx(uint32 alignClkDiv)
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{
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/* Make sure any previous start command has finished. */
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while((Clock_1_CMD_REG & Clock_1_CMD_ENABLE_MASK) != 0u)
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{
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}
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/* Specify the target divider and it's alignment divider, and enable. */
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Clock_1_CMD_REG =
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((uint32)Clock_1__DIV_ID << Clock_1_CMD_DIV_SHIFT)|
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(alignClkDiv << Clock_1_CMD_PA_DIV_SHIFT) |
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(uint32)Clock_1_CMD_ENABLE_MASK;
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}
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#else
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/*******************************************************************************
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* Function Name: Clock_1_Start
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********************************************************************************
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*
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* Summary:
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* Starts the clock.
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*
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* Parameters:
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* None
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*
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* Returns:
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* None
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*
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*******************************************************************************/
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void Clock_1_Start(void)
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{
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/* Set the bit to enable the clock. */
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Clock_1_ENABLE_REG |= Clock_1__ENABLE_MASK;
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}
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#endif /* CYREG_PERI_DIV_CMD */
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/*******************************************************************************
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* Function Name: Clock_1_Stop
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********************************************************************************
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*
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* Summary:
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* Stops the clock and returns immediately. This API does not require the
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* source clock to be running but may return before the hardware is actually
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* disabled.
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*
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* Parameters:
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* None
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*
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* Returns:
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* None
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*
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*******************************************************************************/
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void Clock_1_Stop(void)
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{
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#if defined CYREG_PERI_DIV_CMD
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/* Make sure any previous start command has finished. */
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while((Clock_1_CMD_REG & Clock_1_CMD_ENABLE_MASK) != 0u)
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{
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}
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/* Specify the target divider and it's alignment divider, and disable. */
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Clock_1_CMD_REG =
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((uint32)Clock_1__DIV_ID << Clock_1_CMD_DIV_SHIFT)|
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((uint32)Clock_1_CMD_DISABLE_MASK);
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#else
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/* Clear the bit to disable the clock. */
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Clock_1_ENABLE_REG &= (uint32)(~Clock_1__ENABLE_MASK);
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#endif /* CYREG_PERI_DIV_CMD */
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}
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/*******************************************************************************
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* Function Name: Clock_1_SetFractionalDividerRegister
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********************************************************************************
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*
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* Summary:
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* Modifies the clock divider and the fractional divider.
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*
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* Parameters:
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* clkDivider: Divider register value (0-65535). This value is NOT the
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* divider; the clock hardware divides by clkDivider plus one. For example,
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* to divide the clock by 2, this parameter should be set to 1.
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* fracDivider: Fractional Divider register value (0-31).
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* Returns:
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* None
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*
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*******************************************************************************/
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void Clock_1_SetFractionalDividerRegister(uint16 clkDivider, uint8 clkFractional)
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{
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uint32 maskVal;
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uint32 regVal;
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#if defined (Clock_1__FRAC_MASK) || defined (CYREG_PERI_DIV_CMD)
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/* get all but divider bits */
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maskVal = Clock_1_DIV_REG &
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(uint32)(~(uint32)(Clock_1_DIV_INT_MASK | Clock_1_DIV_FRAC_MASK));
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/* combine mask and new divider vals into 32-bit value */
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regVal = maskVal |
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((uint32)((uint32)clkDivider << Clock_1_DIV_INT_SHIFT) & Clock_1_DIV_INT_MASK) |
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((uint32)((uint32)clkFractional << Clock_1_DIV_FRAC_SHIFT) & Clock_1_DIV_FRAC_MASK);
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#else
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/* get all but integer divider bits */
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maskVal = Clock_1_DIV_REG & (uint32)(~(uint32)Clock_1__DIVIDER_MASK);
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/* combine mask and new divider val into 32-bit value */
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regVal = clkDivider | maskVal;
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#endif /* Clock_1__FRAC_MASK || CYREG_PERI_DIV_CMD */
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Clock_1_DIV_REG = regVal;
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}
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/*******************************************************************************
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* Function Name: Clock_1_GetDividerRegister
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********************************************************************************
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*
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* Summary:
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* Gets the clock divider register value.
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*
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* Parameters:
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* None
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*
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* Returns:
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* Divide value of the clock minus 1. For example, if the clock is set to
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* divide by 2, the return value will be 1.
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*
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*******************************************************************************/
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uint16 Clock_1_GetDividerRegister(void)
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{
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return (uint16)((Clock_1_DIV_REG & Clock_1_DIV_INT_MASK)
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>> Clock_1_DIV_INT_SHIFT);
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}
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/*******************************************************************************
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* Function Name: Clock_1_GetFractionalDividerRegister
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********************************************************************************
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*
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* Summary:
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* Gets the clock fractional divider register value.
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*
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* Parameters:
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* None
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*
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* Returns:
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* Fractional Divide value of the clock
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* 0 if the fractional divider is not in use.
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*
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*******************************************************************************/
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uint8 Clock_1_GetFractionalDividerRegister(void)
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{
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#if defined (Clock_1__FRAC_MASK)
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/* return fractional divider bits */
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return (uint8)((Clock_1_DIV_REG & Clock_1_DIV_FRAC_MASK)
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>> Clock_1_DIV_FRAC_SHIFT);
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#else
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return 0u;
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#endif /* Clock_1__FRAC_MASK */
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}
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/* [] END OF FILE */
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