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/*******************************************************************************
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* File Name: Clock_1.h
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* Version 2.20
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*
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* Description:
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* Provides the function and constant definitions for the clock component.
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*
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* Note:
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*
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********************************************************************************
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* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
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* You may use this file only in accordance with the license, terms, conditions,
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* disclaimers, and limitations in the end user license agreement accompanying
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* the software package with which this file was provided.
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*******************************************************************************/
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#if !defined(CY_CLOCK_Clock_1_H)
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#define CY_CLOCK_Clock_1_H
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#include <cytypes.h>
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#include <cyfitter.h>
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/***************************************
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* Function Prototypes
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***************************************/
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#if defined CYREG_PERI_DIV_CMD
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void Clock_1_StartEx(uint32 alignClkDiv);
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#define Clock_1_Start() \
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Clock_1_StartEx(Clock_1__PA_DIV_ID)
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#else
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void Clock_1_Start(void);
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#endif/* CYREG_PERI_DIV_CMD */
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void Clock_1_Stop(void);
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void Clock_1_SetFractionalDividerRegister(uint16 clkDivider, uint8 clkFractional);
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uint16 Clock_1_GetDividerRegister(void);
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uint8 Clock_1_GetFractionalDividerRegister(void);
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#define Clock_1_Enable() Clock_1_Start()
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#define Clock_1_Disable() Clock_1_Stop()
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#define Clock_1_SetDividerRegister(clkDivider, reset) \
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Clock_1_SetFractionalDividerRegister((clkDivider), 0u)
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#define Clock_1_SetDivider(clkDivider) Clock_1_SetDividerRegister((clkDivider), 1u)
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#define Clock_1_SetDividerValue(clkDivider) Clock_1_SetDividerRegister((clkDivider) - 1u, 1u)
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/***************************************
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* Registers
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***************************************/
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#if defined CYREG_PERI_DIV_CMD
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#define Clock_1_DIV_ID Clock_1__DIV_ID
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#define Clock_1_CMD_REG (*(reg32 *)CYREG_PERI_DIV_CMD)
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#define Clock_1_CTRL_REG (*(reg32 *)Clock_1__CTRL_REGISTER)
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#define Clock_1_DIV_REG (*(reg32 *)Clock_1__DIV_REGISTER)
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#define Clock_1_CMD_DIV_SHIFT (0u)
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#define Clock_1_CMD_PA_DIV_SHIFT (8u)
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#define Clock_1_CMD_DISABLE_SHIFT (30u)
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#define Clock_1_CMD_ENABLE_SHIFT (31u)
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#define Clock_1_CMD_DISABLE_MASK ((uint32)((uint32)1u << Clock_1_CMD_DISABLE_SHIFT))
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#define Clock_1_CMD_ENABLE_MASK ((uint32)((uint32)1u << Clock_1_CMD_ENABLE_SHIFT))
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#define Clock_1_DIV_FRAC_MASK (0x000000F8u)
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#define Clock_1_DIV_FRAC_SHIFT (3u)
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#define Clock_1_DIV_INT_MASK (0xFFFFFF00u)
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#define Clock_1_DIV_INT_SHIFT (8u)
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#else
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#define Clock_1_DIV_REG (*(reg32 *)Clock_1__REGISTER)
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#define Clock_1_ENABLE_REG Clock_1_DIV_REG
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#define Clock_1_DIV_FRAC_MASK Clock_1__FRAC_MASK
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#define Clock_1_DIV_FRAC_SHIFT (16u)
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#define Clock_1_DIV_INT_MASK Clock_1__DIVIDER_MASK
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#define Clock_1_DIV_INT_SHIFT (0u)
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#endif/* CYREG_PERI_DIV_CMD */
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#endif /* !defined(CY_CLOCK_Clock_1_H) */
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/* [] END OF FILE */
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