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/*******************************************************************************
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* File Name: CyLib.h
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* Version 5.0
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*
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* Description:
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*
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* Note:
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* Documentation of the API's in this file is located in the
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* System Reference Guide provided with PSoC Creator.
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*
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********************************************************************************
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* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
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* You may use this file only in accordance with the license, terms, conditions,
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* disclaimers, and limitations in the end user license agreement accompanying
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* the software package with which this file was provided.
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*******************************************************************************/
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#if !defined(CY_BOOT_CYLIB_H)
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#define CY_BOOT_CYLIB_H
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#include "cytypes.h"
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#include "cydevice_trm.h"
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#include "CyLFClk.h"
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#include <string.h>
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#include <limits.h>
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#include <ctype.h>
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/***************************************
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* Function Prototypes
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***************************************/
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/* Clocks API */
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void CySysClkImoStart(void);
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void CySysClkImoStop(void);
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void CySysClkWriteHfclkDirect(uint32 clkSelect);
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#if (CY_PSOC4_4100M || CY_PSOC4_4200M)
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void CySysClkImoEnableWcoLock(void);
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void CySysClkImoDisableWcoLock(void);
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#endif /* (CY_PSOC4_4100M || CY_PSOC4_4200M) */
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#if !(CY_PSOC4_4100 || CY_PSOC4_4200)
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void CySysClkWriteHfclkDiv(uint32 divider);
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#endif /* !(CY_PSOC4_4100 || CY_PSOC4_4200) */
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void CySysClkWriteSysclkDiv(uint32 divider);
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void CySysClkWriteImoFreq(uint32 freq);
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#if (CY_PSOC4_4100BL || CY_PSOC4_4200BL)
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void CySysClkWriteEcoDiv(uint32 divider);
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#endif /* (CY_PSOC4_4100BL || CY_PSOC4_4200BL) */
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#if(CY_IP_SRSSV2)
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/* Low Voltage Detection */
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void CySysLvdEnable(uint32 threshold);
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void CySysLvdDisable(void);
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uint32 CySysLvdGetInterruptSource(void);
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void CySysLvdClearInterrupt(void);
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#endif /* (CY_IP_SRSSV2) */
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/* Interrupt Function Prototypes */
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cyisraddress CyIntSetSysVector(uint8 number, cyisraddress address);
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cyisraddress CyIntGetSysVector(uint8 number);
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cyisraddress CyIntSetVector(uint8 number, cyisraddress address);
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cyisraddress CyIntGetVector(uint8 number);
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void CyIntSetPriority(uint8 number, uint8 priority);
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uint8 CyIntGetPriority(uint8 number);
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void CyIntEnable(uint8 number);
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uint8 CyIntGetState(uint8 number);
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void CyIntDisable(uint8 number);
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void CyIntSetPending(uint8 number);
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void CyIntClearPending(uint8 number);
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uint32 CyDisableInts(void);
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void CyEnableInts(uint32 mask);
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/* System Function Prototypes */
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void CyDelay(uint32 milliseconds);
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void CyDelayUs(uint16 microseconds);
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void CyDelayFreq(uint32 freq);
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void CyDelayCycles(uint32 cycles);
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/* General APIs */
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void CySoftwareReset(void);
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uint8 CyEnterCriticalSection(void);
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void CyExitCriticalSection(uint8 savedIntrStatus);
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void CyHalt(uint8 reason);
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uint32 CySysGetResetReason(uint32 reason);
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/* Default interrupt handler */
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CY_ISR_PROTO(IntDefaultHandler);
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/* System tick timer APIs */
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typedef void (*cySysTickCallback)(void);
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void CySysTickStart(void);
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void CySysTickInit(void);
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void CySysTickEnable(void);
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void CySysTickStop(void);
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void CySysTickEnableInterrupt(void);
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void CySysTickDisableInterrupt(void);
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void CySysTickSetReload(uint32 value);
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uint32 CySysTickGetReload(void);
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uint32 CySysTickGetValue(void);
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cySysTickCallback CySysTickSetCallback(uint32 number, cySysTickCallback function);
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cySysTickCallback CySysTickGetCallback(uint32 number);
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#if(!CY_PSOC3 && !CY_PSOC4_4000 && !CY_PSOC4_4100 && !CY_PSOC4_4200)
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void CySysTickSetClockSource(uint32 clockSource);
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#endif /* (!CY_PSOC3 && !CY_PSOC4_4000 && !CY_PSOC4_4100 && !CY_PSOC4_4200) */
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uint32 CySysTickGetCountFlag(void);
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void CySysTickClear(void);
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extern uint32 CySysTickInitVar;
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/* Do not use these definitions directly in your application */
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extern uint32 cydelayFreqHz;
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extern uint32 cydelayFreqKhz;
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extern uint8 cydelayFreqMhz;
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extern uint32 cydelay32kMs;
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#if (CY_PSOC4_4100BL || CY_PSOC4_4200BL)
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cystatus CySysClkEcoStart(uint32 timeoutUs);
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void CySysClkEcoStop(void);
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uint32 CySysClkEcoReadStatus(void);
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#endif /* (CY_PSOC4_4100BL || CY_PSOC4_4200BL) */
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void CyGetUniqueId(uint32* uniqueId);
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/***************************************
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* API Constants
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***************************************/
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/*******************************************************************************
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* Clock API Constants
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*******************************************************************************/
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/* CySysClkWriteHfclkDirect() - implementation definitions */
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#if(CY_IP_SRSSV2)
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#define CY_SYS_CLK_SELECT_DIRECT_SEL_MASK (( uint32 ) 0x07u)
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#if (CY_PSOC4_4100BL || CY_PSOC4_4200BL)
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/* The ECO is the valid option */
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#define CY_SYS_CLK_SELECT_DIRECT_SEL_PARAM_MASK (( uint32 ) 0x03u)
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#else
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#define CY_SYS_CLK_SELECT_DIRECT_SEL_PARAM_MASK (( uint32 ) 0x01u)
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#endif /* (CY_PSOC4_4100BL || CY_PSOC4_4200BL) */
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#else
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#define CY_SYS_CLK_SELECT_DIRECT_SEL_MASK (( uint32 ) 0x03u)
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#define CY_SYS_CLK_SELECT_DIRECT_SEL_PARAM_MASK (CY_SYS_CLK_SELECT_DIRECT_SEL_MASK)
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#endif /* (CY_IP_SRSSV2) */
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/* CySysClkWriteHfclkDirect() - parameter definitions */
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#define CY_SYS_CLK_HFCLK_IMO (0u)
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#define CY_SYS_CLK_HFCLK_EXTCLK (1u)
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#if (CY_PSOC4_4100BL || CY_PSOC4_4200BL)
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#define CY_SYS_CLK_HFCLK_ECO (2u)
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#endif /* (CY_PSOC4_4100BL || CY_PSOC4_4200BL) */
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/* CySysClkWriteSysclkDiv() - parameter definitions */
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#define CY_SYS_CLK_SYSCLK_DIV1 (0u)
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#define CY_SYS_CLK_SYSCLK_DIV2 (1u)
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#define CY_SYS_CLK_SYSCLK_DIV4 (2u)
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#define CY_SYS_CLK_SYSCLK_DIV8 (3u)
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#if(CY_IP_SRSSV2)
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#define CY_SYS_CLK_SYSCLK_DIV16 (4u)
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#define CY_SYS_CLK_SYSCLK_DIV32 (5u)
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#define CY_SYS_CLK_SYSCLK_DIV64 (6u)
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#define CY_SYS_CLK_SYSCLK_DIV128 (7u)
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#endif /* (CY_IP_SRSSV2) */
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/* CySysClkWriteSysclkDiv() - implementation definitions */
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#if(CY_IP_SRSSV2)
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#define CY_SYS_CLK_SELECT_SYSCLK_DIV_SHIFT (19u)
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#define CY_SYS_CLK_SELECT_SYSCLK_DIV_MASK (( uint32 )0x07u)
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#else
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#define CY_SYS_CLK_SELECT_SYSCLK_DIV_SHIFT (6u)
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#define CY_SYS_CLK_SELECT_SYSCLK_DIV_MASK (( uint32 )0x03u)
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#endif /* (CY_IP_SRSSV2) */
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/* CySysClkWriteImoFreq() - implementation definitions */
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#if(CY_IP_SRSSV2)
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#define CY_SYS_CLK_IMO_MAX_FREQ_MHZ (48u)
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#define CY_SYS_CLK_IMO_MIN_FREQ_MHZ (3u)
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#define CY_SYS_CLK_IMO_TEMP_FREQ_MHZ (24u)
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#define CY_SYS_CLK_IMO_TEMP_FREQ_TRIM2 (0x19u) /* Corresponds to 24 MHz */
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#define CY_SYS_CLK_IMO_BOUNDARY_FREQ_MHZ (43u)
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#define CY_SYS_CLK_IMO_BOUNDARY_FREQ_TRIM2 (0x30u) /* Corresponds to 43 MHz */
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#define CY_SYS_CLK_IMO_FREQ_TIMEOUT_CYCLES (5u)
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#define CY_SYS_CLK_IMO_TRIM_TIMEOUT_US (5u)
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#define CY_SYS_CLK_IMO_FREQ_TABLE_SIZE (46u)
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#define CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET (3u)
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#define CY_SYS_CLK_IMO_FREQ_BITS_MASK (( uint32 )0x3Fu)
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#define CY_SYS_CLK_IMO_FREQ_CLEAR (( uint32 )(CY_SYS_CLK_IMO_FREQ_BITS_MASK << 8u))
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#define CY_SYS_CLK_IMO_TRIM4_GAIN_MASK (( uint32 )0x1Fu)
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#define CY_SYS_CLK_IMO_TRIM4_GAIN (( uint32 ) 12u)
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#else
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#define CY_SYS_CLK_IMO_MIN_FREQ_MHZ (24u)
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#define CY_SYS_CLK_IMO_MAX_FREQ_MHZ (48u)
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#define CY_SYS_CLK_IMO_STEP_SIZE_MASK (0x03u)
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#define CY_SYS_CLK_IMO_TRIM1_OFFSET_MASK (( uint32 )(0xFFu))
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#define CY_SYS_CLK_IMO_TRIM2_FSOFFSET_MASK (( uint32 )(0x07u))
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#define CY_SYS_CLK_IMO_TRIM3_VALUES_MASK (( uint32 )(0x7Fu))
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#define CY_SYS_CLK_IMO_SELECT_FREQ_MASK (( uint32 )(0x07u))
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#define CY_SYS_CLK_IMO_SELECT_24MHZ (( uint32 )(0x00u))
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#define CY_SYS_CLK_IMO_TRIM_DELAY_US (( uint32 )(50u))
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#endif /* (CY_IP_SRSSV2) */
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#if(CY_IP_SRSSV2)
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/* Conversion between CySysClkWriteImoFreq() parameter and register's value */
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extern const uint8 cyImoFreqMhz2Reg[CY_SYS_CLK_IMO_FREQ_TABLE_SIZE];
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#endif /* (CY_IP_SRSSV2) */
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/* CySysClkImoStart()/CySysClkImoStop() - implementation definitions */
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#define CY_SYS_CLK_IMO_CONFIG_ENABLE (( uint32 )(( uint32 )0x01u << 31u))
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#if(CY_IP_SRSSLT)
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/* CySysClkWriteHfclkDiv() - parameter definitions */
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#define CY_SYS_CLK_HFCLK_DIV_NODIV (0u)
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#define CY_SYS_CLK_HFCLK_DIV_2 (1u)
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#define CY_SYS_CLK_HFCLK_DIV_4 (2u)
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#define CY_SYS_CLK_HFCLK_DIV_8 (3u)
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/* CySysClkWriteHfclkDiv() - implementation definitions */
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#define CY_SYS_CLK_SELECT_HFCLK_DIV_SHIFT (2u)
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#define CY_SYS_CLK_SELECT_HFCLK_DIV_MASK (( uint32 )0x03u)
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#endif /* (CY_IP_SRSSLT) */
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/* Operating source for Pump clock */
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#if(CY_IP_SRSSV2)
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#define CY_SYS_CLK_IMO_CONFIG_PUMP_SEL_SHIFT (25u)
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#define CY_SYS_CLK_IMO_CONFIG_PUMP_SEL_MASK ((uint32) 0x07u)
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#define CY_SYS_CLK_IMO_CONFIG_PUMP_SEL_IMO (1u)
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#define CY_SYS_CLK_IMO_CONFIG_PUMP_OSC (( uint32 )(( uint32 )0x01u << 22u))
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#else /* CY_IP_SRSSLT */
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#define CY_SYS_CLK_SELECT_PUMP_SEL_SHIFT (4u)
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#define CY_SYS_CLK_SELECT_PUMP_SEL_MASK ((uint32) 0x03u)
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#define CY_SYS_CLK_SELECT_PUMP_SEL_IMO (1u)
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#endif /* (CY_IP_SRSSLT) */
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#if (CY_PSOC4_4100BL || CY_PSOC4_4200BL)
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/* Radio configuration register */
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#define CY_SYS_XTAL_BLESS_RF_CONFIG_RF_ENABLE (( uint32 )0x01u)
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/* RFCTRL mode transition control */
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#define CY_SYS_XTAL_BLERD_DBUS_XTAL_ENABLE (( uint32 )(( uint32 )0x01u << 15u))
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/* XO is oscillating status */
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#define CY_SYS_XTAL_BLERD_FSM_XO_AMP_DETECT (( uint32 )0x01u)
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/* BB bump configuration 2 */
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#define CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_X1_MASK (( uint32 )(( uint32 )0x7Fu << 8u))
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#define CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_X2_MASK (( uint32 )(( uint32 )0x7Fu << 0u))
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#define CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_X1_ADD_CAP (( uint32 )(( uint32 )0x01u << 15u))
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#define CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_X2_ADD_CAP (( uint32 )(( uint32 )0x01u << 7u))
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/* BB bump configuration 1 */
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#define CY_SYS_XTAL_BLERD_BB_XO_TRIM ((uint32) 0x2002u)
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/* CySysClkWriteEcoDiv() - parameter definitions */
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#define CY_SYS_CLK_ECO_DIV1 ((uint32) 0x00)
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#define CY_SYS_CLK_ECO_DIV2 ((uint32) 0x01)
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#define CY_SYS_CLK_ECO_DIV4 ((uint32) 0x02)
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#define CY_SYS_CLK_ECO_DIV8 ((uint32) 0x03)
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/* CySysClkWriteEcoDiv() - implementation definitions */
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#define CY_SYS_CLK_XTAL_CLK_DIV_MASK ((uint32) 0x03)
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#endif /* (CY_PSOC4_4100BL || CY_PSOC4_4200BL) */
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/* CySysClkImoEnableWcoLock() / CySysClkImoDisableWcoLock() constants */
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#if (CY_PSOC4_4100M || CY_PSOC4_4200M)
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/* Fimo = DPLL_MULT * Fwco */
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#define CY_SYS_CLK_WCO_CONFIG_DPLL_ENABLE (( uint32 )(( uint32 )0x01u << 30u))
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/* Rounding integer division: DPLL_MULT = (Fimo_in_khz + Fwco_in_khz / 2) / Fwco_in_khz */
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#define CY_SYS_CLK_WCO_DPLL_MULT_VALUE(frequencyMhz) ((uint32) (((((frequencyMhz) * 1000000u) + 16384u) / 32768u) - 1u))
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#define CY_SYS_CLK_WCO_DPLL_MULT_MASK ((uint32) 0x7FFu)
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#define CY_SYS_CLK_WCO_CONFIG_DPLL_LF_IGAIN_SHIFT (16u)
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#define CY_SYS_CLK_WCO_CONFIG_DPLL_LF_PGAIN_SHIFT (19u)
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#define CY_SYS_CLK_WCO_CONFIG_DPLL_LF_IGAIN_MASK (( uint32 )(( uint32 )0x07u << CY_SYS_CLK_WCO_CONFIG_DPLL_LF_IGAIN_SHIFT))
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#define CY_SYS_CLK_WCO_CONFIG_DPLL_LF_PGAIN_MASK (( uint32 )(( uint32 )0x07u << CY_SYS_CLK_WCO_CONFIG_DPLL_LF_PGAIN_SHIFT))
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#define CY_SYS_CLK_WCO_CONFIG_DPLL_LF_IGAIN (( uint32 )(( uint32 ) 4u << CY_SYS_CLK_WCO_CONFIG_DPLL_LF_IGAIN_SHIFT))
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#define CY_SYS_CLK_WCO_CONFIG_DPLL_LF_PGAIN (( uint32 )(( uint32 ) 2u << CY_SYS_CLK_WCO_CONFIG_DPLL_LF_PGAIN_SHIFT))
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#endif /* (CY_PSOC4_4100M || CY_PSOC4_4200M) */
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/*******************************************************************************
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* System API Constants
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*******************************************************************************/
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/* CySysGetResetReason() */
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#define CY_SYS_RESET_WDT_SHIFT (0u)
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#define CY_SYS_RESET_PROTFAULT_SHIFT (3u)
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#define CY_SYS_RESET_SW_SHIFT (4u)
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#define CY_SYS_RESET_WDT ((uint32)1u << CY_SYS_RESET_WDT_SHIFT )
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#define CY_SYS_RESET_PROTFAULT ((uint32)1u << CY_SYS_RESET_PROTFAULT_SHIFT)
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#define CY_SYS_RESET_SW ((uint32)1u << CY_SYS_RESET_SW_SHIFT )
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/* CySoftwareReset() - implementation definitions */
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/* Vector Key */
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#define CY_SYS_CM0_AIRCR_VECTKEY_SHIFT (16u)
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#define CY_SYS_CM0_AIRCR_VECTKEY ((uint32)((uint32)0x05FAu << CY_SYS_CM0_AIRCR_VECTKEY_SHIFT))
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#define CY_SYS_CM0_AIRCR_VECTKEY_MASK ((uint32)((uint32)0xFFFFu << CY_SYS_CM0_AIRCR_VECTKEY_SHIFT))
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/* System Reset Request */
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#define CY_SYS_CM0_AIRCR_SYSRESETREQ_SHIFT (2u)
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#define CY_SYS_CM0_AIRCR_SYSRESETREQ ((uint32)((uint32)1u << CY_SYS_CM0_AIRCR_SYSRESETREQ_SHIFT))
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#if defined(__ARMCC_VERSION)
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#define CyGlobalIntEnable do \
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{ \
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__enable_irq(); \
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} while ( 0 )
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#define CyGlobalIntDisable do \
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{ \
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__disable_irq(); \
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} while ( 0 )
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#elif defined(__GNUC__) || defined (__ICCARM__)
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#define CyGlobalIntEnable do \
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{ \
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__asm("CPSIE i"); \
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} while ( 0 )
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#define CyGlobalIntDisable do \
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{ \
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__asm("CPSID i"); \
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} while ( 0 )
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#else
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#error No compiler toolchain defined
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#define CyGlobalIntEnable
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#define CyGlobalIntDisable
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#endif /* (__ARMCC_VERSION) */
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/* System tick timer */
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#define CY_SYS_SYST_CSR_ENABLE ((uint32) (0x01u))
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#define CY_SYS_SYST_CSR_ENABLE_INT ((uint32) (0x02u))
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#define CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT (0x02u)
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#define CY_SYS_SYST_CSR_COUNTFLAG_SHIFT (16u)
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#define CY_SYS_SYST_CSR_CLK_SRC_SYSCLK ((uint32) (1u))
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#define CY_SYS_SYST_CSR_CLK_SRC_LFCLK (0u)
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#define CY_SYS_SYST_RVR_CNT_MASK (0x00FFFFFFu)
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#define CY_SYS_SYST_CVR_CNT_MASK (0x00FFFFFFu)
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#define CY_SYS_SYST_NUM_OF_CALLBACKS (5u)
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/*******************************************************************************
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* Macro Name: CyAssert
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********************************************************************************
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* Summary:
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* Macro that evaluates the expression and, if it is false (evaluates to 0),
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* the processor is halted.
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*
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* This macro is evaluated unless NDEBUG is defined.
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* If NDEBUG is defined, then no code is generated for this macro.
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* NDEBUG is defined by default for a Release build setting and not defined for
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* a Debug build setting.
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*
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* Parameters:
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* expr: Logical expression. Asserts if false.
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*
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* Return:
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* None
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*
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*******************************************************************************/
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#if !defined(NDEBUG)
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#define CYASSERT(x) do \
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{ \
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if(0u == (x)) \
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{ \
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CyHalt((uint8) 0u); \
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} \
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} while ( 0u )
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#else
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#define CYASSERT(x)
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#endif /* !defined(NDEBUG) */
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/*******************************************************************************
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* Interrupt API Constants
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*******************************************************************************/
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#define CY_NUM_INTERRUPTS (CY_IP_INT_NR)
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#define CY_MIN_PRIORITY (3u)
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#define CY_INT_IRQ_BASE (16u)
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#define CY_INT_CLEAR_DISABLE_ALL (0xFFFFFFFFu)
|
|
#define CY_INT_ENABLE_RANGE_MASK (0x1Fu)
|
|
|
|
/* Register n contains priorities for interrupts N=4n .. 4n+3 */
|
|
#define CY_INT_PRIORITY_SHIFT(number) (( uint32 )6u + (8u * (( uint32 )(number) % 4u)))
|
|
|
|
/* Mask to get valid range of system priority 0-3 */
|
|
#define CY_INT_PRIORITY_MASK (( uint32 ) 0x03u)
|
|
|
|
/* CyIntSetSysVector()/CyIntGetSysVector() - parameter definitions */
|
|
#define CY_INT_NMI_IRQN ( 2u) /* Non Maskable Interrupt */
|
|
#define CY_INT_HARD_FAULT_IRQN ( 3u) /* Hard Fault Interrupt */
|
|
#define CY_INT_SVCALL_IRQN (11u) /* SV Call Interrupt */
|
|
#define CY_INT_PEND_SV_IRQN (14u) /* Pend SV Interrupt */
|
|
#define CY_INT_SYSTICK_IRQN (15u) /* System Tick Interrupt */
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|
|
|
|
#if(CY_IP_SRSSV2)
|
|
|
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|
|
/*******************************************************************************
|
|
* Low Voltage Detection API Constants
|
|
*******************************************************************************/
|
|
|
|
/* CySysLvdEnable() - parameter definitions */
|
|
#define CY_LVD_THRESHOLD_1_75_V (( uint32 ) 0u)
|
|
#define CY_LVD_THRESHOLD_1_80_V (( uint32 ) 1u)
|
|
#define CY_LVD_THRESHOLD_1_90_V (( uint32 ) 2u)
|
|
#define CY_LVD_THRESHOLD_2_00_V (( uint32 ) 3u)
|
|
#define CY_LVD_THRESHOLD_2_10_V (( uint32 ) 4u)
|
|
#define CY_LVD_THRESHOLD_2_20_V (( uint32 ) 5u)
|
|
#define CY_LVD_THRESHOLD_2_30_V (( uint32 ) 6u)
|
|
#define CY_LVD_THRESHOLD_2_40_V (( uint32 ) 7u)
|
|
#define CY_LVD_THRESHOLD_2_50_V (( uint32 ) 8u)
|
|
#define CY_LVD_THRESHOLD_2_60_V (( uint32 ) 9u)
|
|
#define CY_LVD_THRESHOLD_2_70_V (( uint32 ) 10u)
|
|
#define CY_LVD_THRESHOLD_2_80_V (( uint32 ) 11u)
|
|
#define CY_LVD_THRESHOLD_2_90_V (( uint32 ) 12u)
|
|
#define CY_LVD_THRESHOLD_3_00_V (( uint32 ) 13u)
|
|
#define CY_LVD_THRESHOLD_3_20_V (( uint32 ) 14u)
|
|
#define CY_LVD_THRESHOLD_4_50_V (( uint32 ) 15u)
|
|
|
|
/* CySysLvdEnable() - implementation definitions */
|
|
#define CY_LVD_PWR_VMON_CONFIG_LVD_EN (( uint32 ) 0x01u)
|
|
#define CY_LVD_PWR_VMON_CONFIG_LVD_SEL_SHIFT (1u)
|
|
#define CY_LVD_PWR_VMON_CONFIG_LVD_SEL_MASK (( uint32 ) (0x0F << CY_LVD_PWR_VMON_CONFIG_LVD_SEL_SHIFT))
|
|
#define CY_LVD_PROPAGATE_INT_TO_CPU (( uint32 ) 0x02u)
|
|
#define CY_LVD_STABILIZE_TIMEOUT_US (1000u)
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|
|
/* CySysLvdGetInterruptSource()/ CySysLvdClearInterrupt() - parameter definitions */
|
|
#define CY_SYS_LVD_INT (( uint32 ) 0x02u)
|
|
#endif /* (CY_IP_SRSSV2) */
|
|
|
|
/* CyDelay()/CyDelayFreq() - implementation definitions */
|
|
#define CY_DELAY_MS_OVERFLOW (0x8000u)
|
|
#define CY_DELAY_1M_THRESHOLD (1000000u)
|
|
#define CY_DELAY_1M_MINUS_1_THRESHOLD (999999u)
|
|
#define CY_DELAY_1K_THRESHOLD (1000u)
|
|
#define CY_DELAY_1K_MINUS_1_THRESHOLD (999u)
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|
|
|
|
/***************************************
|
|
* Registers
|
|
***************************************/
|
|
|
|
|
|
/*******************************************************************************
|
|
* Clocks API Registers
|
|
*******************************************************************************/
|
|
#define CY_SYS_CLK_IMO_TRIM1_REG (*(reg32 *) CYREG_CLK_IMO_TRIM1)
|
|
#define CY_SYS_CLK_IMO_TRIM1_PTR ( (reg32 *) CYREG_CLK_IMO_TRIM1)
|
|
|
|
#define CY_SYS_CLK_IMO_TRIM2_REG (*(reg32 *) CYREG_CLK_IMO_TRIM2)
|
|
#define CY_SYS_CLK_IMO_TRIM2_PTR ( (reg32 *) CYREG_CLK_IMO_TRIM2)
|
|
|
|
#define CY_SYS_CLK_IMO_TRIM3_REG (*(reg32 *) CYREG_CLK_IMO_TRIM3)
|
|
#define CY_SYS_CLK_IMO_TRIM3_PTR ( (reg32 *) CYREG_CLK_IMO_TRIM3)
|
|
|
|
#define CY_SYS_CLK_IMO_TRIM4_REG (*(reg32 *) CYREG_CLK_IMO_TRIM4)
|
|
#define CY_SYS_CLK_IMO_TRIM4_PTR ( (reg32 *) CYREG_CLK_IMO_TRIM4)
|
|
|
|
#define CY_SYS_CLK_IMO_CONFIG_REG (*(reg32 *) CYREG_CLK_IMO_CONFIG)
|
|
#define CY_SYS_CLK_IMO_CONFIG_PTR ( (reg32 *) CYREG_CLK_IMO_CONFIG)
|
|
|
|
|
|
#define CY_SYS_CLK_SELECT_REG (*(reg32 *) CYREG_CLK_SELECT)
|
|
#define CY_SYS_CLK_SELECT_PTR ( (reg32 *) CYREG_CLK_SELECT)
|
|
|
|
#if(CY_IP_SRSSV2)
|
|
|
|
|
|
#if(CY_PSOC4_4100 || CY_PSOC4_4200)
|
|
#define CY_SFLASH_IMO_TRIM_REG(number) ( ((reg8 *) CYREG_SFLASH_IMO_TRIM00)[number])
|
|
#define CY_SFLASH_IMO_TRIM_PTR(number) (&((reg8 *) CYREG_SFLASH_IMO_TRIM00)[number])
|
|
#else
|
|
#define CY_SFLASH_IMO_TRIM_REG(number) ( ((reg8 *) CYREG_SFLASH_IMO_TRIM0)[number])
|
|
#define CY_SFLASH_IMO_TRIM_PTR(number) (&((reg8 *) CYREG_SFLASH_IMO_TRIM0)[number])
|
|
#endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */
|
|
|
|
#define CY_SFLASH_IMO_MAXF0_REG (*(reg8 *) CYREG_SFLASH_IMO_MAXF0)
|
|
#define CY_SFLASH_IMO_MAXF0_PTR ( (reg8 *) CYREG_SFLASH_IMO_MAXF0)
|
|
|
|
#define CY_SFLASH_IMO_ABS0_REG (*(reg8 *) CYREG_SFLASH_IMO_ABS0)
|
|
#define CY_SFLASH_IMO_ABS0_PTR ( (reg8 *) CYREG_SFLASH_IMO_ABS0)
|
|
|
|
#define CY_SFLASH_IMO_TMPCO0_REG (*(reg8 *) CYREG_SFLASH_IMO_TMPCO0)
|
|
#define CY_SFLASH_IMO_TMPCO0_PTR ( (reg8 *) CYREG_SFLASH_IMO_TMPCO0)
|
|
|
|
#define CY_SFLASH_IMO_MAXF1_REG (*(reg8 *) CYREG_SFLASH_IMO_MAXF1)
|
|
#define CY_SFLASH_IMO_MAXF1_PTR ( (reg8 *) CYREG_SFLASH_IMO_MAXF1)
|
|
|
|
#define CY_SFLASH_IMO_ABS1_REG (*(reg8 *) CYREG_SFLASH_IMO_ABS1)
|
|
#define CY_SFLASH_IMO_ABS1_PTR ( (reg8 *) CYREG_SFLASH_IMO_ABS1)
|
|
|
|
#define CY_SFLASH_IMO_TMPCO1_REG (*(reg8 *) CYREG_SFLASH_IMO_TMPCO1)
|
|
#define CY_SFLASH_IMO_TMPCO1_PTR ( (reg8 *) CYREG_SFLASH_IMO_TMPCO1)
|
|
|
|
#define CY_SFLASH_IMO_MAXF2_REG (*(reg8 *) CYREG_SFLASH_IMO_MAXF2)
|
|
#define CY_SFLASH_IMO_MAXF2_PTR ( (reg8 *) CYREG_SFLASH_IMO_MAXF2)
|
|
|
|
#define CY_SFLASH_IMO_ABS2_REG (*(reg8 *) CYREG_SFLASH_IMO_ABS2)
|
|
#define CY_SFLASH_IMO_ABS2_PTR ( (reg8 *) CYREG_SFLASH_IMO_ABS2)
|
|
|
|
#define CY_SFLASH_IMO_TMPCO2_REG (*(reg8 *) CYREG_SFLASH_IMO_TMPCO2)
|
|
#define CY_SFLASH_IMO_TMPCO2_PTR ( (reg8 *) CYREG_SFLASH_IMO_TMPCO2)
|
|
|
|
#define CY_SFLASH_IMO_MAXF3_REG (*(reg8 *) CYREG_SFLASH_IMO_MAXF3)
|
|
#define CY_SFLASH_IMO_MAXF3_PTR ( (reg8 *) CYREG_SFLASH_IMO_MAXF3)
|
|
|
|
#define CY_SFLASH_IMO_ABS3_REG (*(reg8 *) CYREG_SFLASH_IMO_ABS3)
|
|
#define CY_SFLASH_IMO_ABS3_PTR ( (reg8 *) CYREG_SFLASH_IMO_ABS3)
|
|
|
|
#define CY_SFLASH_IMO_TMPCO3_REG (*(reg8 *) CYREG_SFLASH_IMO_TMPCO3)
|
|
#define CY_SFLASH_IMO_TMPCO3_PTR ( (reg8 *) CYREG_SFLASH_IMO_TMPCO3)
|
|
|
|
#define CY_SFLASH_IMO_ABS4_REG (*(reg8 *) CYREG_SFLASH_IMO_ABS4)
|
|
#define CY_SFLASH_IMO_ABS4_PTR ( (reg8 *) CYREG_SFLASH_IMO_ABS4)
|
|
|
|
#define CY_SFLASH_IMO_TMPCO4_REG (*(reg8 *) CYREG_SFLASH_IMO_TMPCO4)
|
|
#define CY_SFLASH_IMO_TMPCO4_PTR ( (reg8 *) CYREG_SFLASH_IMO_TMPCO4)
|
|
|
|
#define CY_PWR_BG_TRIM4_REG (*(reg32 *) CYREG_PWR_BG_TRIM4)
|
|
#define CY_PWR_BG_TRIM4_PTR ( (reg32 *) CYREG_PWR_BG_TRIM4)
|
|
|
|
#define CY_PWR_BG_TRIM5_REG (*(reg32 *) CYREG_PWR_BG_TRIM5)
|
|
#define CY_PWR_BG_TRIM5_PTR ( (reg32 *) CYREG_PWR_BG_TRIM5)
|
|
|
|
#else
|
|
|
|
#define CY_SYS_CLK_IMO_SELECT_REG (*(reg32 *) CYREG_CLK_IMO_SELECT)
|
|
#define CY_SYS_CLK_IMO_SELECT_PTR ( (reg32 *) CYREG_CLK_IMO_SELECT)
|
|
|
|
#define CY_SFLASH_IMO_TCTRIM_REG(number) ( ((reg8 *) CYREG_SFLASH_IMO_TCTRIM_LT0)[number])
|
|
#define CY_SFLASH_IMO_TCTRIM_PTR(number) (&((reg8 *) CYREG_SFLASH_IMO_TCTRIM_LT0)[number])
|
|
|
|
#define CY_SFLASH_IMO_TRIM_REG(number) ( ((reg8 *) CYREG_SFLASH_IMO_TRIM_LT0)[number])
|
|
#define CY_SFLASH_IMO_TRIM_PTR(number) (&((reg8 *) CYREG_SFLASH_IMO_TRIM_LT0)[number])
|
|
|
|
#endif /* (CY_IP_SRSSV2) */
|
|
|
|
|
|
#if (CY_PSOC4_4100BL || CY_PSOC4_4200BL)
|
|
/* Radio configuration register */
|
|
#define CY_SYS_XTAL_BLESS_RF_CONFIG_REG (*(reg32 *) CYREG_BLE_BLESS_RF_CONFIG)
|
|
#define CY_SYS_XTAL_BLESS_RF_CONFIG_PTR ( (reg32 *) CYREG_BLE_BLESS_RF_CONFIG)
|
|
|
|
/* RFCTRL mode transition control */
|
|
#define CY_SYS_XTAL_BLERD_DBUS_REG (*(reg32 *) CYREG_BLE_BLERD_DBUS)
|
|
#define CY_SYS_XTAL_BLERD_DBUS_PTR ( (reg32 *) CYREG_BLE_BLERD_DBUS)
|
|
|
|
/* RFCTRL state information */
|
|
#define CY_SYS_XTAL_BLERD_FSM_REG (*(reg32 *) CYREG_BLE_BLERD_FSM)
|
|
#define CY_SYS_XTAL_BLERD_FSM_PTR ( (reg32 *) CYREG_BLE_BLERD_FSM)
|
|
|
|
/* BB bump configuration 1 */
|
|
#define CY_SYS_XTAL_BLERD_BB_XO_REG (*(reg32 *) CYREG_BLE_BLERD_BB_XO)
|
|
#define CY_SYS_XTAL_BLERD_BB_XO_PTR ( (reg32 *) CYREG_BLE_BLERD_BB_XO)
|
|
|
|
/* BB bump configuration 2 */
|
|
#define CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_REG (*(reg32 *) CYREG_BLE_BLERD_BB_XO_CAPTRIM)
|
|
#define CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_PTR ( (reg32 *) CYREG_BLE_BLERD_BB_XO_CAPTRIM)
|
|
|
|
/* Crystal clock divider configuration register */
|
|
#define CY_SYS_CLK_XTAL_CLK_DIV_CONFIG_REG (*(reg32 *) CYREG_BLE_BLESS_XTAL_CLK_DIV_CONFIG)
|
|
#define CY_SYS_CLK_XTAL_CLK_DIV_CONFIG_PTR ( (reg32 *) CYREG_BLE_BLESS_XTAL_CLK_DIV_CONFIG)
|
|
#endif /* (CY_PSOC4_4100BL || CY_PSOC4_4200BL) */
|
|
|
|
|
|
/* CySysClkImoEnableWcoLock() / CySysClkImoDisableWcoLock() registers */
|
|
#if (CY_PSOC4_4100M || CY_PSOC4_4200M)
|
|
/* WCO DPLL Register */
|
|
#define CY_SYS_CLK_WCO_DPLL_REG (*(reg32 *) CYREG_WCO_DPLL)
|
|
#define CY_SYS_CLK_WCO_DPLL_PTR ( (reg32 *) CYREG_WCO_DPLL)
|
|
#endif /* (CY_PSOC4_4100M || CY_PSOC4_4200M) */
|
|
|
|
|
|
/*******************************************************************************
|
|
* System API Registers
|
|
*******************************************************************************/
|
|
#define CY_SYS_CM0_AIRCR_REG (*(reg32 *) CYREG_CM0_AIRCR)
|
|
#define CY_SYS_CM0_AIRCR_PTR ( (reg32 *) CYREG_CM0_AIRCR)
|
|
|
|
/* Reset Cause Observation Register */
|
|
#define CY_SYS_RES_CAUSE_REG (*(reg32 *) CYREG_RES_CAUSE)
|
|
#define CY_SYS_RES_CAUSE_PTR ( (reg32 *) CYREG_RES_CAUSE)
|
|
|
|
#if(CY_IP_SRSSV2)
|
|
|
|
/*******************************************************************************
|
|
* Low Voltage Detection
|
|
*******************************************************************************/
|
|
|
|
/* Voltage Monitoring Trim and Configuration */
|
|
#define CY_LVD_PWR_VMON_CONFIG_REG (*(reg32 *) CYREG_PWR_VMON_CONFIG)
|
|
#define CY_LVD_PWR_VMON_CONFIG_PTR ( (reg32 *) CYREG_PWR_VMON_CONFIG)
|
|
|
|
/* Power System Interrupt Mask Register */
|
|
#define CY_LVD_PWR_INTR_MASK_REG (*(reg32 *) CYREG_PWR_INTR_MASK)
|
|
#define CY_LVD_PWR_INTR_MASK_PTR ( (reg32 *) CYREG_PWR_INTR_MASK)
|
|
|
|
/* Power System Interrupt Register */
|
|
#define CY_LVD_PWR_INTR_REG (*(reg32 *) CYREG_PWR_INTR)
|
|
#define CY_LVD_PWR_INTR_PTR ( (reg32 *) CYREG_PWR_INTR)
|
|
|
|
#endif /* (CY_IP_SRSSV2) */
|
|
|
|
|
|
/*******************************************************************************
|
|
* Interrupt API Registers
|
|
*******************************************************************************/
|
|
#define CY_INT_VECT_TABLE ( (cyisraddress **) CYDEV_SRAM_BASE)
|
|
|
|
#define CY_INT_PRIORITY_REG(number) ( ((reg32 *) CYREG_CM0_IPR0)[(number)/4u])
|
|
#define CY_INT_PRIORITY_PTR(number) (&((reg32 *) CYREG_CM0_IPR0)[(number)/4u])
|
|
|
|
#define CY_INT_ENABLE_REG (*(reg32 *) CYREG_CM0_ISER)
|
|
#define CY_INT_ENABLE_PTR ( (reg32 *) CYREG_CM0_ISER)
|
|
|
|
#define CY_INT_CLEAR_REG (*(reg32 *) CYREG_CM0_ICER)
|
|
#define CY_INT_CLEAR_PTR ( (reg32 *) CYREG_CM0_ICER)
|
|
|
|
#define CY_INT_SET_PEND_REG (*(reg32 *) CYREG_CM0_ISPR)
|
|
#define CY_INT_SET_PEND_PTR ( (reg32 *) CYREG_CM0_ISPR)
|
|
|
|
#define CY_INT_CLR_PEND_REG (*(reg32 *) CYREG_CM0_ICPR)
|
|
#define CY_INT_CLR_PEND_PTR ( (reg32 *) CYREG_CM0_ICPR)
|
|
|
|
|
|
/*******************************************************************************
|
|
* System tick API Registers
|
|
*******************************************************************************/
|
|
#define CY_SYS_SYST_CSR_REG (*(reg32 *) CYREG_CM0_SYST_CSR)
|
|
#define CY_SYS_SYST_CSR_PTR ( (reg32 *) CYREG_CM0_SYST_CSR)
|
|
|
|
#define CY_SYS_SYST_RVR_REG (*(reg32 *) CYREG_CM0_SYST_RVR)
|
|
#define CY_SYS_SYST_RVR_PTR ( (reg32 *) CYREG_CM0_SYST_RVR)
|
|
|
|
#define CY_SYS_SYST_CVR_REG (*(reg32 *) CYREG_CM0_SYST_CVR)
|
|
#define CY_SYS_SYST_CVR_PTR ( (reg32 *) CYREG_CM0_SYST_CVR)
|
|
|
|
#define CY_SYS_SYST_CALIB_REG (*(reg32 *) CYREG_CM0_SYST_CALIB)
|
|
#define CY_SYS_SYST_CALIB_PTR ( (reg32 *) CYREG_CM0_SYST_CALIB)
|
|
|
|
|
|
|
|
|
|
/*******************************************************************************
|
|
* The following code is OBSOLETE and must not be used.
|
|
*
|
|
* If the obsoleted macro definitions are intended for use in the application,
|
|
* use the following scheme, redefine your own versions of these definitions:
|
|
* #ifdef <OBSOLETED_DEFINE>
|
|
* #undef <OBSOLETED_DEFINE>
|
|
* #define <OBSOLETED_DEFINE> (<New Value>)
|
|
* #endif
|
|
*
|
|
* Note: Redefine obsoleted macro definitions with caution. They might still be
|
|
* used in the application and their modification might lead to unexpected
|
|
* consequences.
|
|
*******************************************************************************/
|
|
#define CYINT_IRQ_BASE (CY_INT_IRQ_BASE)
|
|
|
|
/* SFLASH0 block has been renamed to SFLASH */
|
|
#if (CY_PSOC4_4100 || CY_PSOC4_4200)
|
|
#if !defined(CYREG_SFLASH_IMO_TRIM21)
|
|
#define CYREG_SFLASH_IMO_TRIM21 (CYREG_SFLASH0_IMO_TRIM21)
|
|
#endif /* !defined(CYREG_SFLASH_IMO_TRIM21) */
|
|
#endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */
|
|
|
|
#endif /* CY_BOOT_CYLIB_H */
|
|
|
|
|
|
/* [] END OF FILE */
|