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#ifndef INCLUDED_CYFITTER_H
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#define INCLUDED_CYFITTER_H
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#include "cydevice_trm.h"
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/* BLE_bless_isr */
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#define BLE_bless_isr__INTC_CLR_EN_REG CYREG_CM0_ICER
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#define BLE_bless_isr__INTC_CLR_PD_REG CYREG_CM0_ICPR
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#define BLE_bless_isr__INTC_MASK 0x1000u
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#define BLE_bless_isr__INTC_NUMBER 12u
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#define BLE_bless_isr__INTC_PRIOR_MASK 0xC0u
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#define BLE_bless_isr__INTC_PRIOR_NUM 3u
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#define BLE_bless_isr__INTC_PRIOR_REG CYREG_CM0_IPR3
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#define BLE_bless_isr__INTC_SET_EN_REG CYREG_CM0_ISER
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#define BLE_bless_isr__INTC_SET_PD_REG CYREG_CM0_ISPR
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/* BLE_cy_m0s8_ble */
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#define BLE_cy_m0s8_ble__ADC_BUMP1 CYREG_BLE_BLERD_ADC_BUMP1
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#define BLE_cy_m0s8_ble__ADC_BUMP2 CYREG_BLE_BLERD_ADC_BUMP2
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#define BLE_cy_m0s8_ble__ADV_CH_TX_POWER CYREG_BLE_BLELL_ADV_CH_TX_POWER
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#define BLE_cy_m0s8_ble__ADV_CONFIG CYREG_BLE_BLELL_ADV_CONFIG
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#define BLE_cy_m0s8_ble__ADV_INTERVAL_TIMEOUT CYREG_BLE_BLELL_ADV_INTERVAL_TIMEOUT
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#define BLE_cy_m0s8_ble__ADV_INTR CYREG_BLE_BLELL_ADV_INTR
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#define BLE_cy_m0s8_ble__ADV_NEXT_INSTANT CYREG_BLE_BLELL_ADV_NEXT_INSTANT
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#define BLE_cy_m0s8_ble__ADV_PARAMS CYREG_BLE_BLELL_ADV_PARAMS
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#define BLE_cy_m0s8_ble__ADV_SCN_RSP_TX_FIFO CYREG_BLE_BLELL_ADV_SCN_RSP_TX_FIFO
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#define BLE_cy_m0s8_ble__ADV_TX_DATA_FIFO CYREG_BLE_BLELL_ADV_TX_DATA_FIFO
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#define BLE_cy_m0s8_ble__AGC CYREG_BLE_BLERD_AGC
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#define BLE_cy_m0s8_ble__BALUN CYREG_BLE_BLERD_BALUN
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#define BLE_cy_m0s8_ble__BB_BUMP1 CYREG_BLE_BLERD_BB_BUMP1
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#define BLE_cy_m0s8_ble__BB_BUMP2 CYREG_BLE_BLERD_BB_BUMP2
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#define BLE_cy_m0s8_ble__BB_XO CYREG_BLE_BLERD_BB_XO
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#define BLE_cy_m0s8_ble__BB_XO_CAPTRIM CYREG_BLE_BLERD_BB_XO_CAPTRIM
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#define BLE_cy_m0s8_ble__CE_CNFG_STS_REGISTER CYREG_BLE_BLELL_CE_CNFG_STS_REGISTER
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#define BLE_cy_m0s8_ble__CE_LENGTH CYREG_BLE_BLELL_CE_LENGTH
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#define BLE_cy_m0s8_ble__CFG_1_FCAL CYREG_BLE_BLERD_CFG_1_FCAL
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#define BLE_cy_m0s8_ble__CFG_2_FCAL CYREG_BLE_BLERD_CFG_2_FCAL
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#define BLE_cy_m0s8_ble__CFG_3_FCAL CYREG_BLE_BLERD_CFG_3_FCAL
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#define BLE_cy_m0s8_ble__CFG_4_FCAL CYREG_BLE_BLERD_CFG_4_FCAL
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#define BLE_cy_m0s8_ble__CFG_5_FCAL CYREG_BLE_BLERD_CFG_5_FCAL
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#define BLE_cy_m0s8_ble__CFG_6_FCAL CYREG_BLE_BLERD_CFG_6_FCAL
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#define BLE_cy_m0s8_ble__CFG1 CYREG_BLE_BLERD_CFG1
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#define BLE_cy_m0s8_ble__CFG2 CYREG_BLE_BLERD_CFG2
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#define BLE_cy_m0s8_ble__CFGCTRL CYREG_BLE_BLERD_CFGCTRL
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#define BLE_cy_m0s8_ble__CLOCK_CONFIG CYREG_BLE_BLELL_CLOCK_CONFIG
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#define BLE_cy_m0s8_ble__COMMAND_REGISTER CYREG_BLE_BLELL_COMMAND_REGISTER
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#define BLE_cy_m0s8_ble__CONN_CE_COUNTER CYREG_BLE_BLELL_CONN_CE_COUNTER
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#define BLE_cy_m0s8_ble__CONN_CE_INSTANT CYREG_BLE_BLELL_CONN_CE_INSTANT
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#define BLE_cy_m0s8_ble__CONN_CH_TX_POWER CYREG_BLE_BLELL_CONN_CH_TX_POWER
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#define BLE_cy_m0s8_ble__CONN_CONFIG CYREG_BLE_BLELL_CONN_CONFIG
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#define BLE_cy_m0s8_ble__CONN_INDEX CYREG_BLE_BLELL_CONN_INDEX
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#define BLE_cy_m0s8_ble__CONN_INTERVAL CYREG_BLE_BLELL_CONN_INTERVAL
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#define BLE_cy_m0s8_ble__CONN_INTR CYREG_BLE_BLELL_CONN_INTR
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#define BLE_cy_m0s8_ble__CONN_INTR_MASK CYREG_BLE_BLELL_CONN_INTR_MASK
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#define BLE_cy_m0s8_ble__CONN_PARAM1 CYREG_BLE_BLELL_CONN_PARAM1
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#define BLE_cy_m0s8_ble__CONN_PARAM2 CYREG_BLE_BLELL_CONN_PARAM2
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#define BLE_cy_m0s8_ble__CONN_REQ_WORD0 CYREG_BLE_BLELL_CONN_REQ_WORD0
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#define BLE_cy_m0s8_ble__CONN_REQ_WORD1 CYREG_BLE_BLELL_CONN_REQ_WORD1
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#define BLE_cy_m0s8_ble__CONN_REQ_WORD10 CYREG_BLE_BLELL_CONN_REQ_WORD10
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#define BLE_cy_m0s8_ble__CONN_REQ_WORD11 CYREG_BLE_BLELL_CONN_REQ_WORD11
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#define BLE_cy_m0s8_ble__CONN_REQ_WORD2 CYREG_BLE_BLELL_CONN_REQ_WORD2
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#define BLE_cy_m0s8_ble__CONN_REQ_WORD3 CYREG_BLE_BLELL_CONN_REQ_WORD3
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#define BLE_cy_m0s8_ble__CONN_REQ_WORD4 CYREG_BLE_BLELL_CONN_REQ_WORD4
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#define BLE_cy_m0s8_ble__CONN_REQ_WORD5 CYREG_BLE_BLELL_CONN_REQ_WORD5
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#define BLE_cy_m0s8_ble__CONN_REQ_WORD6 CYREG_BLE_BLELL_CONN_REQ_WORD6
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#define BLE_cy_m0s8_ble__CONN_REQ_WORD7 CYREG_BLE_BLELL_CONN_REQ_WORD7
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#define BLE_cy_m0s8_ble__CONN_REQ_WORD8 CYREG_BLE_BLELL_CONN_REQ_WORD8
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#define BLE_cy_m0s8_ble__CONN_REQ_WORD9 CYREG_BLE_BLELL_CONN_REQ_WORD9
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#define BLE_cy_m0s8_ble__CONN_RXMEM_BASE_ADDR CYREG_BLE_BLELL_CONN_RXMEM_BASE_ADDR
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#define BLE_cy_m0s8_ble__CONN_STATUS CYREG_BLE_BLELL_CONN_STATUS
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#define BLE_cy_m0s8_ble__CONN_TXMEM_BASE_ADDR CYREG_BLE_BLELL_CONN_TXMEM_BASE_ADDR
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#define BLE_cy_m0s8_ble__CONN_UPDATE_NEW_INTERVAL CYREG_BLE_BLELL_CONN_UPDATE_NEW_INTERVAL
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#define BLE_cy_m0s8_ble__CONN_UPDATE_NEW_LATENCY CYREG_BLE_BLELL_CONN_UPDATE_NEW_LATENCY
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#define BLE_cy_m0s8_ble__CONN_UPDATE_NEW_SL_INTERVAL CYREG_BLE_BLELL_CONN_UPDATE_NEW_SL_INTERVAL
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#define BLE_cy_m0s8_ble__CONN_UPDATE_NEW_SUP_TO CYREG_BLE_BLELL_CONN_UPDATE_NEW_SUP_TO
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#define BLE_cy_m0s8_ble__CTR1 CYREG_BLE_BLERD_CTR1
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#define BLE_cy_m0s8_ble__DATA_CHANNELS_H0 CYREG_BLE_BLELL_DATA_CHANNELS_H0
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#define BLE_cy_m0s8_ble__DATA_CHANNELS_H1 CYREG_BLE_BLELL_DATA_CHANNELS_H1
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#define BLE_cy_m0s8_ble__DATA_CHANNELS_L0 CYREG_BLE_BLELL_DATA_CHANNELS_L0
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#define BLE_cy_m0s8_ble__DATA_CHANNELS_L1 CYREG_BLE_BLELL_DATA_CHANNELS_L1
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#define BLE_cy_m0s8_ble__DATA_CHANNELS_M0 CYREG_BLE_BLELL_DATA_CHANNELS_M0
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#define BLE_cy_m0s8_ble__DATA_CHANNELS_M1 CYREG_BLE_BLELL_DATA_CHANNELS_M1
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#define BLE_cy_m0s8_ble__DATA_LIST_ACK_UPDATE__STATUS CYREG_BLE_BLELL_DATA_LIST_ACK_UPDATE__STATUS
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#define BLE_cy_m0s8_ble__DATA_LIST_SENT_UPDATE__STATUS CYREG_BLE_BLELL_DATA_LIST_SENT_UPDATE__STATUS
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#define BLE_cy_m0s8_ble__DATA_MEM_DESCRIPTOR0 CYREG_BLE_BLELL_DATA_MEM_DESCRIPTOR0
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#define BLE_cy_m0s8_ble__DATA_MEM_DESCRIPTOR1 CYREG_BLE_BLELL_DATA_MEM_DESCRIPTOR1
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#define BLE_cy_m0s8_ble__DATA_MEM_DESCRIPTOR2 CYREG_BLE_BLELL_DATA_MEM_DESCRIPTOR2
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#define BLE_cy_m0s8_ble__DATA_MEM_DESCRIPTOR3 CYREG_BLE_BLELL_DATA_MEM_DESCRIPTOR3
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#define BLE_cy_m0s8_ble__DATA_MEM_DESCRIPTOR4 CYREG_BLE_BLELL_DATA_MEM_DESCRIPTOR4
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#define BLE_cy_m0s8_ble__DATA0 CYREG_BLE_BLELL_DATA0
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#define BLE_cy_m0s8_ble__DATA1 CYREG_BLE_BLELL_DATA1
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#define BLE_cy_m0s8_ble__DATA10 CYREG_BLE_BLELL_DATA10
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#define BLE_cy_m0s8_ble__DATA11 CYREG_BLE_BLELL_DATA11
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#define BLE_cy_m0s8_ble__DATA12 CYREG_BLE_BLELL_DATA12
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#define BLE_cy_m0s8_ble__DATA13 CYREG_BLE_BLELL_DATA13
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#define BLE_cy_m0s8_ble__DATA2 CYREG_BLE_BLELL_DATA2
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#define BLE_cy_m0s8_ble__DATA3 CYREG_BLE_BLELL_DATA3
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#define BLE_cy_m0s8_ble__DATA4 CYREG_BLE_BLELL_DATA4
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#define BLE_cy_m0s8_ble__DATA5 CYREG_BLE_BLELL_DATA5
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#define BLE_cy_m0s8_ble__DATA6 CYREG_BLE_BLELL_DATA6
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#define BLE_cy_m0s8_ble__DATA7 CYREG_BLE_BLELL_DATA7
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#define BLE_cy_m0s8_ble__DATA8 CYREG_BLE_BLELL_DATA8
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#define BLE_cy_m0s8_ble__DATA9 CYREG_BLE_BLELL_DATA9
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#define BLE_cy_m0s8_ble__DBG_1 CYREG_BLE_BLERD_DBG_1
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#define BLE_cy_m0s8_ble__DBG_2 CYREG_BLE_BLERD_DBG_2
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#define BLE_cy_m0s8_ble__DBG_3 CYREG_BLE_BLERD_DBG_3
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#define BLE_cy_m0s8_ble__DBG_BB CYREG_BLE_BLERD_DBG_BB
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#define BLE_cy_m0s8_ble__DBUS CYREG_BLE_BLERD_DBUS
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#define BLE_cy_m0s8_ble__DC CYREG_BLE_BLERD_DC
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#define BLE_cy_m0s8_ble__DCCAL CYREG_BLE_BLERD_DCCAL
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#define BLE_cy_m0s8_ble__DEV_PUB_ADDR_H CYREG_BLE_BLELL_DEV_PUB_ADDR_H
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#define BLE_cy_m0s8_ble__DEV_PUB_ADDR_L CYREG_BLE_BLELL_DEV_PUB_ADDR_L
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#define BLE_cy_m0s8_ble__DEV_PUB_ADDR_M CYREG_BLE_BLELL_DEV_PUB_ADDR_M
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#define BLE_cy_m0s8_ble__DEVICE_RAND_ADDR_H CYREG_BLE_BLELL_DEVICE_RAND_ADDR_H
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#define BLE_cy_m0s8_ble__DEVICE_RAND_ADDR_L CYREG_BLE_BLELL_DEVICE_RAND_ADDR_L
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#define BLE_cy_m0s8_ble__DEVICE_RAND_ADDR_M CYREG_BLE_BLELL_DEVICE_RAND_ADDR_M
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#define BLE_cy_m0s8_ble__DIAG1 CYREG_BLE_BLERD_DIAG1
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#define BLE_cy_m0s8_ble__DPLL_CONFIG CYREG_BLE_BLELL_DPLL_CONFIG
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#define BLE_cy_m0s8_ble__DSM1 CYREG_BLE_BLERD_DSM1
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#define BLE_cy_m0s8_ble__DSM2 CYREG_BLE_BLERD_DSM2
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#define BLE_cy_m0s8_ble__DSM3 CYREG_BLE_BLERD_DSM3
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#define BLE_cy_m0s8_ble__DSM4 CYREG_BLE_BLERD_DSM4
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#define BLE_cy_m0s8_ble__DSM5 CYREG_BLE_BLERD_DSM5
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#define BLE_cy_m0s8_ble__DSM6 CYREG_BLE_BLERD_DSM6
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#define BLE_cy_m0s8_ble__DTM_RX_PKT_COUNT CYREG_BLE_BLELL_DTM_RX_PKT_COUNT
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#define BLE_cy_m0s8_ble__ENC_CONFIG CYREG_BLE_BLELL_ENC_CONFIG
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#define BLE_cy_m0s8_ble__ENC_INTR CYREG_BLE_BLELL_ENC_INTR
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#define BLE_cy_m0s8_ble__ENC_INTR_EN CYREG_BLE_BLELL_ENC_INTR_EN
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#define BLE_cy_m0s8_ble__ENC_KEY0 CYREG_BLE_BLELL_ENC_KEY0
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#define BLE_cy_m0s8_ble__ENC_KEY1 CYREG_BLE_BLELL_ENC_KEY1
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#define BLE_cy_m0s8_ble__ENC_KEY2 CYREG_BLE_BLELL_ENC_KEY2
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#define BLE_cy_m0s8_ble__ENC_KEY3 CYREG_BLE_BLELL_ENC_KEY3
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#define BLE_cy_m0s8_ble__ENC_KEY4 CYREG_BLE_BLELL_ENC_KEY4
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#define BLE_cy_m0s8_ble__ENC_KEY5 CYREG_BLE_BLELL_ENC_KEY5
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#define BLE_cy_m0s8_ble__ENC_KEY6 CYREG_BLE_BLELL_ENC_KEY6
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#define BLE_cy_m0s8_ble__ENC_KEY7 CYREG_BLE_BLELL_ENC_KEY7
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#define BLE_cy_m0s8_ble__ENC_PARAMS CYREG_BLE_BLELL_ENC_PARAMS
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#define BLE_cy_m0s8_ble__EVENT_ENABLE CYREG_BLE_BLELL_EVENT_ENABLE
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#define BLE_cy_m0s8_ble__EVENT_INTR CYREG_BLE_BLELL_EVENT_INTR
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#define BLE_cy_m0s8_ble__FCAL_TEST CYREG_BLE_BLERD_FCAL_TEST
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#define BLE_cy_m0s8_ble__FPD_TEST CYREG_BLE_BLERD_FPD_TEST
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#define BLE_cy_m0s8_ble__FSM CYREG_BLE_BLERD_FSM
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#define BLE_cy_m0s8_ble__IM CYREG_BLE_BLERD_IM
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#define BLE_cy_m0s8_ble__INIT_CONFIG CYREG_BLE_BLELL_INIT_CONFIG
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#define BLE_cy_m0s8_ble__INIT_INTERVAL CYREG_BLE_BLELL_INIT_INTERVAL
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#define BLE_cy_m0s8_ble__INIT_INTR CYREG_BLE_BLELL_INIT_INTR
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#define BLE_cy_m0s8_ble__INIT_NEXT_INSTANT CYREG_BLE_BLELL_INIT_NEXT_INSTANT
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#define BLE_cy_m0s8_ble__INIT_PARAM CYREG_BLE_BLELL_INIT_PARAM
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#define BLE_cy_m0s8_ble__INIT_SCN_ADV_RX_FIFO CYREG_BLE_BLELL_INIT_SCN_ADV_RX_FIFO
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#define BLE_cy_m0s8_ble__INIT_WINDOW CYREG_BLE_BLELL_INIT_WINDOW
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#define BLE_cy_m0s8_ble__IQMIS CYREG_BLE_BLERD_IQMIS
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#define BLE_cy_m0s8_ble__IV_MASTER0 CYREG_BLE_BLELL_IV_MASTER0
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#define BLE_cy_m0s8_ble__IV_MASTER1 CYREG_BLE_BLELL_IV_MASTER1
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#define BLE_cy_m0s8_ble__IV_SLAVE0 CYREG_BLE_BLELL_IV_SLAVE0
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#define BLE_cy_m0s8_ble__IV_SLAVE1 CYREG_BLE_BLELL_IV_SLAVE1
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#define BLE_cy_m0s8_ble__KVCAL CYREG_BLE_BLERD_KVCAL
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#define BLE_cy_m0s8_ble__LDO CYREG_BLE_BLERD_LDO
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#define BLE_cy_m0s8_ble__LDO_BYPASS CYREG_BLE_BLERD_LDO_BYPASS
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#define BLE_cy_m0s8_ble__LE_PING_TIMER_ADDR CYREG_BLE_BLELL_LE_PING_TIMER_ADDR
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#define BLE_cy_m0s8_ble__LE_PING_TIMER_NEXT_EXP CYREG_BLE_BLELL_LE_PING_TIMER_NEXT_EXP
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#define BLE_cy_m0s8_ble__LE_PING_TIMER_OFFSET CYREG_BLE_BLELL_LE_PING_TIMER_OFFSET
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#define BLE_cy_m0s8_ble__LE_PING_TIMER_WRAP_COUNT CYREG_BLE_BLELL_LE_PING_TIMER_WRAP_COUNT
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#define BLE_cy_m0s8_ble__LE_RF_TEST_MODE CYREG_BLE_BLELL_LE_RF_TEST_MODE
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#define BLE_cy_m0s8_ble__LF_CLK_CTRL CYREG_BLE_BLESS_LF_CLK_CTRL
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#define BLE_cy_m0s8_ble__LL_CLK_EN CYREG_BLE_BLESS_LL_CLK_EN
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#define BLE_cy_m0s8_ble__LL_DSM_CTRL CYREG_BLE_BLESS_LL_DSM_CTRL
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#define BLE_cy_m0s8_ble__LL_DSM_INTR_STAT CYREG_BLE_BLESS_LL_DSM_INTR_STAT
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#define BLE_cy_m0s8_ble__LLH_FEATURE_CONFIG CYREG_BLE_BLELL_LLH_FEATURE_CONFIG
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#define BLE_cy_m0s8_ble__MIC_IN0 CYREG_BLE_BLELL_MIC_IN0
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#define BLE_cy_m0s8_ble__MIC_IN1 CYREG_BLE_BLELL_MIC_IN1
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#define BLE_cy_m0s8_ble__MIC_OUT0 CYREG_BLE_BLELL_MIC_OUT0
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#define BLE_cy_m0s8_ble__MIC_OUT1 CYREG_BLE_BLELL_MIC_OUT1
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#define BLE_cy_m0s8_ble__MODEM CYREG_BLE_BLERD_MODEM
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#define BLE_cy_m0s8_ble__MONI CYREG_BLE_BLERD_MONI
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#define BLE_cy_m0s8_ble__NEXT_CE_INSTANT CYREG_BLE_BLELL_NEXT_CE_INSTANT
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#define BLE_cy_m0s8_ble__NEXT_RESP_TIMER_EXP CYREG_BLE_BLELL_NEXT_RESP_TIMER_EXP
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#define BLE_cy_m0s8_ble__NEXT_SUP_TO CYREG_BLE_BLELL_NEXT_SUP_TO
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#define BLE_cy_m0s8_ble__OFFSET_TO_FIRST_INSTANT CYREG_BLE_BLELL_OFFSET_TO_FIRST_INSTANT
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#define BLE_cy_m0s8_ble__PACKET_COUNTER0 CYREG_BLE_BLELL_PACKET_COUNTER0
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#define BLE_cy_m0s8_ble__PACKET_COUNTER1 CYREG_BLE_BLELL_PACKET_COUNTER1
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#define BLE_cy_m0s8_ble__PACKET_COUNTER2 CYREG_BLE_BLELL_PACKET_COUNTER2
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#define BLE_cy_m0s8_ble__PDU_ACCESS_ADDR_H_REGISTER CYREG_BLE_BLELL_PDU_ACCESS_ADDR_H_REGISTER
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#define BLE_cy_m0s8_ble__PDU_ACCESS_ADDR_L_REGISTER CYREG_BLE_BLELL_PDU_ACCESS_ADDR_L_REGISTER
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#define BLE_cy_m0s8_ble__PDU_RESP_TIMER CYREG_BLE_BLELL_PDU_RESP_TIMER
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#define BLE_cy_m0s8_ble__PEER_ADDR_H CYREG_BLE_BLELL_PEER_ADDR_H
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#define BLE_cy_m0s8_ble__PEER_ADDR_L CYREG_BLE_BLELL_PEER_ADDR_L
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#define BLE_cy_m0s8_ble__PEER_ADDR_M CYREG_BLE_BLELL_PEER_ADDR_M
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#define BLE_cy_m0s8_ble__POC_REG__TIM_CONTROL CYREG_BLE_BLELL_POC_REG__TIM_CONTROL
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#define BLE_cy_m0s8_ble__RCCAL CYREG_BLE_BLERD_RCCAL
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#define BLE_cy_m0s8_ble__READ_IQ_1 CYREG_BLE_BLERD_READ_IQ_1
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#define BLE_cy_m0s8_ble__READ_IQ_2 CYREG_BLE_BLERD_READ_IQ_2
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#define BLE_cy_m0s8_ble__READ_IQ_3 CYREG_BLE_BLERD_READ_IQ_3
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#define BLE_cy_m0s8_ble__READ_IQ_4 CYREG_BLE_BLERD_READ_IQ_4
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#define BLE_cy_m0s8_ble__RECEIVE_TRIG_CTRL CYREG_BLE_BLELL_RECEIVE_TRIG_CTRL
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#define BLE_cy_m0s8_ble__RF_CONFIG CYREG_BLE_BLESS_RF_CONFIG
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#define BLE_cy_m0s8_ble__RMAP CYREG_BLE_BLERD_RMAP
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#define BLE_cy_m0s8_ble__RSSI CYREG_BLE_BLERD_RSSI
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#define BLE_cy_m0s8_ble__RX CYREG_BLE_BLERD_RX
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#define BLE_cy_m0s8_ble__RX_BUMP1 CYREG_BLE_BLERD_RX_BUMP1
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#define BLE_cy_m0s8_ble__RX_BUMP2 CYREG_BLE_BLERD_RX_BUMP2
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#define BLE_cy_m0s8_ble__SCAN_CONFIG CYREG_BLE_BLELL_SCAN_CONFIG
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#define BLE_cy_m0s8_ble__SCAN_INTERVAL CYREG_BLE_BLELL_SCAN_INTERVAL
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#define BLE_cy_m0s8_ble__SCAN_INTR CYREG_BLE_BLELL_SCAN_INTR
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#define BLE_cy_m0s8_ble__SCAN_NEXT_INSTANT CYREG_BLE_BLELL_SCAN_NEXT_INSTANT
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#define BLE_cy_m0s8_ble__SCAN_PARAM CYREG_BLE_BLELL_SCAN_PARAM
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#define BLE_cy_m0s8_ble__SCAN_WINDOW CYREG_BLE_BLELL_SCAN_WINDOW
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#define BLE_cy_m0s8_ble__SL_CONN_INTERVAL CYREG_BLE_BLELL_SL_CONN_INTERVAL
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#define BLE_cy_m0s8_ble__SLAVE_LATENCY CYREG_BLE_BLELL_SLAVE_LATENCY
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#define BLE_cy_m0s8_ble__SLAVE_TIMING_CONTROL CYREG_BLE_BLELL_SLAVE_TIMING_CONTROL
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#define BLE_cy_m0s8_ble__SLV_WIN_ADJ CYREG_BLE_BLELL_SLV_WIN_ADJ
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#define BLE_cy_m0s8_ble__SUP_TIMEOUT CYREG_BLE_BLELL_SUP_TIMEOUT
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#define BLE_cy_m0s8_ble__SY CYREG_BLE_BLERD_SY
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#define BLE_cy_m0s8_ble__SY_BUMP1 CYREG_BLE_BLERD_SY_BUMP1
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#define BLE_cy_m0s8_ble__SY_BUMP2 CYREG_BLE_BLERD_SY_BUMP2
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#define BLE_cy_m0s8_ble__TEST CYREG_BLE_BLERD_TEST
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#define BLE_cy_m0s8_ble__TEST2_SY CYREG_BLE_BLERD_TEST2_SY
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#define BLE_cy_m0s8_ble__THRSHD1 CYREG_BLE_BLERD_THRSHD1
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#define BLE_cy_m0s8_ble__THRSHD2 CYREG_BLE_BLERD_THRSHD2
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#define BLE_cy_m0s8_ble__THRSHD3 CYREG_BLE_BLERD_THRSHD3
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#define BLE_cy_m0s8_ble__THRSHD4 CYREG_BLE_BLERD_THRSHD4
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#define BLE_cy_m0s8_ble__THRSHD5 CYREG_BLE_BLERD_THRSHD5
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#define BLE_cy_m0s8_ble__TIM_COUNTER_L CYREG_BLE_BLELL_TIM_COUNTER_L
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#define BLE_cy_m0s8_ble__TRANSMIT_WINDOW_OFFSET CYREG_BLE_BLELL_TRANSMIT_WINDOW_OFFSET
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#define BLE_cy_m0s8_ble__TRANSMIT_WINDOW_SIZE CYREG_BLE_BLELL_TRANSMIT_WINDOW_SIZE
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#define BLE_cy_m0s8_ble__TX CYREG_BLE_BLERD_TX
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#define BLE_cy_m0s8_ble__TX_BUMP1 CYREG_BLE_BLERD_TX_BUMP1
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#define BLE_cy_m0s8_ble__TX_BUMP2 CYREG_BLE_BLERD_TX_BUMP2
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#define BLE_cy_m0s8_ble__TX_EN_EXT_DELAY CYREG_BLE_BLELL_TX_EN_EXT_DELAY
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#define BLE_cy_m0s8_ble__TX_RX_ON_DELAY CYREG_BLE_BLELL_TX_RX_ON_DELAY
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#define BLE_cy_m0s8_ble__TX_RX_SYNTH_DELAY CYREG_BLE_BLELL_TX_RX_SYNTH_DELAY
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#define BLE_cy_m0s8_ble__TXRX_HOP CYREG_BLE_BLELL_TXRX_HOP
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#define BLE_cy_m0s8_ble__WAKEUP_CONFIG CYREG_BLE_BLELL_WAKEUP_CONFIG
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#define BLE_cy_m0s8_ble__WAKEUP_CONTROL CYREG_BLE_BLELL_WAKEUP_CONTROL
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#define BLE_cy_m0s8_ble__WCO_CONFIG CYREG_BLE_BLESS_WCO_CONFIG
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#define BLE_cy_m0s8_ble__WCO_STATUS CYREG_BLE_BLESS_WCO_STATUS
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#define BLE_cy_m0s8_ble__WCO_TRIM CYREG_BLE_BLESS_WCO_TRIM
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#define BLE_cy_m0s8_ble__WHITELIST_BASE_ADDR CYREG_BLE_BLELL_WHITELIST_BASE_ADDR
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#define BLE_cy_m0s8_ble__WIN_MIN_STEP_SIZE CYREG_BLE_BLELL_WIN_MIN_STEP_SIZE
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#define BLE_cy_m0s8_ble__WINDOW_WIDEN_INTVL CYREG_BLE_BLELL_WINDOW_WIDEN_INTVL
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#define BLE_cy_m0s8_ble__WINDOW_WIDEN_WINOFF CYREG_BLE_BLELL_WINDOW_WIDEN_WINOFF
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#define BLE_cy_m0s8_ble__WL_ADDR_TYPE CYREG_BLE_BLELL_WL_ADDR_TYPE
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#define BLE_cy_m0s8_ble__WL_ENABLE CYREG_BLE_BLELL_WL_ENABLE
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#define BLE_cy_m0s8_ble__XTAL_CLK_DIV_CONFIG CYREG_BLE_BLESS_XTAL_CLK_DIV_CONFIG
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/* PWM_cy_m0s8_tcpwm_1 */
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#define PWM_cy_m0s8_tcpwm_1__CC CYREG_TCPWM_CNT0_CC
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#define PWM_cy_m0s8_tcpwm_1__CC_BUFF CYREG_TCPWM_CNT0_CC_BUFF
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#define PWM_cy_m0s8_tcpwm_1__COUNTER CYREG_TCPWM_CNT0_COUNTER
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#define PWM_cy_m0s8_tcpwm_1__CTRL CYREG_TCPWM_CNT0_CTRL
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#define PWM_cy_m0s8_tcpwm_1__INTR CYREG_TCPWM_CNT0_INTR
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#define PWM_cy_m0s8_tcpwm_1__INTR_MASK CYREG_TCPWM_CNT0_INTR_MASK
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#define PWM_cy_m0s8_tcpwm_1__INTR_MASKED CYREG_TCPWM_CNT0_INTR_MASKED
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#define PWM_cy_m0s8_tcpwm_1__INTR_SET CYREG_TCPWM_CNT0_INTR_SET
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#define PWM_cy_m0s8_tcpwm_1__PERIOD CYREG_TCPWM_CNT0_PERIOD
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#define PWM_cy_m0s8_tcpwm_1__PERIOD_BUFF CYREG_TCPWM_CNT0_PERIOD_BUFF
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#define PWM_cy_m0s8_tcpwm_1__STATUS CYREG_TCPWM_CNT0_STATUS
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#define PWM_cy_m0s8_tcpwm_1__TCPWM_CMD CYREG_TCPWM_CMD
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#define PWM_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_MASK 0x01u
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#define PWM_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_SHIFT 0
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#define PWM_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_MASK 0x100u
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#define PWM_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_SHIFT 8
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#define PWM_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_MASK 0x1000000u
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#define PWM_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_SHIFT 24
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#define PWM_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_MASK 0x10000u
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#define PWM_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_SHIFT 16
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#define PWM_cy_m0s8_tcpwm_1__TCPWM_CTRL CYREG_TCPWM_CTRL
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#define PWM_cy_m0s8_tcpwm_1__TCPWM_CTRL_MASK 0x01u
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#define PWM_cy_m0s8_tcpwm_1__TCPWM_CTRL_SHIFT 0
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#define PWM_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE CYREG_TCPWM_INTR_CAUSE
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#define PWM_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_MASK 0x01u
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#define PWM_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_SHIFT 0
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#define PWM_cy_m0s8_tcpwm_1__TCPWM_NUMBER 0u
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#define PWM_cy_m0s8_tcpwm_1__TR_CTRL0 CYREG_TCPWM_CNT0_TR_CTRL0
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#define PWM_cy_m0s8_tcpwm_1__TR_CTRL1 CYREG_TCPWM_CNT0_TR_CTRL1
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#define PWM_cy_m0s8_tcpwm_1__TR_CTRL2 CYREG_TCPWM_CNT0_TR_CTRL2
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/* Clock_1 */
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#define Clock_1__CTRL_REGISTER CYREG_PERI_PCLK_CTL7
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#define Clock_1__DIV_ID 0x00000040u
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#define Clock_1__DIV_REGISTER CYREG_PERI_DIV_16_CTL0
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#define Clock_1__PA_DIV_ID 0x000000FFu
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/* Red_LED */
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#define Red_LED__0__DR CYREG_GPIO_PRT2_DR
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#define Red_LED__0__DR_CLR CYREG_GPIO_PRT2_DR_CLR
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#define Red_LED__0__DR_INV CYREG_GPIO_PRT2_DR_INV
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#define Red_LED__0__DR_SET CYREG_GPIO_PRT2_DR_SET
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#define Red_LED__0__HSIOM CYREG_HSIOM_PORT_SEL2
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#define Red_LED__0__HSIOM_MASK 0x0F000000u
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#define Red_LED__0__HSIOM_SHIFT 24u
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#define Red_LED__0__INTCFG CYREG_GPIO_PRT2_INTR_CFG
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#define Red_LED__0__INTR CYREG_GPIO_PRT2_INTR
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#define Red_LED__0__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
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#define Red_LED__0__INTSTAT CYREG_GPIO_PRT2_INTR
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#define Red_LED__0__MASK 0x40u
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#define Red_LED__0__OUT_SEL CYREG_UDB_PA2_CFG10
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#define Red_LED__0__OUT_SEL_SHIFT 12u
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#define Red_LED__0__OUT_SEL_VAL 1u
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#define Red_LED__0__PA__CFG0 CYREG_UDB_PA2_CFG0
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#define Red_LED__0__PA__CFG1 CYREG_UDB_PA2_CFG1
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#define Red_LED__0__PA__CFG10 CYREG_UDB_PA2_CFG10
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#define Red_LED__0__PA__CFG11 CYREG_UDB_PA2_CFG11
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#define Red_LED__0__PA__CFG12 CYREG_UDB_PA2_CFG12
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#define Red_LED__0__PA__CFG13 CYREG_UDB_PA2_CFG13
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#define Red_LED__0__PA__CFG14 CYREG_UDB_PA2_CFG14
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#define Red_LED__0__PA__CFG2 CYREG_UDB_PA2_CFG2
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#define Red_LED__0__PA__CFG3 CYREG_UDB_PA2_CFG3
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#define Red_LED__0__PA__CFG4 CYREG_UDB_PA2_CFG4
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#define Red_LED__0__PA__CFG5 CYREG_UDB_PA2_CFG5
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#define Red_LED__0__PA__CFG6 CYREG_UDB_PA2_CFG6
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#define Red_LED__0__PA__CFG7 CYREG_UDB_PA2_CFG7
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#define Red_LED__0__PA__CFG8 CYREG_UDB_PA2_CFG8
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#define Red_LED__0__PA__CFG9 CYREG_UDB_PA2_CFG9
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#define Red_LED__0__PC CYREG_GPIO_PRT2_PC
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#define Red_LED__0__PC2 CYREG_GPIO_PRT2_PC2
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#define Red_LED__0__PORT 2u
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#define Red_LED__0__PS CYREG_GPIO_PRT2_PS
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#define Red_LED__0__SHIFT 6
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#define Red_LED__DR CYREG_GPIO_PRT2_DR
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#define Red_LED__DR_CLR CYREG_GPIO_PRT2_DR_CLR
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#define Red_LED__DR_INV CYREG_GPIO_PRT2_DR_INV
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#define Red_LED__DR_SET CYREG_GPIO_PRT2_DR_SET
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#define Red_LED__INTCFG CYREG_GPIO_PRT2_INTR_CFG
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#define Red_LED__INTR CYREG_GPIO_PRT2_INTR
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#define Red_LED__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
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#define Red_LED__INTSTAT CYREG_GPIO_PRT2_INTR
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#define Red_LED__MASK 0x40u
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#define Red_LED__PA__CFG0 CYREG_UDB_PA2_CFG0
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#define Red_LED__PA__CFG1 CYREG_UDB_PA2_CFG1
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#define Red_LED__PA__CFG10 CYREG_UDB_PA2_CFG10
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#define Red_LED__PA__CFG11 CYREG_UDB_PA2_CFG11
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#define Red_LED__PA__CFG12 CYREG_UDB_PA2_CFG12
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#define Red_LED__PA__CFG13 CYREG_UDB_PA2_CFG13
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#define Red_LED__PA__CFG14 CYREG_UDB_PA2_CFG14
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#define Red_LED__PA__CFG2 CYREG_UDB_PA2_CFG2
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#define Red_LED__PA__CFG3 CYREG_UDB_PA2_CFG3
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#define Red_LED__PA__CFG4 CYREG_UDB_PA2_CFG4
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#define Red_LED__PA__CFG5 CYREG_UDB_PA2_CFG5
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#define Red_LED__PA__CFG6 CYREG_UDB_PA2_CFG6
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#define Red_LED__PA__CFG7 CYREG_UDB_PA2_CFG7
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#define Red_LED__PA__CFG8 CYREG_UDB_PA2_CFG8
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#define Red_LED__PA__CFG9 CYREG_UDB_PA2_CFG9
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#define Red_LED__PC CYREG_GPIO_PRT2_PC
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#define Red_LED__PC2 CYREG_GPIO_PRT2_PC2
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#define Red_LED__PORT 2u
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#define Red_LED__PS CYREG_GPIO_PRT2_PS
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#define Red_LED__SHIFT 6
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/* Miscellaneous */
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#define CY_PROJECT_NAME "BLE Lab 1_1"
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#define CY_VERSION "PSoC Creator 3.2"
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#define CYDEV_BCLK__HFCLK__HZ 48000000U
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#define CYDEV_BCLK__HFCLK__KHZ 48000U
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#define CYDEV_BCLK__HFCLK__MHZ 48U
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#define CYDEV_BCLK__SYSCLK__HZ 48000000U
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#define CYDEV_BCLK__SYSCLK__KHZ 48000U
|
|
#define CYDEV_BCLK__SYSCLK__MHZ 48U
|
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#define CYDEV_CHIP_DIE_GEN4 2u
|
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#define CYDEV_CHIP_DIE_LEOPARD 1u
|
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#define CYDEV_CHIP_DIE_PANTHER 12u
|
|
#define CYDEV_CHIP_DIE_PSOC4A 5u
|
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#define CYDEV_CHIP_DIE_PSOC5LP 11u
|
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#define CYDEV_CHIP_DIE_UNKNOWN 0u
|
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#define CYDEV_CHIP_FAMILY_PSOC3 1u
|
|
#define CYDEV_CHIP_FAMILY_PSOC4 2u
|
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#define CYDEV_CHIP_FAMILY_PSOC5 3u
|
|
#define CYDEV_CHIP_FAMILY_UNKNOWN 0u
|
|
#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC4
|
|
#define CYDEV_CHIP_JTAG_ID 0x0E34119Eu
|
|
#define CYDEV_CHIP_MEMBER_3A 1u
|
|
#define CYDEV_CHIP_MEMBER_4A 5u
|
|
#define CYDEV_CHIP_MEMBER_4C 9u
|
|
#define CYDEV_CHIP_MEMBER_4D 3u
|
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#define CYDEV_CHIP_MEMBER_4E 4u
|
|
#define CYDEV_CHIP_MEMBER_4F 6u
|
|
#define CYDEV_CHIP_MEMBER_4G 2u
|
|
#define CYDEV_CHIP_MEMBER_4L 8u
|
|
#define CYDEV_CHIP_MEMBER_4M 7u
|
|
#define CYDEV_CHIP_MEMBER_5A 11u
|
|
#define CYDEV_CHIP_MEMBER_5B 10u
|
|
#define CYDEV_CHIP_MEMBER_UNKNOWN 0u
|
|
#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_4F
|
|
#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED
|
|
#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT
|
|
#define CYDEV_CHIP_REV_GEN4_ES 17u
|
|
#define CYDEV_CHIP_REV_GEN4_ES2 33u
|
|
#define CYDEV_CHIP_REV_GEN4_PRODUCTION 17u
|
|
#define CYDEV_CHIP_REV_LEOPARD_ES1 0u
|
|
#define CYDEV_CHIP_REV_LEOPARD_ES2 1u
|
|
#define CYDEV_CHIP_REV_LEOPARD_ES3 3u
|
|
#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u
|
|
#define CYDEV_CHIP_REV_PANTHER_ES0 0u
|
|
#define CYDEV_CHIP_REV_PANTHER_ES1 1u
|
|
#define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1u
|
|
#define CYDEV_CHIP_REV_PSOC4A_ES0 17u
|
|
#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u
|
|
#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u
|
|
#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_3A_ES1 0u
|
|
#define CYDEV_CHIP_REVISION_3A_ES2 1u
|
|
#define CYDEV_CHIP_REVISION_3A_ES3 3u
|
|
#define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u
|
|
#define CYDEV_CHIP_REVISION_4A_ES0 17u
|
|
#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u
|
|
#define CYDEV_CHIP_REVISION_4C_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_4E_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0u
|
|
#define CYDEV_CHIP_REVISION_4G_ES 17u
|
|
#define CYDEV_CHIP_REVISION_4G_ES2 33u
|
|
#define CYDEV_CHIP_REVISION_4G_PRODUCTION 17u
|
|
#define CYDEV_CHIP_REVISION_4L_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_4M_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_5A_ES0 0u
|
|
#define CYDEV_CHIP_REVISION_5A_ES1 1u
|
|
#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u
|
|
#define CYDEV_CHIP_REVISION_5B_ES0 0u
|
|
#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_4F_PRODUCTION
|
|
#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REVISION_USED
|
|
#define CYDEV_CONFIG_READ_ACCELERATOR 1
|
|
#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0
|
|
#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowButWarn
|
|
#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1
|
|
#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2
|
|
#define CYDEV_CONFIGURATION_COMPRESSED 1
|
|
#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0
|
|
#define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_COMPRESSED
|
|
#define CYDEV_CONFIGURATION_MODE_DMA 2
|
|
#define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1
|
|
#define CYDEV_DEBUG_PROTECT_KILL 4
|
|
#define CYDEV_DEBUG_PROTECT_OPEN 1
|
|
#define CYDEV_DEBUG_PROTECT CYDEV_DEBUG_PROTECT_OPEN
|
|
#define CYDEV_DEBUG_PROTECT_PROTECTED 2
|
|
#define CYDEV_DEBUGGING_DPS_Disable 3
|
|
#define CYDEV_DEBUGGING_DPS_SWD 2
|
|
#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD
|
|
#define CYDEV_DEBUGGING_ENABLE 1
|
|
#define CYDEV_DFT_SELECT_CLK0 10u
|
|
#define CYDEV_DFT_SELECT_CLK1 11u
|
|
#define CYDEV_HEAP_SIZE 0x80
|
|
#define CYDEV_IMO_TRIMMED_BY_WCO 0u
|
|
#define CYDEV_PROJ_TYPE 0
|
|
#define CYDEV_PROJ_TYPE_BOOTLOADER 1
|
|
#define CYDEV_PROJ_TYPE_LAUNCHER 5
|
|
#define CYDEV_PROJ_TYPE_LOADABLE 2
|
|
#define CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER 4
|
|
#define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3
|
|
#define CYDEV_PROJ_TYPE_STANDARD 0
|
|
#define CYDEV_STACK_SIZE 0x0800
|
|
#define CYDEV_USE_BUNDLED_CMSIS 1
|
|
#define CYDEV_VARIABLE_VDDA 1
|
|
#define CYDEV_VDDA 3.3
|
|
#define CYDEV_VDDA_MV 3300
|
|
#define CYDEV_VDDD 3.3
|
|
#define CYDEV_VDDD_MV 3300
|
|
#define CYDEV_VDDR 3.3
|
|
#define CYDEV_VDDR_MV 3300
|
|
#define CYDEV_WDT_GENERATE_ISR 0u
|
|
#define CYIPBLOCK_m0s8bless_VERSION 1
|
|
#define CYIPBLOCK_m0s8cpussv2_VERSION 1
|
|
#define CYIPBLOCK_m0s8csd_VERSION 1
|
|
#define CYIPBLOCK_m0s8ioss_VERSION 1
|
|
#define CYIPBLOCK_m0s8lcd_VERSION 2
|
|
#define CYIPBLOCK_m0s8lpcomp_VERSION 2
|
|
#define CYIPBLOCK_m0s8peri_VERSION 1
|
|
#define CYIPBLOCK_m0s8scb_VERSION 2
|
|
#define CYIPBLOCK_m0s8srssv2_VERSION 1
|
|
#define CYIPBLOCK_m0s8tcpwm_VERSION 2
|
|
#define CYIPBLOCK_m0s8udbif_VERSION 1
|
|
#define CYIPBLOCK_s8pass4al_VERSION 1
|
|
#define CYDEV_BOOTLOADER_ENABLE 0
|
|
|
|
#endif /* INCLUDED_CYFITTER_H */
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