|
/*******************************************************************************
|
|
* FILENAME: cyfitter_cfg.c
|
|
*
|
|
* PSoC Creator 3.2
|
|
*
|
|
* DESCRIPTION:
|
|
* This file contains device initialization code.
|
|
* Except for the user defined sections in CyClockStartupError(), this file should not be modified.
|
|
* This file is automatically generated by PSoC Creator.
|
|
*
|
|
********************************************************************************
|
|
* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
|
|
* You may use this file only in accordance with the license, terms, conditions,
|
|
* disclaimers, and limitations in the end user license agreement accompanying
|
|
* the software package with which this file was provided.
|
|
********************************************************************************/
|
|
|
|
#include <string.h>
|
|
#include "cytypes.h"
|
|
#include "cydevice_trm.h"
|
|
#include "cyfitter.h"
|
|
#include "CyLib.h"
|
|
#include "cyfitter_cfg.h"
|
|
|
|
|
|
#if defined(__GNUC__) || defined(__ARMCC_VERSION)
|
|
#define CYPACKED
|
|
#define CYPACKED_ATTR __attribute__ ((packed))
|
|
#define CYALIGNED __attribute__ ((aligned))
|
|
#define CY_CFG_UNUSED __attribute__ ((unused))
|
|
#define CY_CFG_SECTION __attribute__ ((section(".psocinit")))
|
|
|
|
#if defined(__ARMCC_VERSION)
|
|
#define CY_CFG_MEMORY_BARRIER() __memory_changed()
|
|
#else
|
|
#define CY_CFG_MEMORY_BARRIER() __sync_synchronize()
|
|
#endif
|
|
|
|
#elif defined(__ICCARM__)
|
|
#include <intrinsics.h>
|
|
|
|
#define CYPACKED __packed
|
|
#define CYPACKED_ATTR
|
|
#define CYALIGNED _Pragma("data_alignment=4")
|
|
#define CY_CFG_UNUSED _Pragma("diag_suppress=Pe177")
|
|
#define CY_CFG_SECTION _Pragma("location=\".psocinit\"")
|
|
|
|
#define CY_CFG_MEMORY_BARRIER() __DMB()
|
|
|
|
#else
|
|
#error Unsupported toolchain
|
|
#endif
|
|
|
|
|
|
CY_CFG_UNUSED
|
|
static void CYMEMZERO(void *s, size_t n);
|
|
CY_CFG_UNUSED
|
|
static void CYMEMZERO(void *s, size_t n)
|
|
{
|
|
(void)memset(s, 0, n);
|
|
}
|
|
CY_CFG_UNUSED
|
|
static void CYCONFIGCPY(void *dest, const void *src, size_t n);
|
|
CY_CFG_UNUSED
|
|
static void CYCONFIGCPY(void *dest, const void *src, size_t n)
|
|
{
|
|
(void)memcpy(dest, src, n);
|
|
}
|
|
CY_CFG_UNUSED
|
|
static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n);
|
|
CY_CFG_UNUSED
|
|
static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n)
|
|
{
|
|
(void)memcpy(dest, src, n);
|
|
}
|
|
|
|
|
|
|
|
/* Clock startup error codes */
|
|
#define CYCLOCKSTART_NO_ERROR 0u
|
|
#define CYCLOCKSTART_XTAL_ERROR 1u
|
|
#define CYCLOCKSTART_32KHZ_ERROR 2u
|
|
#define CYCLOCKSTART_PLL_ERROR 3u
|
|
|
|
#ifdef CY_NEED_CYCLOCKSTARTUPERROR
|
|
/*******************************************************************************
|
|
* Function Name: CyClockStartupError
|
|
********************************************************************************
|
|
* Summary:
|
|
* If an error is encountered during clock configuration (crystal startup error,
|
|
* PLL lock error, etc.), the system will end up here. Unless reimplemented by
|
|
* the customer, this function will stop in an infinite loop.
|
|
*
|
|
* Parameters:
|
|
* void
|
|
*
|
|
* Return:
|
|
* void
|
|
*
|
|
*******************************************************************************/
|
|
CY_CFG_UNUSED
|
|
static void CyClockStartupError(uint8 errorCode);
|
|
CY_CFG_UNUSED
|
|
static void CyClockStartupError(uint8 errorCode)
|
|
{
|
|
/* To remove the compiler warning if errorCode not used. */
|
|
errorCode = errorCode;
|
|
|
|
/* `#START CyClockStartupError` */
|
|
|
|
/* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */
|
|
/* we will end up here to allow the customer to implement something to */
|
|
/* deal with the clock condition. */
|
|
|
|
/* `#END` */
|
|
|
|
/* If nothing else, stop here since the clocks have not started */
|
|
/* correctly. */
|
|
while(1) {}
|
|
}
|
|
#endif
|
|
|
|
#define CY_CFG_BASE_ADDR_COUNT 1u
|
|
CYPACKED typedef struct
|
|
{
|
|
uint8 offset;
|
|
uint8 value;
|
|
} CYPACKED_ATTR cy_cfg_addrvalue_t;
|
|
|
|
|
|
|
|
/*******************************************************************************
|
|
* Function Name: cfg_write_bytes32
|
|
********************************************************************************
|
|
* Summary:
|
|
* This function is used for setting up the chip configuration areas that
|
|
* contain relatively sparse data.
|
|
*
|
|
* Parameters:
|
|
* void
|
|
*
|
|
* Return:
|
|
* void
|
|
*
|
|
*******************************************************************************/
|
|
static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]);
|
|
static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[])
|
|
{
|
|
/* For 32-bit little-endian architectures */
|
|
uint32 i, j = 0u;
|
|
for (i = 0u; i < CY_CFG_BASE_ADDR_COUNT; i++)
|
|
{
|
|
uint32 baseAddr = addr_table[i];
|
|
uint8 count = (uint8)baseAddr;
|
|
baseAddr &= 0xFFFFFF00u;
|
|
while (count != 0u)
|
|
{
|
|
CY_SET_XTND_REG8((void CYFAR *)(baseAddr + data_table[j].offset), data_table[j].value);
|
|
j++;
|
|
count--;
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
/*******************************************************************************
|
|
* Function Name: ClockSetup
|
|
********************************************************************************
|
|
*
|
|
* Summary:
|
|
* Performs the initialization of all of the clocks in the device based on the
|
|
* settings in the Clock tab of the DWR. This includes enabling the requested
|
|
* clocks and setting the necessary dividers to produce the desired frequency.
|
|
*
|
|
* Parameters:
|
|
* void
|
|
*
|
|
* Return:
|
|
* void
|
|
*
|
|
*******************************************************************************/
|
|
static void ClockSetup(void);
|
|
CY_CFG_SECTION
|
|
static void ClockSetup(void)
|
|
{
|
|
|
|
/* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */
|
|
CY_SET_REG32((void CYXDATA *)(CYREG_CPUSS_FLASH_CTL), (0x0012u));
|
|
|
|
/* Start the WCO */
|
|
CySysClkWcoStart();
|
|
CyDelayCycles(12000000u); /* WCO may take up to 500ms to start */
|
|
(void)CySysClkWcoSetPowerMode(CY_SYS_CLK_WCO_LPM); /* Switch to the low power mode */
|
|
|
|
/* Setup and trim IMO based on desired frequency. */
|
|
CySysClkWriteImoFreq(48u);
|
|
/* CYDEV_CLK_ILO_CONFIG Starting address: CYDEV_CLK_ILO_CONFIG */
|
|
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_ILO_CONFIG), 0x80000006u);
|
|
|
|
/* CYDEV_WDT_CONFIG Starting address: CYDEV_WDT_CONFIG */
|
|
CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x40000000u);
|
|
|
|
|
|
/* Enable fast start mode for XO */
|
|
CY_SET_REG32((void*)CYREG_BLE_BLERD_BB_XO, CY_GET_REG32((void*)CYREG_BLE_BLERD_BB_XO) | (uint32)0x02u);
|
|
CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLERD_BB_XO_CAPTRIM), 0x00003E2Du);
|
|
/* Disable Crystal Stable Interrupt before enabling ECO */
|
|
CY_SET_REG32((void*)CYREG_BLE_BLESS_LL_DSM_CTRL, CY_GET_REG32((void*)CYREG_BLE_BLESS_LL_DSM_CTRL) & (~(uint32)0x08u));
|
|
/* Start the ECO and do not check status since it is not needed for HFCLK */
|
|
(void)CySysClkEcoStart(2000u);
|
|
CyDelayUs(1500u); /* Wait to stabalize */
|
|
|
|
/* Setup phase aligned clocks */
|
|
CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL0, 0x00BB7F00u);
|
|
CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF40u);
|
|
|
|
/* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */
|
|
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG), 0x80000000u);
|
|
|
|
/* CYDEV_CLK_SELECT Starting address: CYDEV_CLK_SELECT */
|
|
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT), 0x00040000u);
|
|
|
|
/* CYDEV_PERI_PCLK_CTL7 Starting address: CYDEV_PERI_PCLK_CTL7 */
|
|
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL7), 0x00000040u);
|
|
|
|
CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x40000000u);
|
|
}
|
|
|
|
|
|
/* Analog API Functions */
|
|
|
|
|
|
/*******************************************************************************
|
|
* Function Name: AnalogSetDefault
|
|
********************************************************************************
|
|
*
|
|
* Summary:
|
|
* Sets up the analog portions of the chip to default values based on chip
|
|
* configuration options from the project.
|
|
*
|
|
* Parameters:
|
|
* void
|
|
*
|
|
* Return:
|
|
* void
|
|
*
|
|
*******************************************************************************/
|
|
static void AnalogSetDefault(void);
|
|
static void AnalogSetDefault(void)
|
|
{
|
|
CY_SET_XTND_REG32((void CYFAR *)CYREG_CTBM0_DFT_CTRL, 0x00000003u);
|
|
CY_SET_XTND_REG32((void CYFAR *)CYREG_CTBM1_DFT_CTRL, 0x00000003u);
|
|
CY_SET_XTND_REG32((void CYFAR *)CYREG_PASS_DSAB_DSAB_CTRL, 0x00000000u);
|
|
}
|
|
|
|
#define CY_AMUX_UNUSED CYREG_CM0_ROM_DWT
|
|
|
|
|
|
/*******************************************************************************
|
|
* Function Name: cyfitter_cfg
|
|
********************************************************************************
|
|
* Summary:
|
|
* This function is called by the start-up code for the selected device. It
|
|
* performs all of the necessary device configuration based on the design
|
|
* settings. This includes settings from the Design Wide Resources (DWR) such
|
|
* as Clocks and Pins as well as any component configuration that is necessary.
|
|
*
|
|
* Parameters:
|
|
* void
|
|
*
|
|
* Return:
|
|
* void
|
|
*
|
|
*******************************************************************************/
|
|
CY_CFG_SECTION
|
|
void cyfitter_cfg(void)
|
|
{
|
|
/* Disable interrupts by default. Let user enable if/when they want. */
|
|
CyGlobalIntDisable;
|
|
|
|
CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLESS_LL_DSM_CTRL), 0x00000000u);
|
|
|
|
{
|
|
static const uint32 CYCODE cy_cfg_addr_table[] = {
|
|
0x400F4204u, /* Base address: 0x400F4200 Count: 4 */
|
|
};
|
|
|
|
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
|
|
{0x19u, 0x02u},
|
|
{0x5Du, 0x02u},
|
|
{0xC6u, 0x08u},
|
|
{0xD6u, 0x01u},
|
|
};
|
|
|
|
|
|
|
|
CYPACKED typedef struct {
|
|
void CYFAR *address;
|
|
uint16 size;
|
|
} CYPACKED_ATTR cfg_memset_t;
|
|
|
|
static const cfg_memset_t CYCODE cfg_memset_list [] = {
|
|
/* address, size */
|
|
{(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u},
|
|
{(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u},
|
|
};
|
|
|
|
uint8 CYDATA i;
|
|
|
|
/* Zero out critical memory blocks before beginning configuration */
|
|
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
|
|
{
|
|
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
|
|
CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));
|
|
}
|
|
|
|
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
|
|
|
|
/* HSIOM Starting address: CYDEV_HSIOM_BASE */
|
|
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0xEE000000u);
|
|
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL2), 0x03000000u);
|
|
|
|
/* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */
|
|
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u);
|
|
|
|
/* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */
|
|
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u);
|
|
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA2_CFG8), 0x10000000u);
|
|
|
|
/* Enable digital routing */
|
|
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u);
|
|
|
|
/* Enable UDB array */
|
|
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u));
|
|
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u));
|
|
}
|
|
|
|
/* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */
|
|
/* IOPINS0_0 Starting address: CYDEV_GPIO_PRT0_DR */
|
|
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT0_PC), 0x00D80000u);
|
|
|
|
/* IOPINS0_2 Starting address: CYDEV_GPIO_PRT2_DR */
|
|
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_DR), 0x00000040u);
|
|
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_PC), 0x00180000u);
|
|
|
|
/* Setup clocks based on selections from Clock DWR */
|
|
ClockSetup();
|
|
|
|
/* Perform basic analog initialization to defaults */
|
|
AnalogSetDefault();
|
|
|
|
}
|