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/*
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Copyright Cypress Semiconductor Corporation, 2010-2011
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*/
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/*library (p4) {
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timescale : 1ns;
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*/
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cell (m0s8clockblockcell) {
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pin (imo) { direction : output; }
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pin (ext) { direction : output; }
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pin (eco) { direction : output; }
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pin (ilo) { direction : output; }
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pin (wco) { direction : output; }
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pin (dbl) { direction : output; }
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pin (pll) { direction : output; }
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pin (dpll) { direction : output; }
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/* TODO: these are backwards from the diagram */
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bundle (dsi_out) {
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members (dsi_out_0, dsi_out_1, dsi_out_2, dsi_out_3);
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direction : input;
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}
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bundle (dsi_in) {
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members (dsi_in_0, dsi_in_1, dsi_in_2, dsi_in_3);
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direction : output;
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}
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pin (lfclk) { direction : output; }
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pin (hfclk) { direction : output; }
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pin (sysclk) { direction : output; }
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pin (halfsysclk) { direction : output; }
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/* TODO: name doesn't match SAS (clk_udbN) */
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bundle (udb_div) {
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members (udb_div_0, udb_div_1, udb_div_2, udb_div_3,
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udb_div_4, udb_div_5, udb_div_6, udb_div_7);
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direction : output;
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}
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/* TODO: name doesn't match SAS (clk_uabN) */
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bundle (uab_div) {
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members (uab_div_0, uab_div_1, uab_div_2, uab_div_3,
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uab_div_4, uab_div_5, uab_div_6, uab_div_7);
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direction : output;
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}
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/* TODO: name doesn't match SAS (clk_ffN) */
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bundle (ff_div) {
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members (ff_div_0, ff_div_1, ff_div_2, ff_div_3,
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ff_div_4, ff_div_5, ff_div_6, ff_div_7);
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direction : output;
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}
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}
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cell (m0s8clockgenblockcell) {
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bundle (gen_clk_in) {
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members (gen_clk_in_0, gen_clk_in_1, gen_clk_in_2, gen_clk_in_3,
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gen_clk_in_4, gen_clk_in_5, gen_clk_in_6, gen_clk_in_7);
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direction : input;
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}
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pin (gen_clk_out_0) {
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direction : output;
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timing() {
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timing_sense : positive_unate;
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timing_type : combinational;
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related_pin : "gen_clk_in_0";
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intrinsic_rise : 0.0;
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intrinsic_fall : 0.0;
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}
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}
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pin (gen_clk_out_1) {
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direction : output;
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timing() {
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timing_sense : positive_unate;
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timing_type : combinational;
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related_pin : "gen_clk_in_1";
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intrinsic_rise : 0.0;
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intrinsic_fall : 0.0;
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}
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}
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pin (gen_clk_out_2) {
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direction : output;
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timing() {
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timing_sense : positive_unate;
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timing_type : combinational;
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related_pin : "gen_clk_in_2";
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intrinsic_rise : 0.0;
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intrinsic_fall : 0.0;
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}
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}
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pin (gen_clk_out_3) {
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direction : output;
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timing() {
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timing_sense : positive_unate;
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timing_type : combinational;
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related_pin : "gen_clk_in_3";
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intrinsic_rise : 0.0;
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intrinsic_fall : 0.0;
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}
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}
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pin (gen_clk_out_4) {
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direction : output;
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timing() {
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timing_sense : positive_unate;
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timing_type : combinational;
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related_pin : "gen_clk_in_4";
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intrinsic_rise : 0.0;
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intrinsic_fall : 0.0;
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}
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}
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pin (gen_clk_out_5) {
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direction : output;
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timing() {
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timing_sense : positive_unate;
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timing_type : combinational;
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related_pin : "gen_clk_in_5";
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intrinsic_rise : 0.0;
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intrinsic_fall : 0.0;
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}
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}
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pin (gen_clk_out_6) {
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direction : output;
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timing() {
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timing_sense : positive_unate;
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timing_type : combinational;
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related_pin : "gen_clk_in_6";
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intrinsic_rise : 0.0;
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intrinsic_fall : 0.0;
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}
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}
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pin (gen_clk_out_7) {
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direction : output;
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timing() {
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timing_sense : positive_unate;
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timing_type : combinational;
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related_pin : "gen_clk_in_7";
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intrinsic_rise : 0.0;
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intrinsic_fall : 0.0;
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}
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}
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}
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cell (carrycell) {
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}
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cell (interrupt) {
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pin (clock) {
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direction : input;
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clock : true;
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}
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pin (interrupt) {
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direction : input;
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}
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}
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cell (logicalport) {
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pin (interrupt) {
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direction : output;
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}
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pin (precharge) {
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direction : input;
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}
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pin (in_clock) {
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direction : input;
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}
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pin (in_clock_en) {
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direction : input;
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}
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pin (in_reset) {
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direction : input;
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}
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pin (out_clock) {
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direction : input;
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}
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pin (out_clock_en) {
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direction : input;
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}
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pin (out_reset) {
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direction : input;
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}
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}
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cell (count7cell) {
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pin (clock) {
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direction : input;
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clock : true;
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}
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pin (clock_n) {
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direction : input;
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clock : true;
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}
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pin (extclk) {
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direction : input;
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clock : true;
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}
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pin (extclk_n) {
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direction : input;
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clock : true;
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}
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pin (clk_en) {
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direction : input;
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timing() {
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timing_type : setup_rising;
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related_pin : "clock";
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intrinsic_rise : 2.1;
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intrinsic_fall : 2.1;
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}
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timing() {
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timing_type : hold_rising;
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related_pin : "clock";
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intrinsic_rise : 0.00;
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intrinsic_fall : 0.00;
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}
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timing() {
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timing_type : setup_falling;
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related_pin : "clock_n";
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intrinsic_rise : 2.1;
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intrinsic_fall : 2.1;
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}
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timing() {
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timing_type : hold_falling;
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related_pin : "clock_n";
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intrinsic_rise : 0.00;
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intrinsic_fall : 0.00;
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}
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timing() {
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timing_type : setup_rising;
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related_pin : "extclk";
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intrinsic_rise : 0;
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intrinsic_fall : 0;
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}
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timing() {
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timing_type : hold_rising;
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related_pin : "extclk";
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intrinsic_rise : 0.6;
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intrinsic_fall : 0.6;
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}
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timing() {
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timing_type : setup_falling;
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related_pin : "extclk_n";
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intrinsic_rise : 0;
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intrinsic_fall : 0;
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}
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timing() {
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timing_type : hold_falling;
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related_pin : "extclk_n";
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intrinsic_rise : 0.6;
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intrinsic_fall : 0.6;
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}
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}
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pin (reset) {
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direction : input;
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timing() {
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timing_type : recovery_rising;
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related_pin : "clock";
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intrinsic_rise : 0.00;
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intrinsic_fall : 0.00;
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}
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timing() {
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timing_type : removal_rising;
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related_pin : "clock";
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intrinsic_rise : 0.00;
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intrinsic_fall : 0.00;
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}
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timing() {
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timing_type : recovery_falling;
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related_pin : "clock_n";
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intrinsic_rise : 0.00;
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intrinsic_fall : 0.00;
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}
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timing() {
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timing_type : removal_falling;
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related_pin : "clock_n";
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intrinsic_rise : 0.00;
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intrinsic_fall : 0.00;
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}
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timing() {
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timing_type : recovery_rising;
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related_pin : "extclk";
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intrinsic_rise : 0.00;
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intrinsic_fall : 0.00;
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}
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timing() {
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timing_type : removal_rising;
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related_pin : "extclk";
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intrinsic_rise : 0.00;
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intrinsic_fall : 0.00;
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}
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timing() {
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timing_type : recovery_falling;
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related_pin : "extclk_n";
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intrinsic_rise : 0.00;
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intrinsic_fall : 0.00;
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}
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timing() {
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timing_type : removal_falling;
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related_pin : "extclk_n";
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intrinsic_rise : 0.00;
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intrinsic_fall : 0.00;
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}
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}
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pin (load) {
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direction : input;
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timing() {
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timing_type : setup_rising;
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related_pin : "clock";
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intrinsic_rise : 4.22;
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intrinsic_fall : 4.22;
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}
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timing() {
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timing_type : hold_rising;
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related_pin : "clock";
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intrinsic_rise : 0.00;
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intrinsic_fall : 0.00;
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}
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timing() {
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timing_type : setup_falling;
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related_pin : "clock_n";
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intrinsic_rise : 4.22;
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intrinsic_fall : 4.22;
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}
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timing() {
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timing_type : hold_falling;
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related_pin : "clock_n";
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intrinsic_rise : 0.00;
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intrinsic_fall : 0.00;
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}
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timing() {
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timing_type : setup_rising;
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related_pin : "extclk";
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intrinsic_rise : 6.22;
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intrinsic_fall : 6.22;
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}
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timing() {
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timing_type : hold_rising;
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related_pin : "extclk";
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intrinsic_rise : 0.00;
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intrinsic_fall : 0.00;
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}
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timing() {
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timing_type : setup_falling;
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related_pin : "extclk_n";
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intrinsic_rise : 6.22;
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intrinsic_fall : 6.22;
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}
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timing() {
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timing_type : hold_falling;
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related_pin : "extclk_n";
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intrinsic_rise : 0.00;
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intrinsic_fall : 0.00;
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}
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}
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pin (enable) {
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direction : input;
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timing() {
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timing_type : setup_rising;
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related_pin : "clock";
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intrinsic_rise : 3.34;
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intrinsic_fall : 3.34;
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}
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timing() {
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timing_type : hold_rising;
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related_pin : "clock";
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intrinsic_rise : 0.00;
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intrinsic_fall : 0.00;
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}
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timing() {
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timing_type : setup_falling;
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related_pin : "clock_n";
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intrinsic_rise : 3.34;
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intrinsic_fall : 3.34;
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}
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timing() {
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timing_type : hold_falling;
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related_pin : "clock_n";
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intrinsic_rise : 0.00;
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intrinsic_fall : 0.00;
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}
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timing() {
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timing_type : setup_rising;
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related_pin : "extclk";
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intrinsic_rise : 5.34;
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intrinsic_fall : 5.34;
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}
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timing() {
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timing_type : hold_rising;
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related_pin : "extclk";
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intrinsic_rise : 0.00;
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intrinsic_fall : 0.00;
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}
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timing() {
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timing_type : setup_falling;
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related_pin : "extclk_n";
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intrinsic_rise : 5.34;
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intrinsic_fall : 5.34;
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}
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timing() {
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timing_type : hold_falling;
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related_pin : "extclk_n";
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intrinsic_rise : 0.00;
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intrinsic_fall : 0.00;
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}
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}
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bundle (count) {
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members (count_0, count_1, count_2, count_3, count_4, count_5, count_6);
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direction : output;
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timing() {
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timing_type : rising_edge;
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related_pin : "clock";
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intrinsic_rise : 2.11;
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intrinsic_fall : 2.11;
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}
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timing() {
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timing_type : rising_edge;
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related_pin : "clock";
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intrinsic_rise : 1.92;
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intrinsic_fall : 1.92;
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}
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timing() {
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timing_type : falling_edge;
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related_pin : "clock_n";
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intrinsic_rise : 2.11;
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intrinsic_fall : 2.11;
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}
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timing() {
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timing_type : falling_edge;
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related_pin : "clock_n";
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intrinsic_rise : 1.92;
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intrinsic_fall : 1.92;
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}
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timing() {
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timing_type : rising_edge;
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related_pin : "extclk";
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intrinsic_rise : 4.11;
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intrinsic_fall : 4.11;
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}
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timing() {
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timing_type : rising_edge;
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related_pin : "extclk";
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intrinsic_rise : 3.92;
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intrinsic_fall : 3.92;
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}
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timing() {
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timing_type : falling_edge;
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related_pin : "extclk_n";
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intrinsic_rise : 4.11;
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intrinsic_fall : 4.11;
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}
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timing() {
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timing_type : falling_edge;
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related_pin : "extclk_n";
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intrinsic_rise : 3.92;
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intrinsic_fall : 3.92;
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}
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timing() {
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timing_type : clear;
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timing_sense : negative_unate;
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related_pin : "reset";
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intrinsic_rise : 7.57;
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intrinsic_fall : 7.57;
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}
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timing() {
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timing_type : clear;
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timing_sense : negative_unate;
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related_pin : "reset";
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intrinsic_rise : 6.24;
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intrinsic_fall : 6.24;
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}
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}
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pin (tc) {
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direction : output;
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timing() {
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timing_type : rising_edge;
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related_pin : "clock";
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intrinsic_rise : 2.58;
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intrinsic_fall : 2.58;
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}
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timing() {
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timing_type : rising_edge;
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related_pin : "clock";
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intrinsic_rise : 2.04;
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intrinsic_fall : 2.04;
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}
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timing() {
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timing_type : falling_edge;
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related_pin : "clock_n";
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intrinsic_rise : 2.58;
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intrinsic_fall : 2.58;
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}
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timing() {
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timing_type : falling_edge;
|
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related_pin : "clock_n";
|
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intrinsic_rise : 2.04;
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intrinsic_fall : 2.04;
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}
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timing() {
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timing_type : rising_edge;
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related_pin : "extclk";
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intrinsic_rise : 4.58;
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intrinsic_fall : 4.58;
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}
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timing() {
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timing_type : rising_edge;
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related_pin : "extclk";
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intrinsic_rise : 4.04;
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intrinsic_fall : 4.04;
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}
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timing() {
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timing_type : falling_edge;
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related_pin : "extclk_n";
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intrinsic_rise : 4.58;
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intrinsic_fall : 4.58;
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}
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timing() {
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timing_type : falling_edge;
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related_pin : "extclk_n";
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intrinsic_rise : 4.04;
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intrinsic_fall : 4.04;
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}
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timing() {
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timing_type : preset;
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timing_sense : positive_unate;
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related_pin : "reset";
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intrinsic_rise : 8.02;
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intrinsic_fall : 8.02;
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}
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timing() {
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timing_type : preset;
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timing_sense : positive_unate;
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related_pin : "reset";
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intrinsic_rise : 6.19;
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intrinsic_fall : 6.19;
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}
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}
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}
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|
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cell (count7cell_alt) {
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pin (clock) {
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direction : input;
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clock : true;
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}
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pin (clock_n) {
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direction : input;
|
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clock : true;
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}
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pin (extclk) {
|
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direction : input;
|
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clock : true;
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}
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pin (extclk_n) {
|
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direction : input;
|
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clock : true;
|
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}
|
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pin (clk_en) {
|
|
direction : input;
|
|
timing() {
|
|
timing_type : setup_rising;
|
|
related_pin : "clock";
|
|
intrinsic_rise : 2.1;
|
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intrinsic_fall : 2.1;
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}
|
|
timing() {
|
|
timing_type : hold_rising;
|
|
related_pin : "clock";
|
|
intrinsic_rise : 0.00;
|
|
intrinsic_fall : 0.00;
|
|
}
|
|
timing() {
|
|
timing_type : setup_falling;
|
|
related_pin : "clock_n";
|
|
intrinsic_rise : 2.1;
|
|
intrinsic_fall : 2.1;
|
|
}
|
|
timing() {
|
|
timing_type : hold_falling;
|
|
related_pin : "clock_n";
|
|
intrinsic_rise : 0.00;
|
|
intrinsic_fall : 0.00;
|
|
}
|
|
timing() {
|
|
timing_type : setup_rising;
|
|
related_pin : "extclk";
|
|
intrinsic_rise : 0;
|
|
intrinsic_fall : 0;
|
|
}
|
|
timing() {
|
|
timing_type : hold_rising;
|
|
related_pin : "extclk";
|
|
intrinsic_rise : 0.6;
|
|
intrinsic_fall : 0.6;
|
|
}
|
|
timing() {
|
|
timing_type : setup_falling;
|
|
related_pin : "extclk_n";
|
|
intrinsic_rise : 0;
|
|
intrinsic_fall : 0;
|
|
}
|
|
timing() {
|
|
timing_type : hold_falling;
|
|
related_pin : "extclk_n";
|
|
intrinsic_rise : 0.6;
|
|
intrinsic_fall : 0.6;
|
|
}
|
|
}
|
|
pin (reset) {
|
|
direction : input;
|
|
timing() {
|
|
timing_type : recovery_rising;
|
|
related_pin : "clock";
|
|
intrinsic_rise : 0.00;
|
|
intrinsic_fall : 0.00;
|
|
}
|
|
timing() {
|
|
timing_type : removal_rising;
|
|
related_pin : "clock";
|
|
intrinsic_rise : 0.00;
|
|
intrinsic_fall : 0.00;
|
|
}
|
|
timing() {
|
|
timing_type : recovery_falling;
|
|
related_pin : "clock_n";
|
|
intrinsic_rise : 0.00;
|
|
intrinsic_fall : 0.00;
|
|
}
|
|
timing() {
|
|
timing_type : removal_falling;
|
|
related_pin : "clock_n";
|
|
intrinsic_rise : 0.00;
|
|
intrinsic_fall : 0.00;
|
|
}
|
|
timing() {
|
|
timing_type : recovery_rising;
|
|
related_pin : "extclk";
|
|
intrinsic_rise : 0.00;
|
|
intrinsic_fall : 0.00;
|
|
}
|
|
timing() {
|
|
timing_type : removal_rising;
|
|
related_pin : "extclk";
|
|
intrinsic_rise : 0.00;
|
|
intrinsic_fall : 0.00;
|
|
}
|
|
timing() {
|
|
timing_type : recovery_falling;
|
|
related_pin : "extclk_n";
|
|
intrinsic_rise : 0.00;
|
|
intrinsic_fall : 0.00;
|
|
}
|
|
timing() {
|
|
timing_type : removal_falling;
|
|
related_pin : "extclk_n";
|
|
intrinsic_rise : 0.00;
|
|
intrinsic_fall : 0.00;
|
|
}
|
|
}
|
|
pin (load) {
|
|
direction : input;
|
|
timing() {
|
|
timing_type : setup_rising;
|
|
related_pin : "clock";
|
|
intrinsic_rise : 4.22;
|
|
intrinsic_fall : 4.22;
|
|
}
|
|
timing() {
|
|
timing_type : hold_rising;
|
|
related_pin : "clock";
|
|
intrinsic_rise : 0.00;
|
|
intrinsic_fall : 0.00;
|
|
}
|
|
timing() {
|
|
timing_type : setup_falling;
|
|
related_pin : "clock_n";
|
|
intrinsic_rise : 4.22;
|
|
intrinsic_fall : 4.22;
|
|
}
|
|
timing() {
|
|
timing_type : hold_falling;
|
|
related_pin : "clock_n";
|
|
intrinsic_rise : 0.00;
|
|
intrinsic_fall : 0.00;
|
|
}
|
|
timing() {
|
|
timing_type : setup_rising;
|
|
related_pin : "extclk";
|
|
intrinsic_rise : 6.22;
|
|
intrinsic_fall : 6.22;
|
|
}
|
|
timing() {
|
|
timing_type : hold_rising;
|
|
related_pin : "extclk";
|
|
intrinsic_rise : 0.00;
|
|
intrinsic_fall : 0.00;
|
|
}
|
|
timing() {
|
|
timing_type : setup_falling;
|
|
related_pin : "extclk_n";
|
|
intrinsic_rise : 6.22;
|
|
intrinsic_fall : 6.22;
|
|
}
|
|
timing() {
|
|
timing_type : hold_falling;
|
|
related_pin : "extclk_n";
|
|
intrinsic_rise : 0.00;
|
|
intrinsic_fall : 0.00;
|
|
}
|
|
}
|
|
pin (enable) {
|
|
direction : input;
|
|
timing() {
|
|
timing_type : setup_rising;
|
|
related_pin : "clock";
|
|
intrinsic_rise : 3.34;
|
|
intrinsic_fall : 3.34;
|
|
}
|
|
timing() {
|
|
timing_type : hold_rising;
|
|
related_pin : "clock";
|
|
intrinsic_rise : 0.00;
|
|
intrinsic_fall : 0.00;
|
|
}
|
|
timing() {
|
|
timing_type : setup_falling;
|
|
related_pin : "clock_n";
|
|
intrinsic_rise : 3.34;
|
|
intrinsic_fall : 3.34;
|
|
}
|
|
timing() {
|
|
timing_type : hold_falling;
|
|
related_pin : "clock_n";
|
|
intrinsic_rise : 0.00;
|
|
intrinsic_fall : 0.00;
|
|
}
|
|
timing() {
|
|
timing_type : setup_rising;
|
|
related_pin : "extclk";
|
|
intrinsic_rise : 5.34;
|
|
intrinsic_fall : 5.34;
|
|
}
|
|
timing() {
|
|
timing_type : hold_rising;
|
|
related_pin : "extclk";
|
|
intrinsic_rise : 0.00;
|
|
intrinsic_fall : 0.00;
|
|
}
|
|
timing() {
|
|
timing_type : setup_falling;
|
|
related_pin : "extclk_n";
|
|
intrinsic_rise : 5.34;
|
|
intrinsic_fall : 5.34;
|
|
}
|
|
timing() {
|
|
timing_type : hold_falling;
|
|
related_pin : "extclk_n";
|
|
intrinsic_rise : 0.00;
|
|
intrinsic_fall : 0.00;
|
|
}
|
|
}
|
|
bundle (count) {
|
|
members (count_0, count_1, count_2, count_3, count_4, count_5, count_6);
|
|
direction : output;
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : "clock";
|
|
intrinsic_rise : 2.11;
|
|
intrinsic_fall : 2.11;
|
|
}
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : "clock";
|
|
intrinsic_rise : 1.92;
|
|
intrinsic_fall : 1.92;
|
|
}
|
|
timing() {
|
|
timing_type : falling_edge;
|
|
related_pin : "clock_n";
|
|
intrinsic_rise : 2.11;
|
|
intrinsic_fall : 2.11;
|
|
}
|
|
timing() {
|
|
timing_type : falling_edge;
|
|
related_pin : "clock_n";
|
|
intrinsic_rise : 1.92;
|
|
intrinsic_fall : 1.92;
|
|
}
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : "extclk";
|
|
intrinsic_rise : 4.11;
|
|
intrinsic_fall : 4.11;
|
|
}
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : "extclk";
|
|
intrinsic_rise : 3.92;
|
|
intrinsic_fall : 3.92;
|
|
}
|
|
timing() {
|
|
timing_type : falling_edge;
|
|
related_pin : "extclk_n";
|
|
intrinsic_rise : 4.11;
|
|
intrinsic_fall : 4.11;
|
|
}
|
|
timing() {
|
|
timing_type : falling_edge;
|
|
related_pin : "extclk_n";
|
|
intrinsic_rise : 3.92;
|
|
intrinsic_fall : 3.92;
|
|
}
|
|
timing() {
|
|
timing_type : clear;
|
|
timing_sense : negative_unate;
|
|
related_pin : "reset";
|
|
intrinsic_rise : 7.57;
|
|
intrinsic_fall : 7.57;
|
|
}
|
|
timing() {
|
|
timing_type : clear;
|
|
timing_sense : negative_unate;
|
|
related_pin : "reset";
|
|
intrinsic_rise : 6.24;
|
|
intrinsic_fall : 6.24;
|
|
}
|
|
}
|
|
pin (tc) {
|
|
direction : output;
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : "clock";
|
|
intrinsic_rise : 3.58;
|
|
intrinsic_fall : 3.58;
|
|
}
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : "clock";
|
|
intrinsic_rise : 2.04;
|
|
intrinsic_fall : 2.04;
|
|
}
|
|
timing() {
|
|
timing_type : falling_edge;
|
|
related_pin : "clock_n";
|
|
intrinsic_rise : 3.58;
|
|
intrinsic_fall : 3.58;
|
|
}
|
|
timing() {
|
|
timing_type : falling_edge;
|
|
related_pin : "clock_n";
|
|
intrinsic_rise : 2.04;
|
|
intrinsic_fall : 2.04;
|
|
}
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : "extclk";
|
|
intrinsic_rise : 5.58;
|
|
intrinsic_fall : 5.58;
|
|
}
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : "extclk";
|
|
intrinsic_rise : 4.04;
|
|
intrinsic_fall : 4.04;
|
|
}
|
|
timing() {
|
|
timing_type : falling_edge;
|
|
related_pin : "extclk_n";
|
|
intrinsic_rise : 5.58;
|
|
intrinsic_fall : 5.58;
|
|
}
|
|
timing() {
|
|
timing_type : falling_edge;
|
|
related_pin : "extclk_n";
|
|
intrinsic_rise : 4.04;
|
|
intrinsic_fall : 4.04;
|
|
}
|
|
timing() {
|
|
timing_type : preset;
|
|
timing_sense : positive_unate;
|
|
related_pin : "reset";
|
|
intrinsic_rise : 8.02;
|
|
intrinsic_fall : 8.02;
|
|
}
|
|
timing() {
|
|
timing_type : preset;
|
|
timing_sense : positive_unate;
|
|
related_pin : "reset";
|
|
intrinsic_rise : 6.19;
|
|
intrinsic_fall : 6.19;
|
|
}
|
|
}
|
|
}
|
|
|
|
cell (synccell) {
|
|
pin (clock) {
|
|
direction : input;
|
|
clock : true;
|
|
}
|
|
|
|
pin (clock_n) {
|
|
direction : input;
|
|
clock : true;
|
|
}
|
|
|
|
pin (extclk) {
|
|
direction : input;
|
|
clock : true;
|
|
}
|
|
|
|
pin (extclk_n) {
|
|
direction : input;
|
|
clock : true;
|
|
}
|
|
|
|
pin (clk_en) {
|
|
direction : input;
|
|
timing() {
|
|
timing_type : setup_rising;
|
|
related_pin : "clock";
|
|
intrinsic_rise : 2.1;
|
|
intrinsic_fall : 2.1;
|
|
}
|
|
timing() {
|
|
timing_type : hold_rising;
|
|
related_pin : "clock";
|
|
intrinsic_rise : 0.00;
|
|
intrinsic_fall : 0.00;
|
|
}
|
|
timing() {
|
|
timing_type : setup_falling;
|
|
related_pin : "clock_n";
|
|
intrinsic_rise : 2.1;
|
|
intrinsic_fall : 2.1;
|
|
}
|
|
timing() {
|
|
timing_type : hold_falling;
|
|
related_pin : "clock_n";
|
|
intrinsic_rise : 0.00;
|
|
intrinsic_fall : 0.00;
|
|
}
|
|
timing() {
|
|
timing_type : setup_rising;
|
|
related_pin : "extclk";
|
|
intrinsic_rise : 0;
|
|
intrinsic_fall : 0;
|
|
}
|
|
timing() {
|
|
timing_type : hold_rising;
|
|
related_pin : "extclk";
|
|
intrinsic_rise : 0.6;
|
|
intrinsic_fall : 0.6;
|
|
}
|
|
timing() {
|
|
timing_type : setup_falling;
|
|
related_pin : "extclk_n";
|
|
intrinsic_rise : 0;
|
|
intrinsic_fall : 0;
|
|
}
|
|
timing() {
|
|
timing_type : hold_falling;
|
|
related_pin : "extclk_n";
|
|
intrinsic_rise : 0.6;
|
|
intrinsic_fall : 0.6;
|
|
}
|
|
}
|
|
|
|
pin (in) {
|
|
direction : input;
|
|
}
|
|
|
|
pin (out) {
|
|
direction : output;
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : "clock"
|
|
intrinsic_rise : 1.48;
|
|
intrinsic_fall : 1.48;
|
|
}
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : "clock"
|
|
intrinsic_rise : 1;
|
|
intrinsic_fall : 1;
|
|
}
|
|
timing() {
|
|
timing_type : falling_edge;
|
|
related_pin : "clock_n"
|
|
intrinsic_rise : 1.48;
|
|
intrinsic_fall : 1.48;
|
|
}
|
|
timing() {
|
|
timing_type : falling_edge;
|
|
related_pin : "clock_n"
|
|
intrinsic_rise : 1;
|
|
intrinsic_fall : 1;
|
|
}
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : "extclk"
|
|
intrinsic_rise : 3.48;
|
|
intrinsic_fall : 3.48;
|
|
}
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : "extclk"
|
|
intrinsic_rise : 3;
|
|
intrinsic_fall : 3;
|
|
}
|
|
timing() {
|
|
timing_type : falling_edge;
|
|
related_pin : "extclk_n"
|
|
intrinsic_rise : 3.48;
|
|
intrinsic_fall : 3.48;
|
|
}
|
|
timing() {
|
|
timing_type : falling_edge;
|
|
related_pin : "extclk_n"
|
|
intrinsic_rise : 3;
|
|
intrinsic_fall : 3;
|
|
}
|
|
}
|
|
}
|
|
|
|
cell (sarcell) {
|
|
pin (clock) { direction : input; }
|
|
pin (clk_udb) { direction : input; }
|
|
pin (sof_udb) { direction : input; }
|
|
pin (vp_ctl_udb_0) { direction : input; }
|
|
pin (vp_ctl_udb_1) { direction : input; }
|
|
pin (vp_ctl_udb_2) { direction : input; }
|
|
pin (vp_ctl_udb_3) { direction : input; }
|
|
pin (vn_ctl_udb_0) { direction : input; }
|
|
pin (vn_ctl_udb_1) { direction : input; }
|
|
pin (vn_ctl_udb_2) { direction : input; }
|
|
pin (vn_ctl_udb_3) { direction : input; }
|
|
pin (data_out_udb_0) { direction : output; }
|
|
pin (data_out_udb_1) { direction : output; }
|
|
pin (data_out_udb_2) { direction : output; }
|
|
pin (data_out_udb_3) { direction : output; }
|
|
pin (data_out_udb_4) { direction : output; }
|
|
pin (data_out_udb_5) { direction : output; }
|
|
pin (data_out_udb_6) { direction : output; }
|
|
pin (data_out_udb_7) { direction : output; }
|
|
pin (data_out_udb_8) { direction : output; }
|
|
pin (data_out_udb_9) { direction : output; }
|
|
pin (data_out_udb_10) { direction : output; }
|
|
pin (data_out_udb_11) { direction : output; }
|
|
pin (eof_udb) { direction : output; }
|
|
pin (irq) { direction : output; }
|
|
}
|
|
|
|
cell (ssccell) {
|
|
pin (rst_n) { direction : input; }
|
|
pin (scli) { direction : input; }
|
|
pin (sdai) { direction : input; }
|
|
pin (csel) { direction : input; }
|
|
pin (sclo) { direction : output; }
|
|
pin (sdao) { direction : output; }
|
|
pin (irq) { direction : output; }
|
|
}
|
|
|
|
cell (m0s8lcdcell) {
|
|
bundle (com) {
|
|
members (com_0, com_1, com_2, com_3,
|
|
com_4, com_5, com_6, com_7,
|
|
com_8, com_9, com_10, com_11,
|
|
com_12, com_13, com_14, com_15);
|
|
direction : output;
|
|
}
|
|
bundle (seg) {
|
|
members (seg_0, seg_1, seg_2, seg_3,
|
|
seg_4, seg_5, seg_6, seg_7,
|
|
seg_8, seg_9, seg_10, seg_11,
|
|
seg_12, seg_13, seg_14, seg_15,
|
|
seg_16, seg_17, seg_18, seg_19,
|
|
seg_20, seg_21, seg_22, seg_23,
|
|
seg_24, seg_25, seg_26, seg_27,
|
|
seg_28, seg_29, seg_30, seg_31,
|
|
seg_32, seg_33, seg_34, seg_35,
|
|
seg_36, seg_37, seg_38, seg_39,
|
|
seg_40, seg_41, seg_42, seg_43,
|
|
seg_44, seg_45, seg_46, seg_47,
|
|
seg_48, seg_49, seg_50, seg_51,
|
|
seg_52, seg_53, seg_54, seg_55,
|
|
seg_56, seg_57, seg_58, seg_59,
|
|
seg_60, seg_61, seg_62, seg_63);
|
|
direction : output;
|
|
}
|
|
pin (clock) {
|
|
direction : input;
|
|
clock : true;
|
|
}
|
|
}
|
|
|
|
cell (m0s8scbcell) {
|
|
pin (clock) {
|
|
direction : input;
|
|
clock : true;
|
|
}
|
|
pin (interrupt) {
|
|
direction : output;
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : "clock";
|
|
intrinsic_rise : 0.0;
|
|
intrinsic_fall : 0.0;
|
|
}
|
|
}
|
|
pin (cts) { direction : input; }
|
|
pin (rts) { direction : output; }
|
|
pin (rx) { direction : input; }
|
|
pin (tx) { direction : output; }
|
|
pin (mosi_m) { direction : output; }
|
|
pin (miso_m) { direction : input; }
|
|
bundle (select) {
|
|
members (select_m_0, select_m_1, select_m_2, select_m_3);
|
|
direction : output;
|
|
}
|
|
pin (sclk_m) { direction : output; }
|
|
pin (mosi_s) { direction : input; }
|
|
pin (miso_s) { direction : output; }
|
|
pin (select_s) { direction : input; }
|
|
pin (sclk_s) { direction : input; }
|
|
pin (scl) { direction : inout; }
|
|
pin (sda) { direction : inout; }
|
|
pin (rx_req) { direction : output; }
|
|
pin (tx_req) { direction : output; }
|
|
}
|
|
|
|
cell (m0s8tcpwmcell) {
|
|
pin (clock) {
|
|
direction : input;
|
|
clock : true;
|
|
}
|
|
pin (capture) { direction : input; }
|
|
pin (count) { direction : input; }
|
|
pin (reload) { direction : input; }
|
|
pin (stop) { direction : input; }
|
|
pin (start) { direction : input; }
|
|
pin (tr_underflow) {
|
|
direction : output;
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : clock;
|
|
intrinsic_rise : 0.0;
|
|
intrinsic_fall : 0.0;
|
|
}
|
|
}
|
|
pin (tr_overflow) {
|
|
direction : output;
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : clock;
|
|
intrinsic_rise : 0.0;
|
|
intrinsic_fall : 0.0;
|
|
}
|
|
}
|
|
pin (tr_compare_match) {
|
|
direction : output;
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : clock;
|
|
intrinsic_rise : 0.0;
|
|
intrinsic_fall : 0.0;
|
|
}
|
|
}
|
|
pin (line_out) {
|
|
direction : output;
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : clock;
|
|
intrinsic_rise : 0.0;
|
|
intrinsic_fall : 0.0;
|
|
}
|
|
}
|
|
pin (line_out_compl) {
|
|
direction : output;
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : clock;
|
|
intrinsic_rise : 0.0;
|
|
intrinsic_fall : 0.0;
|
|
}
|
|
}
|
|
pin (interrupt) { direction : output; }
|
|
}
|
|
|
|
cell (m0s8tsscell) {
|
|
/* TODO: names don't match DSI file */
|
|
pin (clk_seq) { direction : input; clock : true; }
|
|
pin (clk_adc) { direction : input; clock : true; }
|
|
|
|
/* Non-routable, optional, pin inputs */
|
|
pin (ext_reject) { direction : input; }
|
|
pin (ext_sync) { direction : input; }
|
|
|
|
/* DSI input or fixed clock input */
|
|
pin (tx_sync) { direction : input; clock : true; }
|
|
|
|
/* DSI connections, in */
|
|
pin (reject_in) { direction : input; }
|
|
pin (start_in) { direction : input; }
|
|
|
|
/* DSI connections, out */
|
|
pin (lx_det_hi) { direction : output; }
|
|
pin (lx_det_lo) { direction : output; }
|
|
pin (rej_window) {
|
|
direction : output;
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : "clk_seq";
|
|
intrinsic_rise : 0.0;
|
|
intrinsic_fall : 0.0;
|
|
}
|
|
}
|
|
pin (tx_hilo) {
|
|
direction : output;
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : "clk_seq";
|
|
intrinsic_rise : 0.0;
|
|
intrinsic_fall : 0.0;
|
|
}
|
|
}
|
|
pin (phase_end) {
|
|
direction : output;
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : "clk_seq";
|
|
intrinsic_rise : 0.0;
|
|
intrinsic_fall : 0.0;
|
|
}
|
|
}
|
|
bundle (phase_num) {
|
|
members (phase_num_0, phase_num_1, phase_num_2, phase_num_3);
|
|
direction : output;
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : "clk_seq";
|
|
intrinsic_rise : 0.0;
|
|
intrinsic_fall : 0.0;
|
|
}
|
|
}
|
|
pin (ipq_reject) {
|
|
direction : output;
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : "clk_seq";
|
|
intrinsic_rise : 0.0;
|
|
intrinsic_fall : 0.0;
|
|
}
|
|
}
|
|
pin (ipq_start) {
|
|
direction : output;
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : "clk_seq";
|
|
intrinsic_rise : 0.0;
|
|
intrinsic_fall : 0.0;
|
|
}
|
|
}
|
|
pin (epq_reject) {
|
|
direction : output;
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : "clk_seq";
|
|
intrinsic_rise : 0.0;
|
|
intrinsic_fall : 0.0;
|
|
}
|
|
}
|
|
pin (epq_start) {
|
|
direction : output;
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : "clk_seq";
|
|
intrinsic_rise : 0.0;
|
|
intrinsic_fall : 0.0;
|
|
}
|
|
}
|
|
pin (mcs_reject) {
|
|
direction : output;
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : "clk_seq";
|
|
intrinsic_rise : 0.0;
|
|
intrinsic_fall : 0.0;
|
|
}
|
|
}
|
|
pin (mcs_start) {
|
|
direction : output;
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : "clk_seq";
|
|
intrinsic_rise : 0.0;
|
|
intrinsic_fall : 0.0;
|
|
}
|
|
}
|
|
|
|
pin (do_switch) { direction : output; }
|
|
pin (adc_start) { direction : output; }
|
|
pin (adc_done) { direction : output; }
|
|
}
|
|
|
|
cell (p4sarcell) {
|
|
pin (clock) {
|
|
direction : input;
|
|
clock : true;
|
|
}
|
|
pin (sw_negvref) { direction : input; }
|
|
bundle (cfg_st_sel) {
|
|
members (cfg_st_sel_0, cfg_st_sel_1);
|
|
direction : input;
|
|
}
|
|
pin (cfg_average) { direction : input; }
|
|
pin (cfg_resolution) { direction : input; }
|
|
pin (cfg_differential) { direction : input; }
|
|
pin (data_hilo_sel) { direction : input; }
|
|
pin (trigger) { direction : input; }
|
|
pin (sample_done) {
|
|
direction : output;
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : clock;
|
|
intrinsic_rise : 0.0;
|
|
intrinsic_fall : 0.0;
|
|
}
|
|
}
|
|
pin (chan_id_valid) {
|
|
direction : output;
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : clock;
|
|
intrinsic_rise : 0.0;
|
|
intrinsic_fall : 0.0;
|
|
}
|
|
}
|
|
pin (data_valid) {
|
|
direction : output;
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : clock;
|
|
intrinsic_rise : 0.0;
|
|
intrinsic_fall : 0.0;
|
|
}
|
|
}
|
|
bundle (chan_id) {
|
|
members (chan_id_0, chan_id_1, chan_id_2, chan_id_3);
|
|
direction : output;
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : clock;
|
|
intrinsic_rise : 0.0;
|
|
intrinsic_fall : 0.0;
|
|
}
|
|
}
|
|
bundle (data) {
|
|
members (data_0, data_1, data_2, data_3, data_4, data_5,
|
|
data_6, data_7, data_8, data_9, data_10, data_11);
|
|
direction : output;
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : clock;
|
|
intrinsic_rise : 0.0;
|
|
intrinsic_fall : 0.0;
|
|
}
|
|
}
|
|
pin (eos_intr) {
|
|
direction : output;
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : clock;
|
|
intrinsic_rise : 0.0;
|
|
intrinsic_fall : 0.0;
|
|
}
|
|
}
|
|
pin (tr_sar_out) {
|
|
direction : output;
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : clock;
|
|
intrinsic_rise : 0.0;
|
|
intrinsic_fall : 0.0;
|
|
}
|
|
}
|
|
pin (irq) {
|
|
direction : output;
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : clock;
|
|
intrinsic_rise : 0.0;
|
|
intrinsic_fall : 0.0;
|
|
}
|
|
}
|
|
}
|
|
|
|
cell (p4csdcell) {
|
|
pin (clk1) { direction : input; clock : true; }
|
|
pin (clk2) { direction : input; clock : true; }
|
|
pin (sense_in) { direction : input; }
|
|
pin (sample_in) { direction : input; }
|
|
pin (sense_out) {
|
|
direction : output;
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : "clk2"; /* TODO: this is actually clocked by clk_hf */
|
|
intrinsic_rise : 0.0;
|
|
intrinsic_fall : 0.0;
|
|
}
|
|
}
|
|
pin (sample_out) {
|
|
direction : output;
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : "clk2"; /* TODO: this is actually clocked by clk_sample_o (analog clock) */
|
|
intrinsic_rise : 0.0;
|
|
intrinsic_fall : 0.0;
|
|
}
|
|
}
|
|
pin (irq) {
|
|
direction : output;
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : "clk2"; /* TODO: actual clock not specified */
|
|
intrinsic_rise : 0.0;
|
|
intrinsic_fall : 0.0;
|
|
}
|
|
}
|
|
}
|
|
|
|
cell (p4halfuabcell) {
|
|
pin (clock) { direction : input; clock : true; }
|
|
pin (comp) {
|
|
direction : output;
|
|
/* TODO: add timing arc */
|
|
}
|
|
pin (ctrl) { direction : input; clock : true; }
|
|
}
|
|
|
|
cell (p4csidac8cell) {
|
|
pin (en) { direction : input; }
|
|
}
|
|
|
|
cell (p4csidac7cell) {
|
|
pin (en) { direction : input; }
|
|
}
|
|
|
|
cell (m0s8spcifcell) {
|
|
pin (spcif_int) { direction : output; }
|
|
}
|
|
|
|
cell (m0s8wdtcell) {
|
|
pin (wdt_int) { direction : output; }
|
|
}
|
|
|
|
cell (m0s8pmcell) {
|
|
pin (pm_int) { direction : output; }
|
|
}
|
|
|
|
cell (p4lpcompcell) {
|
|
pin (cmpout) { direction : output; }
|
|
}
|
|
|
|
cell (p4lpcompblockcell) {
|
|
pin (interrupt) { direction : output; }
|
|
}
|
|
|
|
cell (p4ctbmblockcell) {
|
|
pin (interrupt) { direction : output; }
|
|
}
|
|
|
|
cell (p4abufcell) {
|
|
pin (ctb_dsi_comp) { direction : output; }
|
|
pin (dsi_out) { direction : input; }
|
|
}
|
|
|
|
cell (p4anapumpcell) {
|
|
pin (pump_clock) { direction : input; }
|
|
}
|
|
|
|
cell (p4blecell) {
|
|
pin (interrupt) { direction : output; }
|
|
pin (rfctrl_extpa_en) { direction : output; }
|
|
}
|
|
|
|
cell (m0s8gangedpicucell) {
|
|
pin (interrupt) { direction : output; }
|
|
}
|
|
|
|
cell (m0s8dmacell) {
|
|
pin (interrupt) { direction : output; }
|
|
}
|
|
|
|
cell (cancell) {
|
|
pin (clock) { direction : input; clock: true; }
|
|
pin (can_rx) { direction : input; }
|
|
pin (can_tx) { direction : output; }
|
|
pin (can_tx_en) {
|
|
direction : output;
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : "clock";
|
|
intrinsic_rise : 1.0;
|
|
intrinsic_fall : 1.0;
|
|
}
|
|
}
|
|
pin (interrupt) {
|
|
direction : output;
|
|
timing() {
|
|
timing_type : rising_edge;
|
|
related_pin : "clock";
|
|
intrinsic_rise : 1.0;
|
|
intrinsic_fall : 1.0;
|
|
}
|
|
}
|
|
}
|
|
|
|
/*}*/
|